rt2560.c revision 3a1a8936dac0ebe7e956fa122b0b0d15e62d4108
a6d42e7d71324c5193c3b94d57d96ba2925d52e1Peter Dunlap * Copyright 2007 Sun Microsystems, Inc. All rights reserved.
a6d42e7d71324c5193c3b94d57d96ba2925d52e1Peter Dunlap * Use is subject to license terms.
a6d42e7d71324c5193c3b94d57d96ba2925d52e1Peter Dunlap * Copyright (c) 2005, 2006
a6d42e7d71324c5193c3b94d57d96ba2925d52e1Peter Dunlap * Damien Bergamini <damien.bergamini@free.fr>
a6d42e7d71324c5193c3b94d57d96ba2925d52e1Peter Dunlap * Permission to use, copy, modify, and distribute this software for any
a6d42e7d71324c5193c3b94d57d96ba2925d52e1Peter Dunlap * purpose with or without fee is hereby granted, provided that the above
a6d42e7d71324c5193c3b94d57d96ba2925d52e1Peter Dunlap * copyright notice and this permission notice appear in all copies.
a6d42e7d71324c5193c3b94d57d96ba2925d52e1Peter Dunlap * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
a6d42e7d71324c5193c3b94d57d96ba2925d52e1Peter Dunlap * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
a6d42e7d71324c5193c3b94d57d96ba2925d52e1Peter Dunlap * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
a6d42e7d71324c5193c3b94d57d96ba2925d52e1Peter Dunlap * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
a6d42e7d71324c5193c3b94d57d96ba2925d52e1Peter Dunlap * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
a6d42e7d71324c5193c3b94d57d96ba2925d52e1Peter Dunlap * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
a6d42e7d71324c5193c3b94d57d96ba2925d52e1Peter Dunlap * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
a481fa48e4b49ab092647a92bb0ea0edf9afc5ceRick McNeal * Ralink Technology RT2560 chipset driver
a6d42e7d71324c5193c3b94d57d96ba2925d52e1Peter Dunlap#pragma ident "%Z%%M% %I% %E% SMI"
a6d42e7d71324c5193c3b94d57d96ba2925d52e1Peter Dunlap/* quickly determine if a given rate is CCK or OFDM */
a6d42e7d71324c5193c3b94d57d96ba2925d52e1Peter Dunlap#define RAL_RATE_IS_OFDM(rate) ((rate) >= 12 && (rate) != 22)
a6d42e7d71324c5193c3b94d57d96ba2925d52e1Peter Dunlap * Supported rates for 802.11a/b/g modes (in 500Kbps unit).
a6d42e7d71324c5193c3b94d57d96ba2925d52e1Peter Dunlapstatic const struct ieee80211_rateset rt2560_rateset_11a =
a6d42e7d71324c5193c3b94d57d96ba2925d52e1Peter Dunlapstatic const struct ieee80211_rateset rt2560_rateset_11b =
a6d42e7d71324c5193c3b94d57d96ba2925d52e1Peter Dunlapstatic const struct ieee80211_rateset rt2560_rateset_11g =
a6d42e7d71324c5193c3b94d57d96ba2925d52e1Peter Dunlap { 12, { 2, 4, 11, 22, 12, 18, 24, 36, 48, 72, 96, 108 } };
a6d42e7d71324c5193c3b94d57d96ba2925d52e1Peter Dunlapstatic const struct {
a6d42e7d71324c5193c3b94d57d96ba2925d52e1Peter Dunlapstatic const struct {
a6d42e7d71324c5193c3b94d57d96ba2925d52e1Peter Dunlapstatic const uint32_t rt2560_rf2522_r2[] = RT2560_RF2522_R2;
a6d42e7d71324c5193c3b94d57d96ba2925d52e1Peter Dunlapstatic const uint32_t rt2560_rf2523_r2[] = RT2560_RF2523_R2;
a6d42e7d71324c5193c3b94d57d96ba2925d52e1Peter Dunlapstatic const uint32_t rt2560_rf2524_r2[] = RT2560_RF2524_R2;
a6d42e7d71324c5193c3b94d57d96ba2925d52e1Peter Dunlapstatic const uint32_t rt2560_rf2525_r2[] = RT2560_RF2525_R2;
a6d42e7d71324c5193c3b94d57d96ba2925d52e1Peter Dunlapstatic const uint32_t rt2560_rf2525_hi_r2[] = RT2560_RF2525_HI_R2;
a6d42e7d71324c5193c3b94d57d96ba2925d52e1Peter Dunlapstatic const uint32_t rt2560_rf2525e_r2[] = RT2560_RF2525E_R2;
a6d42e7d71324c5193c3b94d57d96ba2925d52e1Peter Dunlapstatic const uint32_t rt2560_rf2526_r2[] = RT2560_RF2526_R2;
a6d42e7d71324c5193c3b94d57d96ba2925d52e1Peter Dunlapstatic const uint32_t rt2560_rf2526_hi_r2[] = RT2560_RF2526_HI_R2;
a6d42e7d71324c5193c3b94d57d96ba2925d52e1Peter Dunlapstatic const struct {
a6d42e7d71324c5193c3b94d57d96ba2925d52e1Peter Dunlap * PIO access attributes for registers
3fc1e17e160b171792527e6238216e3a602e8f8bPriya Krishnanstatic ddi_device_acc_attr_t ral_csr_accattr = {
d618d68dcf9c6c8f2c1e2fbbd4de1de0cf30150ePriya Krishnan * DMA access attributes for descriptors: NOT to be byte swapped.
d618d68dcf9c6c8f2c1e2fbbd4de1de0cf30150ePriya Krishnanstatic ddi_device_acc_attr_t ral_desc_accattr = {
d618d68dcf9c6c8f2c1e2fbbd4de1de0cf30150ePriya Krishnan * Describes the chip's DMA engine
d618d68dcf9c6c8f2c1e2fbbd4de1de0cf30150ePriya Krishnan 0x0000000000000000ull, /* dma_attr_addr_lo */
d618d68dcf9c6c8f2c1e2fbbd4de1de0cf30150ePriya Krishnan 0xFFFFFFFFFFFFFFFFull, /* dma_attr_addr_hi */
d618d68dcf9c6c8f2c1e2fbbd4de1de0cf30150ePriya Krishnan 0x00000000FFFFFFFFull, /* dma_attr_count_max */
d618d68dcf9c6c8f2c1e2fbbd4de1de0cf30150ePriya Krishnan 0x000000000000FFFFull, /* dma_attr_maxxfer */
a6d42e7d71324c5193c3b94d57d96ba2925d52e1Peter Dunlap 0 /* dma_attr_flags */
a6d42e7d71324c5193c3b94d57d96ba2925d52e1Peter Dunlap * device operations
a6d42e7d71324c5193c3b94d57d96ba2925d52e1Peter Dunlapstatic int rt2560_attach(dev_info_t *, ddi_attach_cmd_t);
a6d42e7d71324c5193c3b94d57d96ba2925d52e1Peter Dunlapstatic int rt2560_detach(dev_info_t *, ddi_detach_cmd_t);
a6d42e7d71324c5193c3b94d57d96ba2925d52e1Peter Dunlapstatic int rt2560_reset(dev_info_t *, ddi_reset_cmd_t);
a6d42e7d71324c5193c3b94d57d96ba2925d52e1Peter Dunlap * Module Loading Data & Entry Points
a6d42e7d71324c5193c3b94d57d96ba2925d52e1Peter DunlapDDI_DEFINE_STREAM_OPS(ral_dev_ops, nulldev, nulldev, rt2560_attach,
a6d42e7d71324c5193c3b94d57d96ba2925d52e1Peter Dunlap rt2560_detach, rt2560_reset, NULL, D_MP, NULL);
d618d68dcf9c6c8f2c1e2fbbd4de1de0cf30150ePriya Krishnan &mod_driverops, /* Type of module. This one is a driver */
d618d68dcf9c6c8f2c1e2fbbd4de1de0cf30150ePriya Krishnan "Ralink RT2500 driver v%I%", /* short description */
a6d42e7d71324c5193c3b94d57d96ba2925d52e1Peter Dunlapstatic int rt2560_m_stat(void *, uint_t, uint64_t *);
a6d42e7d71324c5193c3b94d57d96ba2925d52e1Peter Dunlapstatic int rt2560_m_start(void *);
a6d42e7d71324c5193c3b94d57d96ba2925d52e1Peter Dunlapstatic void rt2560_m_stop(void *);
a6d42e7d71324c5193c3b94d57d96ba2925d52e1Peter Dunlapstatic int rt2560_m_multicst(void *, boolean_t, const uint8_t *);
a6d42e7d71324c5193c3b94d57d96ba2925d52e1Peter Dunlapstatic int rt2560_m_unicst(void *, const uint8_t *);
a6d42e7d71324c5193c3b94d57d96ba2925d52e1Peter Dunlapstatic void rt2560_m_ioctl(void *, queue_t *, mblk_t *);
a6d42e7d71324c5193c3b94d57d96ba2925d52e1Peter Dunlapral_debug(uint32_t dbg_flags, const int8_t *fmt, ...)
a6d42e7d71324c5193c3b94d57d96ba2925d52e1Peter Dunlap /* update basic rate set */
a6d42e7d71324c5193c3b94d57d96ba2925d52e1Peter Dunlap /* 11b basic rates: 1, 2Mbps */
a6d42e7d71324c5193c3b94d57d96ba2925d52e1Peter Dunlap } else if (IEEE80211_IS_CHAN_5GHZ(ic->ic_curchan)) {
72cf314316bed51cd2e5fd0cb021a9725316a6b0peter dunlap /* 11a basic rates: 6, 12, 24Mbps */
72cf314316bed51cd2e5fd0cb021a9725316a6b0peter dunlap /* 11g basic rates: 1, 2, 5.5, 11, 6, 12, 24Mbps */
a6d42e7d71324c5193c3b94d57d96ba2925d52e1Peter Dunlaprt2560_update_led(struct rt2560_softc *sc, int led1, int led2)
a6d42e7d71324c5193c3b94d57d96ba2925d52e1Peter Dunlap /* set ON period to 70ms and OFF period to 30ms */
72cf314316bed51cd2e5fd0cb021a9725316a6b0peter dunlaprt2560_set_bssid(struct rt2560_softc *sc, uint8_t *bssid)
72cf314316bed51cd2e5fd0cb021a9725316a6b0peter dunlap tmp = bssid[0] | bssid[1] << 8 | bssid[2] << 16 | bssid[3] << 24;
d618d68dcf9c6c8f2c1e2fbbd4de1de0cf30150ePriya Krishnan RAL_DEBUG(RAL_DBG_HW, "setting BSSID to " MACSTR "\n", MAC2STR(bssid));
d618d68dcf9c6c8f2c1e2fbbd4de1de0cf30150ePriya Krishnanrt2560_bbp_write(struct rt2560_softc *sc, uint8_t reg, uint8_t val)
a6d42e7d71324c5193c3b94d57d96ba2925d52e1Peter Dunlap if (!(RAL_READ(sc, RT2560_BBPCSR) & RT2560_BBP_BUSY))
a6d42e7d71324c5193c3b94d57d96ba2925d52e1Peter Dunlap RAL_DEBUG(RAL_DBG_HW, "could not write to BBP\n");
8c629652ef2aba4749bf59757802cf9a4f1a7571Peter Cudhea - Sun Microsystems - Burlington, MA United States return;
8c629652ef2aba4749bf59757802cf9a4f1a7571Peter Cudhea - Sun Microsystems - Burlington, MA United States }
a6d42e7d71324c5193c3b94d57d96ba2925d52e1Peter Dunlap tmp = RT2560_BBP_WRITE | RT2560_BBP_BUSY | reg << 8 | val;
3fc1e17e160b171792527e6238216e3a602e8f8bPriya Krishnan RAL_DEBUG(RAL_DBG_HW, "BBP R%u <- 0x%02x\n", reg, val);
d618d68dcf9c6c8f2c1e2fbbd4de1de0cf30150ePriya Krishnanrt2560_bbp_read(struct rt2560_softc *sc, uint8_t reg)
8c629652ef2aba4749bf59757802cf9a4f1a7571Peter Cudhea - Sun Microsystems - Burlington, MA United States uint32_t val;
a6d42e7d71324c5193c3b94d57d96ba2925d52e1Peter Dunlap RAL_DEBUG(RAL_DBG_HW, "could not read from BBP\n");
a6d42e7d71324c5193c3b94d57d96ba2925d52e1Peter Dunlaprt2560_rf_write(struct rt2560_softc *sc, uint8_t reg, uint32_t val)
d618d68dcf9c6c8f2c1e2fbbd4de1de0cf30150ePriya Krishnan if (!(RAL_READ(sc, RT2560_RFCSR) & RT2560_RF_BUSY))
8c629652ef2aba4749bf59757802cf9a4f1a7571Peter Cudhea - Sun Microsystems - Burlington, MA United States break;
a6d42e7d71324c5193c3b94d57d96ba2925d52e1Peter Dunlap RAL_DEBUG(RAL_DBG_HW, "could not write to RF\n");
a6d42e7d71324c5193c3b94d57d96ba2925d52e1Peter Dunlap tmp = RT2560_RF_BUSY | RT2560_RF_20BIT | (val & 0xfffff) << 2 |
a6d42e7d71324c5193c3b94d57d96ba2925d52e1Peter Dunlap /* remember last written value in sc */
a6d42e7d71324c5193c3b94d57d96ba2925d52e1Peter Dunlap RAL_DEBUG(RAL_DBG_HW, "RF R[%u] <- 0x%05x\n", reg & 0x3, val & 0xfffff);
a6d42e7d71324c5193c3b94d57d96ba2925d52e1Peter Dunlaprt2560_set_chan(struct rt2560_softc *sc, struct ieee80211_channel *c)
a6d42e7d71324c5193c3b94d57d96ba2925d52e1Peter Dunlap /* adjust txpower using ifconfig settings */
a6d42e7d71324c5193c3b94d57d96ba2925d52e1Peter Dunlap RAL_DEBUG(RAL_DBG_CHAN, "setting channel to %u, txpower to %u\n",
a6d42e7d71324c5193c3b94d57d96ba2925d52e1Peter Dunlap rt2560_rf_write(sc, RAL_RF2, rt2560_rf2522_r2[chan - 1]);
a6d42e7d71324c5193c3b94d57d96ba2925d52e1Peter Dunlap rt2560_rf_write(sc, RAL_RF3, power << 7 | 0x00040);
a6d42e7d71324c5193c3b94d57d96ba2925d52e1Peter Dunlap rt2560_rf_write(sc, RAL_RF2, rt2560_rf2523_r2[chan - 1]);
a6d42e7d71324c5193c3b94d57d96ba2925d52e1Peter Dunlap rt2560_rf_write(sc, RAL_RF3, power << 7 | 0x38044);
a6d42e7d71324c5193c3b94d57d96ba2925d52e1Peter Dunlap rt2560_rf_write(sc, RAL_RF4, (chan == 14) ? 0x00280 : 0x00286);
a6d42e7d71324c5193c3b94d57d96ba2925d52e1Peter Dunlap rt2560_rf_write(sc, RAL_RF2, rt2560_rf2524_r2[chan - 1]);
a6d42e7d71324c5193c3b94d57d96ba2925d52e1Peter Dunlap rt2560_rf_write(sc, RAL_RF3, power << 7 | 0x00040);
a6d42e7d71324c5193c3b94d57d96ba2925d52e1Peter Dunlap rt2560_rf_write(sc, RAL_RF4, (chan == 14) ? 0x00280 : 0x00286);
a6d42e7d71324c5193c3b94d57d96ba2925d52e1Peter Dunlap rt2560_rf_write(sc, RAL_RF2, rt2560_rf2525_hi_r2[chan - 1]);
a6d42e7d71324c5193c3b94d57d96ba2925d52e1Peter Dunlap rt2560_rf_write(sc, RAL_RF3, power << 7 | 0x18044);
a6d42e7d71324c5193c3b94d57d96ba2925d52e1Peter Dunlap rt2560_rf_write(sc, RAL_RF4, (chan == 14) ? 0x00280 : 0x00286);
a6d42e7d71324c5193c3b94d57d96ba2925d52e1Peter Dunlap rt2560_rf_write(sc, RAL_RF2, rt2560_rf2525_r2[chan - 1]);
a6d42e7d71324c5193c3b94d57d96ba2925d52e1Peter Dunlap rt2560_rf_write(sc, RAL_RF3, power << 7 | 0x18044);
a6d42e7d71324c5193c3b94d57d96ba2925d52e1Peter Dunlap rt2560_rf_write(sc, RAL_RF4, (chan == 14) ? 0x00280 : 0x00286);
8c629652ef2aba4749bf59757802cf9a4f1a7571Peter Cudhea - Sun Microsystems - Burlington, MA United States rt2560_rf_write(sc, RAL_RF1, 0x08808);
8c629652ef2aba4749bf59757802cf9a4f1a7571Peter Cudhea - Sun Microsystems - Burlington, MA United States rt2560_rf_write(sc, RAL_RF2, rt2560_rf2525e_r2[chan - 1]);
8c629652ef2aba4749bf59757802cf9a4f1a7571Peter Cudhea - Sun Microsystems - Burlington, MA United States rt2560_rf_write(sc, RAL_RF3, power << 7 | 0x18044);
8c629652ef2aba4749bf59757802cf9a4f1a7571Peter Cudhea - Sun Microsystems - Burlington, MA United States rt2560_rf_write(sc, RAL_RF4, (chan == 14) ? 0x00286 : 0x00282);
8c629652ef2aba4749bf59757802cf9a4f1a7571Peter Cudhea - Sun Microsystems - Burlington, MA United States break;
8c629652ef2aba4749bf59757802cf9a4f1a7571Peter Cudhea - Sun Microsystems - Burlington, MA United States
8c629652ef2aba4749bf59757802cf9a4f1a7571Peter Cudhea - Sun Microsystems - Burlington, MA United States case RT2560_RF_2526:
8c629652ef2aba4749bf59757802cf9a4f1a7571Peter Cudhea - Sun Microsystems - Burlington, MA United States rt2560_rf_write(sc, RAL_RF2, rt2560_rf2526_hi_r2[chan - 1]);
8c629652ef2aba4749bf59757802cf9a4f1a7571Peter Cudhea - Sun Microsystems - Burlington, MA United States rt2560_rf_write(sc, RAL_RF4, (chan & 1) ? 0x00386 : 0x00381);
8c629652ef2aba4749bf59757802cf9a4f1a7571Peter Cudhea - Sun Microsystems - Burlington, MA United States
a6d42e7d71324c5193c3b94d57d96ba2925d52e1Peter Dunlap rt2560_rf_write(sc, RAL_RF2, rt2560_rf2526_r2[chan - 1]);
a6d42e7d71324c5193c3b94d57d96ba2925d52e1Peter Dunlap rt2560_rf_write(sc, RAL_RF3, power << 7 | 0x18044);
a6d42e7d71324c5193c3b94d57d96ba2925d52e1Peter Dunlap rt2560_rf_write(sc, RAL_RF4, (chan & 1) ? 0x00386 : 0x00381);
a6d42e7d71324c5193c3b94d57d96ba2925d52e1Peter Dunlap /* dual-band RF */
a6d42e7d71324c5193c3b94d57d96ba2925d52e1Peter Dunlap for (i = 0; rt2560_rf5222[i].chan != chan; i++) {
8c629652ef2aba4749bf59757802cf9a4f1a7571Peter Cudhea - Sun Microsystems - Burlington, MA United States
a6d42e7d71324c5193c3b94d57d96ba2925d52e1Peter Dunlap rt2560_rf_write(sc, RAL_RF1, rt2560_rf5222[i].r1);
a6d42e7d71324c5193c3b94d57d96ba2925d52e1Peter Dunlap rt2560_rf_write(sc, RAL_RF2, rt2560_rf5222[i].r2);
a6d42e7d71324c5193c3b94d57d96ba2925d52e1Peter Dunlap rt2560_rf_write(sc, RAL_RF3, power << 7 | 0x00040);
a6d42e7d71324c5193c3b94d57d96ba2925d52e1Peter Dunlap rt2560_rf_write(sc, RAL_RF4, rt2560_rf5222[i].r4);
a6d42e7d71324c5193c3b94d57d96ba2925d52e1Peter Dunlap /* set Japan filter bit for channel 14 */
a6d42e7d71324c5193c3b94d57d96ba2925d52e1Peter Dunlap /* clear CRC errors */
8c629652ef2aba4749bf59757802cf9a4f1a7571Peter Cudhea - Sun Microsystems - Burlington, MA United States
8c629652ef2aba4749bf59757802cf9a4f1a7571Peter Cudhea - Sun Microsystems - Burlington, MA United States/*
a6d42e7d71324c5193c3b94d57d96ba2925d52e1Peter Dunlap * Refer to IEEE Std 802.11-1999 pp. 123 for more information on TSF
a6d42e7d71324c5193c3b94d57d96ba2925d52e1Peter Dunlap * synchronization.
a6d42e7d71324c5193c3b94d57d96ba2925d52e1Peter Dunlap /* first, disable TSF synchronization */
07a2bfd1dc0b943009fd0adbf34cb344095e378fPeter Cudhea - Sun Microsystems - Burlington, MA United States
07a2bfd1dc0b943009fd0adbf34cb344095e378fPeter Cudhea - Sun Microsystems - Burlington, MA United States logcwmin = 5;
07a2bfd1dc0b943009fd0adbf34cb344095e378fPeter Cudhea - Sun Microsystems - Burlington, MA United States preload = (ic->ic_opmode == IEEE80211_M_STA) ? 384 : 1024;
a6d42e7d71324c5193c3b94d57d96ba2925d52e1Peter Dunlap /* finally, enable TSF synchronization */
8c629652ef2aba4749bf59757802cf9a4f1a7571Peter Cudhea - Sun Microsystems - Burlington, MA United States else
a6d42e7d71324c5193c3b94d57d96ba2925d52e1Peter Dunlap RAL_DEBUG(RAL_DBG_HW, "enabling TSF synchronization\n");
8c629652ef2aba4749bf59757802cf9a4f1a7571Peter Cudhea - Sun Microsystems - Burlington, MA United States struct ieee80211com *ic = &sc->sc_ic;
a6d42e7d71324c5193c3b94d57d96ba2925d52e1Peter Dunlap /* no short preamble for 1Mbps */
a6d42e7d71324c5193c3b94d57d96ba2925d52e1Peter Dunlap if (!(ic->ic_flags & IEEE80211_F_SHPREAMBLE)) {
a6d42e7d71324c5193c3b94d57d96ba2925d52e1Peter Dunlap /* values taken from the reference driver */
8c629652ef2aba4749bf59757802cf9a4f1a7571Peter Cudhea - Sun Microsystems - Burlington, MA United States /* same values as above or'ed 0x8 */
8c629652ef2aba4749bf59757802cf9a4f1a7571Peter Cudhea - Sun Microsystems - Burlington, MA United States RAL_DEBUG(RAL_DBG_HW, "updating PLCP for %s preamble\n",
a6d42e7d71324c5193c3b94d57d96ba2925d52e1Peter Dunlap (ic->ic_flags & IEEE80211_F_SHPREAMBLE) ? "short" : "long");
a6d42e7d71324c5193c3b94d57d96ba2925d52e1Peter Dunlap * This function can be called by ieee80211_set_shortslottime(). Refer to
a6d42e7d71324c5193c3b94d57d96ba2925d52e1Peter Dunlap * IEEE Std 802.11-1999 pp. 85 to know how these values are computed.
a6d42e7d71324c5193c3b94d57d96ba2925d52e1Peter Dunlaprt2560_update_slot(struct ieee80211com *ic, int onoff)
8c629652ef2aba4749bf59757802cf9a4f1a7571Peter Cudhea - Sun Microsystems - Burlington, MA United States struct rt2560_softc *sc = (struct rt2560_softc *)ic;
a6d42e7d71324c5193c3b94d57d96ba2925d52e1Peter Dunlap /* slottime = (ic->ic_flags & IEEE80211_F_SHSLOT) ? 9 : 20; */
07a2bfd1dc0b943009fd0adbf34cb344095e378fPeter Cudhea - Sun Microsystems - Burlington, MA United States
a6d42e7d71324c5193c3b94d57d96ba2925d52e1Peter Dunlap /* update the MAC slot boundaries */
07a2bfd1dc0b943009fd0adbf34cb344095e378fPeter Cudhea - Sun Microsystems - Burlington, MA United States tx_difs = tx_sifs + 2 * slottime;
07a2bfd1dc0b943009fd0adbf34cb344095e378fPeter Cudhea - Sun Microsystems - Burlington, MA United States eifs = (ic->ic_curmode == IEEE80211_MODE_11B) ? 364 : 60;
07a2bfd1dc0b943009fd0adbf34cb344095e378fPeter Cudhea - Sun Microsystems - Burlington, MA United States
07a2bfd1dc0b943009fd0adbf34cb344095e378fPeter Cudhea - Sun Microsystems - Burlington, MA United States tmp = RAL_READ(sc, RT2560_CSR11);
07a2bfd1dc0b943009fd0adbf34cb344095e378fPeter Cudhea - Sun Microsystems - Burlington, MA United States RAL_DEBUG(RAL_DBG_HW, "setting slottime to %uus\n", slottime);
07a2bfd1dc0b943009fd0adbf34cb344095e378fPeter Cudhea - Sun Microsystems - Burlington, MA United States}
07a2bfd1dc0b943009fd0adbf34cb344095e378fPeter Cudhea - Sun Microsystems - Burlington, MA United States
07a2bfd1dc0b943009fd0adbf34cb344095e378fPeter Cudhea - Sun Microsystems - Burlington, MA United Statesint
a6d42e7d71324c5193c3b94d57d96ba2925d52e1Peter Dunlapral_dma_region_alloc(struct rt2560_softc *sc, struct dma_region *dr,
fcc214c383d20beb968b623b83d851672e174702Charles Ting size_t size, uint_t alloc_flags, uint_t bind_flags)
a6d42e7d71324c5193c3b94d57d96ba2925d52e1Peter Dunlap RAL_DEBUG(RAL_DBG_DMA, "ral_dma_region_alloc() size=%u\n", size);
07a2bfd1dc0b943009fd0adbf34cb344095e378fPeter Cudhea - Sun Microsystems - Burlington, MA United States err = ddi_dma_alloc_handle(dip, &ral_dma_attr, DDI_DMA_SLEEP, NULL,
07a2bfd1dc0b943009fd0adbf34cb344095e378fPeter Cudhea - Sun Microsystems - Burlington, MA United States &dr->dr_hnd);
a6d42e7d71324c5193c3b94d57d96ba2925d52e1Peter Dunlap err = ddi_dma_mem_alloc(dr->dr_hnd, size, &ral_desc_accattr,
07a2bfd1dc0b943009fd0adbf34cb344095e378fPeter Cudhea - Sun Microsystems - Burlington, MA United States err = ddi_dma_addr_bind_handle(dr->dr_hnd, NULL,
07a2bfd1dc0b943009fd0adbf34cb344095e378fPeter Cudhea - Sun Microsystems - Burlington, MA United States dr->dr_base, dr->dr_size,
a6d42e7d71324c5193c3b94d57d96ba2925d52e1Peter Dunlap bind_flags, DDI_DMA_SLEEP, NULL, &dr->dr_cookie, &dr->dr_ccnt);
07a2bfd1dc0b943009fd0adbf34cb344095e378fPeter Cudhea - Sun Microsystems - Burlington, MA United States goto fail3;
07a2bfd1dc0b943009fd0adbf34cb344095e378fPeter Cudhea - Sun Microsystems - Burlington, MA United States
07a2bfd1dc0b943009fd0adbf34cb344095e378fPeter Cudhea - Sun Microsystems - Burlington, MA United States if (dr->dr_ccnt != 1) {
07a2bfd1dc0b943009fd0adbf34cb344095e378fPeter Cudhea - Sun Microsystems - Burlington, MA United States err = DDI_FAILURE;
07a2bfd1dc0b943009fd0adbf34cb344095e378fPeter Cudhea - Sun Microsystems - Burlington, MA United States dr->dr_pbase = dr->dr_cookie.dmac_address;
07a2bfd1dc0b943009fd0adbf34cb344095e378fPeter Cudhea - Sun Microsystems - Burlington, MA United States RAL_DEBUG(RAL_DBG_DMA, "get physical-base=0x%08x\n", dr->dr_pbase);
07a2bfd1dc0b943009fd0adbf34cb344095e378fPeter Cudhea - Sun Microsystems - Burlington, MA United States return (DDI_SUCCESS);
07a2bfd1dc0b943009fd0adbf34cb344095e378fPeter Cudhea - Sun Microsystems - Burlington, MA United Statesfail3:
07a2bfd1dc0b943009fd0adbf34cb344095e378fPeter Cudhea - Sun Microsystems - Burlington, MA United States ddi_dma_mem_free(&dr->dr_acc);
07a2bfd1dc0b943009fd0adbf34cb344095e378fPeter Cudhea - Sun Microsystems - Burlington, MA United Statesfail2:
07a2bfd1dc0b943009fd0adbf34cb344095e378fPeter Cudhea - Sun Microsystems - Burlington, MA United States ddi_dma_free_handle(&dr->dr_hnd);
07a2bfd1dc0b943009fd0adbf34cb344095e378fPeter Cudhea - Sun Microsystems - Burlington, MA United Statesfail1:
07a2bfd1dc0b943009fd0adbf34cb344095e378fPeter Cudhea - Sun Microsystems - Burlington, MA United States return (err);
07a2bfd1dc0b943009fd0adbf34cb344095e378fPeter Cudhea - Sun Microsystems - Burlington, MA United States}
a6d42e7d71324c5193c3b94d57d96ba2925d52e1Peter Dunlapral_dma_region_free(struct rt2560_softc *sc, struct dma_region *dr)
8c629652ef2aba4749bf59757802cf9a4f1a7571Peter Cudhea - Sun Microsystems - Burlington, MA United States ddi_dma_free_handle(&dr->dr_hnd);
8c629652ef2aba4749bf59757802cf9a4f1a7571Peter Cudhea - Sun Microsystems - Burlington, MA United States
a6d42e7d71324c5193c3b94d57d96ba2925d52e1Peter Dunlaprt2560_alloc_tx_ring(struct rt2560_softc *sc, struct rt2560_tx_ring *ring,
8c629652ef2aba4749bf59757802cf9a4f1a7571Peter Cudhea - Sun Microsystems - Burlington, MA United States
8c629652ef2aba4749bf59757802cf9a4f1a7571Peter Cudhea - Sun Microsystems - Burlington, MA United States ring->queued = 0;
a6d42e7d71324c5193c3b94d57d96ba2925d52e1Peter Dunlap ring->data = kmem_zalloc(count * (sizeof (struct rt2560_tx_data)),
a6d42e7d71324c5193c3b94d57d96ba2925d52e1Peter Dunlap ring->dr_txbuf = kmem_zalloc(count * (sizeof (struct dma_region)),
8c629652ef2aba4749bf59757802cf9a4f1a7571Peter Cudhea - Sun Microsystems - Burlington, MA United States count * (sizeof (struct rt2560_tx_desc)),
a6d42e7d71324c5193c3b94d57d96ba2925d52e1Peter Dunlap DDI_DMA_CONSISTENT, DDI_DMA_RDWR | DDI_DMA_CONSISTENT);
8c629652ef2aba4749bf59757802cf9a4f1a7571Peter Cudhea - Sun Microsystems - Burlington, MA United States
a6d42e7d71324c5193c3b94d57d96ba2925d52e1Peter Dunlap size = roundup(RAL_TXBUF_SIZE, sc->sc_cachelsz);
8c629652ef2aba4749bf59757802cf9a4f1a7571Peter Cudhea - Sun Microsystems - Burlington, MA United States for (i = 0; i < count; i++) {
a6d42e7d71324c5193c3b94d57d96ba2925d52e1Peter Dunlap err = ral_dma_region_alloc(sc, &ring->dr_txbuf[i], size,
a6d42e7d71324c5193c3b94d57d96ba2925d52e1Peter Dunlap DDI_DMA_STREAMING, DDI_DMA_WRITE | DDI_DMA_STREAMING);
a6d42e7d71324c5193c3b94d57d96ba2925d52e1Peter Dunlap while (i >= 0) {
8c629652ef2aba4749bf59757802cf9a4f1a7571Peter Cudhea - Sun Microsystems - Burlington, MA United States }
8c629652ef2aba4749bf59757802cf9a4f1a7571Peter Cudhea - Sun Microsystems - Burlington, MA United States ring->physaddr = LE_32(ring->dr_desc.dr_pbase);
a6d42e7d71324c5193c3b94d57d96ba2925d52e1Peter Dunlap ring->desc = (struct rt2560_tx_desc *)ring->dr_desc.dr_base;
8c629652ef2aba4749bf59757802cf9a4f1a7571Peter Cudhea - Sun Microsystems - Burlington, MA United States
a6d42e7d71324c5193c3b94d57d96ba2925d52e1Peter Dunlap for (i = 0; i < count; i++) {
07a2bfd1dc0b943009fd0adbf34cb344095e378fPeter Cudhea - Sun Microsystems - Burlington, MA United States ring->desc[i].physaddr = LE_32(ring->dr_txbuf[i].dr_pbase);
8c629652ef2aba4749bf59757802cf9a4f1a7571Peter Cudhea - Sun Microsystems - Burlington, MA United States
07a2bfd1dc0b943009fd0adbf34cb344095e378fPeter Cudhea - Sun Microsystems - Burlington, MA United States return (DDI_SUCCESS);
8c629652ef2aba4749bf59757802cf9a4f1a7571Peter Cudhea - Sun Microsystems - Burlington, MA United Statesfail2:
a6d42e7d71324c5193c3b94d57d96ba2925d52e1Peter Dunlap/* ARGSUSED */
a6d42e7d71324c5193c3b94d57d96ba2925d52e1Peter Dunlaprt2560_reset_tx_ring(struct rt2560_softc *sc, struct rt2560_tx_ring *ring)
a6d42e7d71324c5193c3b94d57d96ba2925d52e1Peter Dunlap ring->count * sizeof (struct rt2560_tx_desc), DDI_DMA_SYNC_FORDEV);
a6d42e7d71324c5193c3b94d57d96ba2925d52e1Peter Dunlaprt2560_free_tx_ring(struct rt2560_softc *sc, struct rt2560_tx_ring *ring)
a6d42e7d71324c5193c3b94d57d96ba2925d52e1Peter Dunlap /* tx buf */
a6d42e7d71324c5193c3b94d57d96ba2925d52e1Peter Dunlap kmem_free(ring->data, ring->count * (sizeof (struct rt2560_tx_data)));
a6d42e7d71324c5193c3b94d57d96ba2925d52e1Peter Dunlap kmem_free(ring->dr_txbuf, ring->count * (sizeof (struct dma_region)));
a6d42e7d71324c5193c3b94d57d96ba2925d52e1Peter Dunlap /* setup tx rings */
a6d42e7d71324c5193c3b94d57d96ba2925d52e1Peter Dunlap tmp = ((uint32_t)RT2560_PRIO_RING_COUNT << 24) |
a6d42e7d71324c5193c3b94d57d96ba2925d52e1Peter Dunlap /* rings must be initialized in this exact order */
a6d42e7d71324c5193c3b94d57d96ba2925d52e1Peter Dunlap RAL_WRITE(sc, RT2560_TXCSR3, sc->txq.physaddr);
a6d42e7d71324c5193c3b94d57d96ba2925d52e1Peter Dunlap RAL_WRITE(sc, RT2560_TXCSR5, sc->prioq.physaddr);
a6d42e7d71324c5193c3b94d57d96ba2925d52e1Peter Dunlap /* setup rx ring */
a6d42e7d71324c5193c3b94d57d96ba2925d52e1Peter Dunlap tmp = RT2560_RX_RING_COUNT << 8 | RT2560_RX_DESC_SIZE;
a6d42e7d71324c5193c3b94d57d96ba2925d52e1Peter Dunlap RAL_WRITE(sc, RT2560_RXCSR2, sc->rxq.physaddr);
a6d42e7d71324c5193c3b94d57d96ba2925d52e1Peter Dunlaprt2560_alloc_rx_ring(struct rt2560_softc *sc, struct rt2560_rx_ring *ring,
a6d42e7d71324c5193c3b94d57d96ba2925d52e1Peter Dunlap ring->data = kmem_zalloc(count * (sizeof (struct rt2560_rx_data)),
a6d42e7d71324c5193c3b94d57d96ba2925d52e1Peter Dunlap ring->dr_rxbuf = kmem_zalloc(count * (sizeof (struct dma_region)),
a6d42e7d71324c5193c3b94d57d96ba2925d52e1Peter Dunlap DDI_DMA_CONSISTENT, DDI_DMA_RDWR | DDI_DMA_CONSISTENT);
a6d42e7d71324c5193c3b94d57d96ba2925d52e1Peter Dunlap size = roundup(RAL_RXBUF_SIZE, sc->sc_cachelsz);
a6d42e7d71324c5193c3b94d57d96ba2925d52e1Peter Dunlap for (i = 0; i < count; i++) {
a6d42e7d71324c5193c3b94d57d96ba2925d52e1Peter Dunlap err = ral_dma_region_alloc(sc, &ring->dr_rxbuf[i], size,
a6d42e7d71324c5193c3b94d57d96ba2925d52e1Peter Dunlap DDI_DMA_STREAMING, DDI_DMA_READ | DDI_DMA_STREAMING);
a6d42e7d71324c5193c3b94d57d96ba2925d52e1Peter Dunlap while (i >= 0) {
a6d42e7d71324c5193c3b94d57d96ba2925d52e1Peter Dunlap ring->desc = (struct rt2560_rx_desc *)ring->dr_desc.dr_base;
a6d42e7d71324c5193c3b94d57d96ba2925d52e1Peter Dunlap for (i = 0; i < count; i++) {
a6d42e7d71324c5193c3b94d57d96ba2925d52e1Peter Dunlap desc->physaddr = LE_32(ring->dr_rxbuf[i].dr_pbase);
a6d42e7d71324c5193c3b94d57d96ba2925d52e1Peter Dunlap/* ARGSUSED */
a6d42e7d71324c5193c3b94d57d96ba2925d52e1Peter Dunlaprt2560_reset_rx_ring(struct rt2560_softc *sc, struct rt2560_rx_ring *ring)
a6d42e7d71324c5193c3b94d57d96ba2925d52e1Peter Dunlaprt2560_free_rx_ring(struct rt2560_softc *sc, struct rt2560_rx_ring *ring)
a6d42e7d71324c5193c3b94d57d96ba2925d52e1Peter Dunlap /* rx buf */
a6d42e7d71324c5193c3b94d57d96ba2925d52e1Peter Dunlap kmem_free(ring->data, ring->count * (sizeof (struct rt2560_rx_data)));
a6d42e7d71324c5193c3b94d57d96ba2925d52e1Peter Dunlap kmem_free(ring->dr_rxbuf, ring->count * (sizeof (struct dma_region)));
a6d42e7d71324c5193c3b94d57d96ba2925d52e1Peter Dunlap/* ARGSUSED */
a6d42e7d71324c5193c3b94d57d96ba2925d52e1Peter Dunlap rn = kmem_zalloc(sizeof (struct rt2560_node), KM_SLEEP);
a6d42e7d71324c5193c3b94d57d96ba2925d52e1Peter Dunlap * This function is called periodically (every 200ms) during scanning to
a6d42e7d71324c5193c3b94d57d96ba2925d52e1Peter Dunlap * switch from one channel to another.
a6d42e7d71324c5193c3b94d57d96ba2925d52e1Peter Dunlap * This function is called for each node present in the node station table.
a6d42e7d71324c5193c3b94d57d96ba2925d52e1Peter Dunlap/* ARGSUSED */
a6d42e7d71324c5193c3b94d57d96ba2925d52e1Peter Dunlaprt2560_iter_func(void *arg, struct ieee80211_node *ni)
a6d42e7d71324c5193c3b94d57d96ba2925d52e1Peter Dunlap struct rt2560_node *rn = (struct rt2560_node *)ni;
a6d42e7d71324c5193c3b94d57d96ba2925d52e1Peter Dunlap * This function is called periodically (every 100ms) in RUN state to update
a6d42e7d71324c5193c3b94d57d96ba2925d52e1Peter Dunlap * the rate adaptation statistics.
a6d42e7d71324c5193c3b94d57d96ba2925d52e1Peter Dunlap ieee80211_iterate_nodes(&ic->ic_sta, rt2560_iter_func, arg);
a6d42e7d71324c5193c3b94d57d96ba2925d52e1Peter Dunlap sc->sc_rssadapt_id = timeout(rt2560_update_rssadapt, (void *)sc,
a6d42e7d71324c5193c3b94d57d96ba2925d52e1Peter Dunlap RAL_DEBUG(RAL_DBG_MSG, "rt2560_statedog(...)\n");
8c629652ef2aba4749bf59757802cf9a4f1a7571Peter Cudhea - Sun Microsystems - Burlington, MA United States
8c629652ef2aba4749bf59757802cf9a4f1a7571Peter Cudhea - Sun Microsystems - Burlington, MA United States RAL_UNLOCK(sc);
8c629652ef2aba4749bf59757802cf9a4f1a7571Peter Cudhea - Sun Microsystems - Burlington, MA United States
8c629652ef2aba4749bf59757802cf9a4f1a7571Peter Cudhea - Sun Microsystems - Burlington, MA United States ieee80211_new_state(ic, state, -1);
8c629652ef2aba4749bf59757802cf9a4f1a7571Peter Cudhea - Sun Microsystems - Burlington, MA United States
8c629652ef2aba4749bf59757802cf9a4f1a7571Peter Cudhea - Sun Microsystems - Burlington, MA United States}
8c629652ef2aba4749bf59757802cf9a4f1a7571Peter Cudhea - Sun Microsystems - Burlington, MA United States
8c629652ef2aba4749bf59757802cf9a4f1a7571Peter Cudhea - Sun Microsystems - Burlington, MA United Statesstatic int
8c629652ef2aba4749bf59757802cf9a4f1a7571Peter Cudhea - Sun Microsystems - Burlington, MA United Statesrt2560_newstate(struct ieee80211com *ic, enum ieee80211_state nstate, int arg)
8c629652ef2aba4749bf59757802cf9a4f1a7571Peter Cudhea - Sun Microsystems - Burlington, MA United States{
8c629652ef2aba4749bf59757802cf9a4f1a7571Peter Cudhea - Sun Microsystems - Burlington, MA United States struct rt2560_softc *sc = (struct rt2560_softc *)ic;
8c629652ef2aba4749bf59757802cf9a4f1a7571Peter Cudhea - Sun Microsystems - Burlington, MA United States enum ieee80211_state ostate;
a6d42e7d71324c5193c3b94d57d96ba2925d52e1Peter Dunlap /* abort TSF synchronization */
a6d42e7d71324c5193c3b94d57d96ba2925d52e1Peter Dunlap /* turn association led off */
a6d42e7d71324c5193c3b94d57d96ba2925d52e1Peter Dunlap sc->sc_scan_id = timeout(rt2560_next_scan, (void *)sc,
d618d68dcf9c6c8f2c1e2fbbd4de1de0cf30150ePriya Krishnan RAL_DEBUG(RAL_DBG_STATE, "-> IEEE80211_S_AUTH ...\n");
a6d42e7d71324c5193c3b94d57d96ba2925d52e1Peter Dunlap RAL_DEBUG(RAL_DBG_STATE, "-> IEEE80211_S_ASSOC ...\n");
a6d42e7d71324c5193c3b94d57d96ba2925d52e1Peter Dunlap sc->sc_state_id = timeout(rt2560_statedog, (void *)sc,
a6d42e7d71324c5193c3b94d57d96ba2925d52e1Peter Dunlap RAL_DEBUG(RAL_DBG_STATE, "-> IEEE80211_S_RUN ...\n");
a6d42e7d71324c5193c3b94d57d96ba2925d52e1Peter Dunlap /* turn assocation led on */
a481fa48e4b49ab092647a92bb0ea0edf9afc5ceRick McNeal sc->sc_rssadapt_id = timeout(rt2560_update_rssadapt,
a481fa48e4b49ab092647a92bb0ea0edf9afc5ceRick McNeal * Finally, start any timers.
a6d42e7d71324c5193c3b94d57d96ba2925d52e1Peter Dunlap * Read 16 bits at address 'addr' from the serial EEPROM (either 93C46 or
a6d42e7d71324c5193c3b94d57d96ba2925d52e1Peter Dunlaprt2560_eeprom_read(struct rt2560_softc *sc, uint8_t addr)
bf604c6405d5cbc4e94e3d0ecc9e6e074ed4ea67Peter Dunlap /* clock C once before the first command */
72cf314316bed51cd2e5fd0cb021a9725316a6b0peter dunlap /* write start bit (1) */
72cf314316bed51cd2e5fd0cb021a9725316a6b0peter dunlap RT2560_EEPROM_CTL(sc, RT2560_S | RT2560_D | RT2560_C);
bf604c6405d5cbc4e94e3d0ecc9e6e074ed4ea67Peter Dunlap /* write READ opcode (10) */
a6d42e7d71324c5193c3b94d57d96ba2925d52e1Peter Dunlap RT2560_EEPROM_CTL(sc, RT2560_S | RT2560_D | RT2560_C);
a6d42e7d71324c5193c3b94d57d96ba2925d52e1Peter Dunlap /* write address (A5-A0 or A7-A0) */
a6d42e7d71324c5193c3b94d57d96ba2925d52e1Peter Dunlap n = (RAL_READ(sc, RT2560_CSR21) & RT2560_93C46) ? 5 : 7;
a6d42e7d71324c5193c3b94d57d96ba2925d52e1Peter Dunlap for (; n >= 0; n--) {
bf604c6405d5cbc4e94e3d0ecc9e6e074ed4ea67Peter Dunlap (((addr >> n) & 1) << RT2560_SHIFT_D) | RT2560_C);
a6d42e7d71324c5193c3b94d57d96ba2925d52e1Peter Dunlap /* read data Q15-Q0 */
a6d42e7d71324c5193c3b94d57d96ba2925d52e1Peter Dunlap for (n = 15; n >= 0; n--) {
a6d42e7d71324c5193c3b94d57d96ba2925d52e1Peter Dunlap val |= ((tmp & RT2560_Q) >> RT2560_SHIFT_Q) << n;
a6d42e7d71324c5193c3b94d57d96ba2925d52e1Peter Dunlap /* clear Chip Select and clock C */
a6d42e7d71324c5193c3b94d57d96ba2925d52e1Peter Dunlap (void) ddi_dma_sync(dr->dr_hnd, 0, count * RT2560_TX_DESC_SIZE,
a6d42e7d71324c5193c3b94d57d96ba2925d52e1Peter Dunlap (LE_32(desc->flags) & RT2560_TX_CIPHER_BUSY) ||
a6d42e7d71324c5193c3b94d57d96ba2925d52e1Peter Dunlap switch (LE_32(desc->flags) & RT2560_TX_RESULT_MASK) {
a6d42e7d71324c5193c3b94d57d96ba2925d52e1Peter Dunlap RAL_DEBUG(RAL_DBG_INTR, "data frame sent success\n");
60220f10412f6a7c5b45f950f6f6aa364658a179Priya Krishnan "data frame sent after %u retries\n",
60220f10412f6a7c5b45f950f6f6aa364658a179Priya Krishnan "sending data frame failed (too much retries)\n");
60220f10412f6a7c5b45f950f6f6aa364658a179Priya Krishnan RAL_DEBUG(RAL_DBG_INTR, "sending data frame failed "
60220f10412f6a7c5b45f950f6f6aa364658a179Priya Krishnan /* descriptor is no longer valid */
60220f10412f6a7c5b45f950f6f6aa364658a179Priya Krishnan RAL_DEBUG(RAL_DBG_INTR, "tx done idx=%u\n", sc->txq.next);
60220f10412f6a7c5b45f950f6f6aa364658a179Priya Krishnan sc->txq.next = (sc->txq.next + 1) % RT2560_TX_RING_COUNT;
a2383ac57dcb38468bc1c213ee2d102d1e9038b1Priya Krishnan sc->txq.queued < (RT2560_TX_RING_COUNT - 32)) {
a2383ac57dcb38468bc1c213ee2d102d1e9038b1Priya Krishnan (void) ddi_dma_sync(dr->dr_hnd, 0, count * RT2560_TX_DESC_SIZE,
a6d42e7d71324c5193c3b94d57d96ba2925d52e1Peter Dunlap (void) ddi_dma_sync(dr->dr_hnd, 0, count * RT2560_TX_DESC_SIZE,
a6d42e7d71324c5193c3b94d57d96ba2925d52e1Peter Dunlap switch (LE_32(desc->flags) & RT2560_TX_RESULT_MASK) {
a6d42e7d71324c5193c3b94d57d96ba2925d52e1Peter Dunlap RAL_DEBUG(RAL_DBG_INTR, "mgt frame sent success\n");
a6d42e7d71324c5193c3b94d57d96ba2925d52e1Peter Dunlap "mgt frame sent after %u retries\n",
72cf314316bed51cd2e5fd0cb021a9725316a6b0peter dunlap "sending mgt frame failed (too much " "retries)\n");
72cf314316bed51cd2e5fd0cb021a9725316a6b0peter dunlap RAL_DEBUG(RAL_DBG_INTR, "sending mgt frame failed "
72cf314316bed51cd2e5fd0cb021a9725316a6b0peter dunlap /* descriptor is no longer valid */
72cf314316bed51cd2e5fd0cb021a9725316a6b0peter dunlap RAL_DEBUG(RAL_DBG_INTR, "prio done idx=%u\n", sc->prioq.next);
72cf314316bed51cd2e5fd0cb021a9725316a6b0peter dunlap sc->prioq.next = (sc->prioq.next + 1) % RT2560_PRIO_RING_COUNT;
60220f10412f6a7c5b45f950f6f6aa364658a179Priya Krishnan (void) ddi_dma_sync(dr->dr_hnd, 0, count * RT2560_TX_DESC_SIZE,
72cf314316bed51cd2e5fd0cb021a9725316a6b0peter dunlap * Some frames were received. Pass them to the hardware cipher engine before
72cf314316bed51cd2e5fd0cb021a9725316a6b0peter dunlap * sending them to the 802.11 layer.
8c629652ef2aba4749bf59757802cf9a4f1a7571Peter Cudhea - Sun Microsystems - Burlington, MA United States
e42a0851889d583925aa3bd2d9bd139189031cb0peter dunlap (void) ddi_dma_sync(dr->dr_hnd, 0, count * RT2560_RX_DESC_SIZE,
8c629652ef2aba4749bf59757802cf9a4f1a7571Peter Cudhea - Sun Microsystems - Burlington, MA United States DDI_DMA_SYNC_FORKERNEL);
8c629652ef2aba4749bf59757802cf9a4f1a7571Peter Cudhea - Sun Microsystems - Burlington, MA United States data = &sc->rxq.data[sc->rxq.cur];
a6d42e7d71324c5193c3b94d57d96ba2925d52e1Peter Dunlap if ((LE_32(desc->flags) & RT2560_RX_PHY_ERROR) ||
72cf314316bed51cd2e5fd0cb021a9725316a6b0peter dunlap * This should not happen since we did not request
a6d42e7d71324c5193c3b94d57d96ba2925d52e1Peter Dunlap * to receive those frames when we filled RXCSR0.
60220f10412f6a7c5b45f950f6f6aa364658a179Priya Krishnan RAL_DEBUG(RAL_DBG_RX, "PHY or CRC error flags 0x%08x\n",
a6d42e7d71324c5193c3b94d57d96ba2925d52e1Peter Dunlap if (((LE_32(desc->flags) >> 16) & 0xfff) > RAL_RXBUF_SIZE) {
a6d42e7d71324c5193c3b94d57d96ba2925d52e1Peter Dunlap if ((len < sizeof (struct ieee80211_frame_min)) ||
a6d42e7d71324c5193c3b94d57d96ba2925d52e1Peter Dunlap RAL_DEBUG(RAL_DBG_RX, "bad frame length=%u\n", len);
a6d42e7d71324c5193c3b94d57d96ba2925d52e1Peter Dunlap " allocate mblk failed.\n");
a6d42e7d71324c5193c3b94d57d96ba2925d52e1Peter Dunlap (void) ddi_dma_sync(dr_bf->dr_hnd, 0, dr_bf->dr_size,
a6d42e7d71324c5193c3b94d57d96ba2925d52e1Peter Dunlap /* give rssi to the rate adatation algorithm */
a6d42e7d71324c5193c3b94d57d96ba2925d52e1Peter Dunlap ral_rssadapt_input(ic, ni, &rn->rssadapt, desc->rssi);
a6d42e7d71324c5193c3b94d57d96ba2925d52e1Peter Dunlap /* send the frame to the 802.11 layer */
a6d42e7d71324c5193c3b94d57d96ba2925d52e1Peter Dunlap (void) ieee80211_input(ic, m, ni, desc->rssi, 0);
a6d42e7d71324c5193c3b94d57d96ba2925d52e1Peter Dunlap /* node is no longer needed */
a6d42e7d71324c5193c3b94d57d96ba2925d52e1Peter Dunlap RAL_DEBUG(RAL_DBG_RX, "rx done idx=%u\n", sc->rxq.cur);
a6d42e7d71324c5193c3b94d57d96ba2925d52e1Peter Dunlap sc->rxq.cur = (sc->rxq.cur + 1) % RT2560_RX_RING_COUNT;
a6d42e7d71324c5193c3b94d57d96ba2925d52e1Peter Dunlap (void) ddi_dma_sync(dr->dr_hnd, 0, count * RT2560_TX_DESC_SIZE,
a6d42e7d71324c5193c3b94d57d96ba2925d52e1Peter Dunlap struct rt2560_softc *sc = (struct rt2560_softc *)data;
a6d42e7d71324c5193c3b94d57d96ba2925d52e1Peter Dunlap * Check if the soft interrupt is triggered by another
a6d42e7d71324c5193c3b94d57d96ba2925d52e1Peter Dunlap * driver at the same level.
a6d42e7d71324c5193c3b94d57d96ba2925d52e1Peter Dunlap * Return the expected ack rate for a frame transmitted at rate `rate'.
a6d42e7d71324c5193c3b94d57d96ba2925d52e1Peter Dunlap * XXX: this should depend on the destination node basic rate set.
a6d42e7d71324c5193c3b94d57d96ba2925d52e1Peter Dunlaprt2560_ack_rate(struct ieee80211com *ic, int rate)
a6d42e7d71324c5193c3b94d57d96ba2925d52e1Peter Dunlap /* CCK rates */
a6d42e7d71324c5193c3b94d57d96ba2925d52e1Peter Dunlap return ((ic->ic_curmode == IEEE80211_MODE_11B) ? 4 : rate);
a6d42e7d71324c5193c3b94d57d96ba2925d52e1Peter Dunlap /* OFDM rates */
a6d42e7d71324c5193c3b94d57d96ba2925d52e1Peter Dunlap return (12);
a6d42e7d71324c5193c3b94d57d96ba2925d52e1Peter Dunlap return (24);
a6d42e7d71324c5193c3b94d57d96ba2925d52e1Peter Dunlap return (48);
d618d68dcf9c6c8f2c1e2fbbd4de1de0cf30150ePriya Krishnan /* default to 1Mbps */
a6d42e7d71324c5193c3b94d57d96ba2925d52e1Peter Dunlap * Compute the duration (in us) needed to transmit `len' bytes at rate `rate'.
a6d42e7d71324c5193c3b94d57d96ba2925d52e1Peter Dunlap * The function automatically determines the operating mode depending on the
a6d42e7d71324c5193c3b94d57d96ba2925d52e1Peter Dunlap * given rate. `flags' indicates whether short preamble is in use or not.
d618d68dcf9c6c8f2c1e2fbbd4de1de0cf30150ePriya Krishnanrt2560_txtime(int len, int rate, uint32_t flags)
d618d68dcf9c6c8f2c1e2fbbd4de1de0cf30150ePriya Krishnan /* IEEE Std 802.11a-1999, pp. 37 */
d618d68dcf9c6c8f2c1e2fbbd4de1de0cf30150ePriya Krishnan txtime = (8 + 4 * len + 3 + rate - 1) / rate;
d618d68dcf9c6c8f2c1e2fbbd4de1de0cf30150ePriya Krishnan /* IEEE Std 802.11b-1999, pp. 28 */
d618d68dcf9c6c8f2c1e2fbbd4de1de0cf30150ePriya Krishnan if (rate != 2 && (flags & IEEE80211_F_SHPREAMBLE))
a6d42e7d71324c5193c3b94d57d96ba2925d52e1Peter Dunlap /* CCK rates (returned values are device-dependent) */
a6d42e7d71324c5193c3b94d57d96ba2925d52e1Peter Dunlap /* OFDM rates (cf IEEE Std 802.11a-1999, pp. 14 Table 80) */
a6d42e7d71324c5193c3b94d57d96ba2925d52e1Peter Dunlap /* unsupported rates (should not get there) */
a6d42e7d71324c5193c3b94d57d96ba2925d52e1Peter Dunlap default: return (0xff);
a6d42e7d71324c5193c3b94d57d96ba2925d52e1Peter Dunlaprt2560_setup_tx_desc(struct rt2560_softc *sc, struct rt2560_tx_desc *desc,
a6d42e7d71324c5193c3b94d57d96ba2925d52e1Peter Dunlap uint32_t flags, int len, int rate, int encrypt)
4142b486074471a886d6d0f0aa625a38b03d4ebaJames Moore desc->flags |= encrypt ? LE_32(RT2560_TX_CIPHER_BUSY) :
a6d42e7d71324c5193c3b94d57d96ba2925d52e1Peter Dunlap /* setup PLCP fields */
47715e7fd18d93fbdad6de94604baaa63665f0fbPriya Krishnan if (rate != 2 && (ic->ic_flags & IEEE80211_F_SHPREAMBLE))
a6d42e7d71324c5193c3b94d57d96ba2925d52e1Peter Dunlap/* ARGSUSED */
a6d42e7d71324c5193c3b94d57d96ba2925d52e1Peter Dunlaprt2560_mgmt_send(ieee80211com_t *ic, mblk_t *mp, uint8_t type)
a6d42e7d71324c5193c3b94d57d96ba2925d52e1Peter Dunlap struct rt2560_softc *sc = (struct rt2560_softc *)ic;
a6d42e7d71324c5193c3b94d57d96ba2925d52e1Peter Dunlap if (sc->prioq.queued >= RT2560_PRIO_RING_COUNT) {
01c0a610793607c653ebeb17728e674bb9d8a851Priya Krishnan RAL_DEBUG(RAL_DBG_TX, "rt2560_mgmt_send: can't alloc mblk.\n");
a6d42e7d71324c5193c3b94d57d96ba2925d52e1Peter Dunlap for (off = 0, m0 = mp; m0 != NULL; m0 = m0->b_cont) {
a6d42e7d71324c5193c3b94d57d96ba2925d52e1Peter Dunlap (void) memcpy(m->b_rptr + off, m0->b_rptr, mblen);
26ec4a22f5c6d9a66aa603d4a2182a2b95d15af9Priya Krishnan /* to support shared_key auth mode */
a6d42e7d71324c5193c3b94d57d96ba2925d52e1Peter Dunlap /* packet header may have moved, reset our local pointer */
a6d42e7d71324c5193c3b94d57d96ba2925d52e1Peter Dunlap rate = IEEE80211_IS_CHAN_5GHZ(ic->ic_curchan) ? 12 : 2;
a6d42e7d71324c5193c3b94d57d96ba2925d52e1Peter Dunlap dur = rt2560_txtime(RAL_ACK_SIZE, rate, ic->ic_flags) +
a6d42e7d71324c5193c3b94d57d96ba2925d52e1Peter Dunlap /* tell hardware to add timestamp for probe responses */
a6d42e7d71324c5193c3b94d57d96ba2925d52e1Peter Dunlap rt2560_setup_tx_desc(sc, desc, flags, pktlen, rate, 0);
a6d42e7d71324c5193c3b94d57d96ba2925d52e1Peter Dunlap (void) ddi_dma_sync(dr->dr_hnd, 0, RAL_TXBUF_SIZE, DDI_DMA_SYNC_FORDEV);
bf604c6405d5cbc4e94e3d0ecc9e6e074ed4ea67Peter Dunlap (void) ddi_dma_sync(dr->dr_hnd, idx * RT2560_TX_DESC_SIZE,
bf604c6405d5cbc4e94e3d0ecc9e6e074ed4ea67Peter Dunlap RAL_DEBUG(RAL_DBG_MGMT, "sending mgt frame len=%u idx=%u rate=%u\n",
bf604c6405d5cbc4e94e3d0ecc9e6e074ed4ea67Peter Dunlap /* kick prio */
a6d42e7d71324c5193c3b94d57d96ba2925d52e1Peter Dunlap sc->prioq.queued++; /* IF > RT2560_PRIO_RING_COUNT? FULL */
a6d42e7d71324c5193c3b94d57d96ba2925d52e1Peter Dunlap sc->prioq.cur = (sc->prioq.cur + 1) % RT2560_PRIO_RING_COUNT;
a6d42e7d71324c5193c3b94d57d96ba2925d52e1Peter Dunlap RAL_WRITE(sc, RT2560_TXCSR0, RT2560_KICK_PRIO);
d618d68dcf9c6c8f2c1e2fbbd4de1de0cf30150ePriya Krishnan struct rt2560_softc *sc = (struct rt2560_softc *)ic;
a6d42e7d71324c5193c3b94d57d96ba2925d52e1Peter Dunlap if (sc->txq.queued >= RT2560_TX_RING_COUNT - 1) {
a6d42e7d71324c5193c3b94d57d96ba2925d52e1Peter Dunlap RAL_DEBUG(RAL_DBG_TX, "ral: rt2560_tx_data(): "
a6d42e7d71324c5193c3b94d57d96ba2925d52e1Peter Dunlap "no TX DMA buffer available!\n");
bf604c6405d5cbc4e94e3d0ecc9e6e074ed4ea67Peter Dunlap RAL_DEBUG(RAL_DBG_TX, "rt2560_xmit(): can't alloc mblk.\n");
a6d42e7d71324c5193c3b94d57d96ba2925d52e1Peter Dunlap for (off = 0, m0 = mp; m0 != NULL; m0 = m0->b_cont) {
60220f10412f6a7c5b45f950f6f6aa364658a179Priya Krishnan (void) memcpy(m->b_rptr + off, m0->b_rptr, mblen);
70a38f022809785150671c14c5ed29eeaf0de287Priya Krishnan /* packet header may have moved, reset our local pointer */
70a38f022809785150671c14c5ed29eeaf0de287Priya Krishnan * RTS/CTS exchange ignore, since the max packet will less than
a6d42e7d71324c5193c3b94d57d96ba2925d52e1Peter Dunlap * the rtsthreshold (2346)
63528ae45fc8c92cddd3c3b0dc846a9be84f44acJames Moore * Unnecessary codes deleted.
a6d42e7d71324c5193c3b94d57d96ba2925d52e1Peter Dunlap if (ic->ic_fixed_rate != IEEE80211_FIXED_RATE_NONE) {
a6d42e7d71324c5193c3b94d57d96ba2925d52e1Peter Dunlap ni->in_txrate = ral_rssadapt_choose(&rn->rssadapt, rs, wh,
a6d42e7d71324c5193c3b94d57d96ba2925d52e1Peter Dunlap /* remember link conditions for rate adaptation algorithm */
a6d42e7d71324c5193c3b94d57d96ba2925d52e1Peter Dunlap if (ic->ic_fixed_rate == IEEE80211_FIXED_RATE_NONE) {
a6d42e7d71324c5193c3b94d57d96ba2925d52e1Peter Dunlap dur = rt2560_txtime(RAL_ACK_SIZE, rt2560_ack_rate(ic, rate),
a6d42e7d71324c5193c3b94d57d96ba2925d52e1Peter Dunlap /* flags |= RT2560_TX_CIPHER_NONE; */
a6d42e7d71324c5193c3b94d57d96ba2925d52e1Peter Dunlap rt2560_setup_tx_desc(sc, desc, flags, pktlen, rate, 0);
72cf314316bed51cd2e5fd0cb021a9725316a6b0peter dunlap (void) ddi_dma_sync(dr->dr_hnd, 0, RAL_TXBUF_SIZE, DDI_DMA_SYNC_FORDEV);
72cf314316bed51cd2e5fd0cb021a9725316a6b0peter dunlap (void) ddi_dma_sync(dr->dr_hnd, idx * RT2560_TX_DESC_SIZE,
a6d42e7d71324c5193c3b94d57d96ba2925d52e1Peter Dunlap RAL_DEBUG(RAL_DBG_TX, "sending data frame len=%u idx=%u rate=%u\n",
a6d42e7d71324c5193c3b94d57d96ba2925d52e1Peter Dunlap /* kick tx */
a6d42e7d71324c5193c3b94d57d96ba2925d52e1Peter Dunlap sc->txq.cur = (sc->txq.cur + 1) % RT2560_TX_RING_COUNT;
1d7b78a3ad3ba3aedee339128153e8f515cb6f1cPriya Krishnan struct rt2560_softc *sc = (struct rt2560_softc *)arg;
1d7b78a3ad3ba3aedee339128153e8f515cb6f1cPriya Krishnan * No data frames go out unless we're associated; this
1d7b78a3ad3ba3aedee339128153e8f515cb6f1cPriya Krishnan * should not happen as the 802.11 layer does not enable
1d7b78a3ad3ba3aedee339128153e8f515cb6f1cPriya Krishnan * the xmit queue until we enter the RUN state.
a6d42e7d71324c5193c3b94d57d96ba2925d52e1Peter Dunlap RAL_DEBUG(RAL_DBG_TX, "ral: rt2560_tx_data(): "
a6d42e7d71324c5193c3b94d57d96ba2925d52e1Peter Dunlaprt2560_set_macaddr(struct rt2560_softc *sc, uint8_t *addr)
a6d42e7d71324c5193c3b94d57d96ba2925d52e1Peter Dunlap tmp = addr[0] | addr[1] << 8 | addr[2] << 16 | addr[3] << 24;
a6d42e7d71324c5193c3b94d57d96ba2925d52e1Peter Dunlap "setting MAC address to " MACSTR "\n", MAC2STR(addr));
1d7b78a3ad3ba3aedee339128153e8f515cb6f1cPriya Krishnanrt2560_get_macaddr(struct rt2560_softc *sc, uint8_t *addr)
a6d42e7d71324c5193c3b94d57d96ba2925d52e1Peter Dunlap (sc->sc_rcr & RAL_RCR_PROMISC) ? "entering" : "leaving");
a6d42e7d71324c5193c3b94d57d96ba2925d52e1Peter Dunlapstatic const char *
bf604c6405d5cbc4e94e3d0ecc9e6e074ed4ea67Peter Dunlap default: return ("unknown");
a6d42e7d71324c5193c3b94d57d96ba2925d52e1Peter Dunlap val = rt2560_eeprom_read(sc, RT2560_EEPROM_CONFIG0);
a6d42e7d71324c5193c3b94d57d96ba2925d52e1Peter Dunlap /* read default values for BBP registers */
a6d42e7d71324c5193c3b94d57d96ba2925d52e1Peter Dunlap for (i = 0; i < 16; i++) {
bf604c6405d5cbc4e94e3d0ecc9e6e074ed4ea67Peter Dunlap val = rt2560_eeprom_read(sc, RT2560_EEPROM_BBP_BASE + i);
bf604c6405d5cbc4e94e3d0ecc9e6e074ed4ea67Peter Dunlap /* read Tx power for all b/g channels */
bf604c6405d5cbc4e94e3d0ecc9e6e074ed4ea67Peter Dunlap val = rt2560_eeprom_read(sc, RT2560_EEPROM_TXPOWER + i);
a6d42e7d71324c5193c3b94d57d96ba2925d52e1Peter Dunlap#define N(a) (sizeof (a) / sizeof ((a)[0]))
a6d42e7d71324c5193c3b94d57d96ba2925d52e1Peter Dunlap /* wait for BBP to be ready */
a6d42e7d71324c5193c3b94d57d96ba2925d52e1Peter Dunlap if (rt2560_bbp_read(sc, RT2560_BBP_VERSION) != 0)
a6d42e7d71324c5193c3b94d57d96ba2925d52e1Peter Dunlap RAL_DEBUG(RAL_DBG_HW, "timeout waiting for BBP\n");
a6d42e7d71324c5193c3b94d57d96ba2925d52e1Peter Dunlap /* initialize BBP registers to default values */
a6d42e7d71324c5193c3b94d57d96ba2925d52e1Peter Dunlap for (i = 0; i < N(rt2560_def_bbp); i++) {
a6d42e7d71324c5193c3b94d57d96ba2925d52e1Peter Dunlaprt2560_set_txantenna(struct rt2560_softc *sc, int antenna)
a6d42e7d71324c5193c3b94d57d96ba2925d52e1Peter Dunlap tx = rt2560_bbp_read(sc, RT2560_BBP_TX) & ~RT2560_BBP_ANTMASK;
a6d42e7d71324c5193c3b94d57d96ba2925d52e1Peter Dunlap /* need to force I/Q flip for RF 2525e, 2526 and 5222 */
a6d42e7d71324c5193c3b94d57d96ba2925d52e1Peter Dunlap if (sc->rf_rev == RT2560_RF_2525E || sc->rf_rev == RT2560_RF_2526 ||
a6d42e7d71324c5193c3b94d57d96ba2925d52e1Peter Dunlap /* update values for CCK and OFDM in BBPCSR1 */
a6d42e7d71324c5193c3b94d57d96ba2925d52e1Peter Dunlap tmp = RAL_READ(sc, RT2560_BBPCSR1) & ~0x00070007;
a6d42e7d71324c5193c3b94d57d96ba2925d52e1Peter Dunlaprt2560_set_rxantenna(struct rt2560_softc *sc, int antenna)
a6d42e7d71324c5193c3b94d57d96ba2925d52e1Peter Dunlap rx = rt2560_bbp_read(sc, RT2560_BBP_RX) & ~RT2560_BBP_ANTMASK;
a6d42e7d71324c5193c3b94d57d96ba2925d52e1Peter Dunlap /* need to force no I/Q flip for RF 2525e and 2526 */
a6d42e7d71324c5193c3b94d57d96ba2925d52e1Peter Dunlap if (sc->rf_rev == RT2560_RF_2525E || sc->rf_rev == RT2560_RF_2526)
a6d42e7d71324c5193c3b94d57d96ba2925d52e1Peter Dunlap ieee80211_stop_watchdog(ic); /* stop the watchdog */
a6d42e7d71324c5193c3b94d57d96ba2925d52e1Peter Dunlap /* abort Tx */
a6d42e7d71324c5193c3b94d57d96ba2925d52e1Peter Dunlap /* disable Rx */
a6d42e7d71324c5193c3b94d57d96ba2925d52e1Peter Dunlap RAL_WRITE(sc, RT2560_RXCSR0, RT2560_DISABLE_RX);
a6d42e7d71324c5193c3b94d57d96ba2925d52e1Peter Dunlap /* reset ASIC (imply reset BBP) */
a6d42e7d71324c5193c3b94d57d96ba2925d52e1Peter Dunlap /* disable interrupts */
a6d42e7d71324c5193c3b94d57d96ba2925d52e1Peter Dunlap /* reset Tx and Rx rings */
a6d42e7d71324c5193c3b94d57d96ba2925d52e1Peter Dunlap#define N(a) (sizeof (a) / sizeof ((a)[0]))
a6d42e7d71324c5193c3b94d57d96ba2925d52e1Peter Dunlap /* struct rt2560_softc *sc = priv; */
a6d42e7d71324c5193c3b94d57d96ba2925d52e1Peter Dunlap /* setup tx/rx ring */
a6d42e7d71324c5193c3b94d57d96ba2925d52e1Peter Dunlap /* initialize MAC registers to default values */
a6d42e7d71324c5193c3b94d57d96ba2925d52e1Peter Dunlap for (i = 0; i < N(rt2560_def_mac); i++)
a6d42e7d71324c5193c3b94d57d96ba2925d52e1Peter Dunlap RAL_WRITE(sc, rt2560_def_mac[i].reg, rt2560_def_mac[i].val);
d618d68dcf9c6c8f2c1e2fbbd4de1de0cf30150ePriya Krishnan /* set basic rate set (will be updated later) */
a6d42e7d71324c5193c3b94d57d96ba2925d52e1Peter Dunlap /* set default BSS channel */
a6d42e7d71324c5193c3b94d57d96ba2925d52e1Peter Dunlap /* kick Rx */
a6d42e7d71324c5193c3b94d57d96ba2925d52e1Peter Dunlap tmp = RT2560_DROP_PHY_ERROR | RT2560_DROP_CRC_ERROR;
a6d42e7d71324c5193c3b94d57d96ba2925d52e1Peter Dunlap tmp |= RT2560_DROP_CTL | RT2560_DROP_VERSION_ERROR;
a6d42e7d71324c5193c3b94d57d96ba2925d52e1Peter Dunlap /* clear old FCS and Rx FIFO errors */
a6d42e7d71324c5193c3b94d57d96ba2925d52e1Peter Dunlap /* clear any pending interrupts */
a6d42e7d71324c5193c3b94d57d96ba2925d52e1Peter Dunlap /* enable interrupts */
72cf314316bed51cd2e5fd0cb021a9725316a6b0peter dunlap (void) ieee80211_new_state(ic, IEEE80211_S_SCAN, -1);
72cf314316bed51cd2e5fd0cb021a9725316a6b0peter dunlap struct rt2560_softc *sc = (struct rt2560_softc *)arg;
72cf314316bed51cd2e5fd0cb021a9725316a6b0peter dunlap type = crypto_mech2id(SUN_CKM_RC4); /* load rc4 module into kernel */
72cf314316bed51cd2e5fd0cb021a9725316a6b0peter dunlap RAL_DEBUG(RAL_DBG_GLD, "enter rt2560_m_start(%d)\n", type);
a6d42e7d71324c5193c3b94d57d96ba2925d52e1Peter Dunlap * initialize rt2560 hardware
a6d42e7d71324c5193c3b94d57d96ba2925d52e1Peter Dunlap RAL_DEBUG(RAL_DBG_GLD, "device configuration failed\n");
a6d42e7d71324c5193c3b94d57d96ba2925d52e1Peter Dunlap sc->sc_flags |= RAL_FLAG_RUNNING; /* RUNNING */
a6d42e7d71324c5193c3b94d57d96ba2925d52e1Peter Dunlap struct rt2560_softc *sc = (struct rt2560_softc *)arg;
a6d42e7d71324c5193c3b94d57d96ba2925d52e1Peter Dunlap RAL_DEBUG(RAL_DBG_GLD, "enter rt2560_m_stop()\n");
a6d42e7d71324c5193c3b94d57d96ba2925d52e1Peter Dunlaprt2560_m_unicst(void *arg, const uint8_t *macaddr)
a6d42e7d71324c5193c3b94d57d96ba2925d52e1Peter Dunlap struct rt2560_softc *sc = (struct rt2560_softc *)arg;
a6d42e7d71324c5193c3b94d57d96ba2925d52e1Peter Dunlap RAL_DEBUG(RAL_DBG_GLD, "rt2560_m_unicst(): " MACSTR "\n",
a6d42e7d71324c5193c3b94d57d96ba2925d52e1Peter Dunlap (void) rt2560_set_macaddr(sc, (uint8_t *)macaddr);
a6d42e7d71324c5193c3b94d57d96ba2925d52e1Peter Dunlaprt2560_m_multicst(void *arg, boolean_t add, const uint8_t *mca)
a6d42e7d71324c5193c3b94d57d96ba2925d52e1Peter Dunlap struct rt2560_softc *sc = (struct rt2560_softc *)arg;
a6d42e7d71324c5193c3b94d57d96ba2925d52e1Peter Dunlap RAL_DEBUG(RAL_DBG_GLD, "rt2560_m_promisc()\n");
a6d42e7d71324c5193c3b94d57d96ba2925d52e1Peter Dunlaprt2560_m_ioctl(void* arg, queue_t *wq, mblk_t *mp)
a6d42e7d71324c5193c3b94d57d96ba2925d52e1Peter Dunlap struct rt2560_softc *sc = (struct rt2560_softc *)arg;
a6d42e7d71324c5193c3b94d57d96ba2925d52e1Peter Dunlap (void) ieee80211_new_state(ic, IEEE80211_S_SCAN, -1);
a6d42e7d71324c5193c3b94d57d96ba2925d52e1Peter Dunlaprt2560_m_stat(void *arg, uint_t stat, uint64_t *val)
a6d42e7d71324c5193c3b94d57d96ba2925d52e1Peter Dunlap struct rt2560_softc *sc = (struct rt2560_softc *)arg;
a6d42e7d71324c5193c3b94d57d96ba2925d52e1Peter Dunlap *val = ((ic->ic_fixed_rate == IEEE80211_FIXED_RATE_NONE) ?
a6d42e7d71324c5193c3b94d57d96ba2925d52e1Peter Dunlap (rs->ir_rates[ni->in_txrate] & IEEE80211_RATE_VAL)
a6d42e7d71324c5193c3b94d57d96ba2925d52e1Peter Dunlap struct rt2560_softc *sc = (struct rt2560_softc *)arg;
a6d42e7d71324c5193c3b94d57d96ba2925d52e1Peter Dunlap if (r == 0xffffffff) {
a6d42e7d71324c5193c3b94d57d96ba2925d52e1Peter Dunlap /* disable interrupts */
d618d68dcf9c6c8f2c1e2fbbd4de1de0cf30150ePriya Krishnan /* re-enable interrupts */
d618d68dcf9c6c8f2c1e2fbbd4de1de0cf30150ePriya Krishnanrt2560_reset(dev_info_t *devinfo, ddi_reset_cmd_t cmd)
a6d42e7d71324c5193c3b94d57d96ba2925d52e1Peter Dunlap RAL_DEBUG(RAL_DBG_GLD, "rt2560_reset(0x%p)\n", (void *)devinfo);
a6d42e7d71324c5193c3b94d57d96ba2925d52e1Peter Dunlap sc = ddi_get_soft_state(ral_soft_state_p, ddi_get_instance(devinfo));
a6d42e7d71324c5193c3b94d57d96ba2925d52e1Peter Dunlap /* abort Tx */
a6d42e7d71324c5193c3b94d57d96ba2925d52e1Peter Dunlap /* disable Rx */
a6d42e7d71324c5193c3b94d57d96ba2925d52e1Peter Dunlap RAL_WRITE(sc, RT2560_RXCSR0, RT2560_DISABLE_RX);
d618d68dcf9c6c8f2c1e2fbbd4de1de0cf30150ePriya Krishnan /* reset ASIC (imply reset BBP) */
d618d68dcf9c6c8f2c1e2fbbd4de1de0cf30150ePriya Krishnan RAL_WRITE(sc, RT2560_CSR1, RT2560_RESET_ASIC);
a6d42e7d71324c5193c3b94d57d96ba2925d52e1Peter Dunlap /* disable interrupts */
a6d42e7d71324c5193c3b94d57d96ba2925d52e1Peter Dunlaprt2560_attach(dev_info_t *devinfo, ddi_attach_cmd_t cmd)
60220f10412f6a7c5b45f950f6f6aa364658a179Priya Krishnan RAL_DEBUG(RAL_DBG_GLD, "enter rt2560_attach()\n");
a6d42e7d71324c5193c3b94d57d96ba2925d52e1Peter Dunlap if (ddi_soft_state_zalloc(ral_soft_state_p, instance) != DDI_SUCCESS) {
30e7468f8f41aa30ada067b2c1d5d284046514daPeter Dunlap RAL_DEBUG(RAL_DBG_GLD, "ral: rt2560_attach(): "
30e7468f8f41aa30ada067b2c1d5d284046514daPeter Dunlap "unable to alloc soft_state_p\n");
30e7468f8f41aa30ada067b2c1d5d284046514daPeter Dunlap sc = ddi_get_soft_state(ral_soft_state_p, instance);
30e7468f8f41aa30ada067b2c1d5d284046514daPeter Dunlap /* pci configuration */
30e7468f8f41aa30ada067b2c1d5d284046514daPeter Dunlap err = ddi_regs_map_setup(devinfo, 0, ®s, 0, 0, &ral_csr_accattr,
30e7468f8f41aa30ada067b2c1d5d284046514daPeter Dunlap RAL_DEBUG(RAL_DBG_GLD, "ral: rt2560_attach(): "
a6d42e7d71324c5193c3b94d57d96ba2925d52e1Peter Dunlap "ddi_regs_map_setup() failed");
a6d42e7d71324c5193c3b94d57d96ba2925d52e1Peter Dunlap cachelsz = ddi_get8(ioh, (uint8_t *)(regs + PCI_CONF_CACHE_LINESZ));
60220f10412f6a7c5b45f950f6f6aa364658a179Priya Krishnan vendor_id = ddi_get16(ioh, (uint16_t *)(regs + PCI_CONF_VENID));
60220f10412f6a7c5b45f950f6f6aa364658a179Priya Krishnan device_id = ddi_get16(ioh, (uint16_t *)(regs + PCI_CONF_DEVID));
60220f10412f6a7c5b45f950f6f6aa364658a179Priya Krishnan RAL_DEBUG(RAL_DBG_GLD, "ral: rt2560_attach(): vendor 0x%x, "
60220f10412f6a7c5b45f950f6f6aa364658a179Priya Krishnan "device id 0x%x, cache size %d\n", vendor_id, device_id, cachelsz);
a6d42e7d71324c5193c3b94d57d96ba2925d52e1Peter Dunlap * Enable response to memory space accesses,
a6d42e7d71324c5193c3b94d57d96ba2925d52e1Peter Dunlap * and enabe bus master.
30e7468f8f41aa30ada067b2c1d5d284046514daPeter Dunlap ddi_put16(ioh, (uint16_t *)(regs + PCI_CONF_COMM), command);
30e7468f8f41aa30ada067b2c1d5d284046514daPeter Dunlap RAL_DEBUG(RAL_DBG_GLD, "ral: rt2560_attach(): "
a6d42e7d71324c5193c3b94d57d96ba2925d52e1Peter Dunlap ddi_put8(ioh, (uint8_t *)(regs + PCI_CONF_LATENCY_TIMER), 0xa8);
a6d42e7d71324c5193c3b94d57d96ba2925d52e1Peter Dunlap ddi_put8(ioh, (uint8_t *)(regs + PCI_CONF_ILINE), 0x10);
a6d42e7d71324c5193c3b94d57d96ba2925d52e1Peter Dunlap /* pci i/o space */
a6d42e7d71324c5193c3b94d57d96ba2925d52e1Peter Dunlap &sc->sc_rbase, 0, 0, &ral_csr_accattr, &sc->sc_ioh);
a6d42e7d71324c5193c3b94d57d96ba2925d52e1Peter Dunlap RAL_DEBUG(RAL_DBG_GLD, "ral: rt2560_attach(): "
a6d42e7d71324c5193c3b94d57d96ba2925d52e1Peter Dunlap RAL_DEBUG(RAL_DBG_GLD, "ral: rt2560_attach(): "
a6d42e7d71324c5193c3b94d57d96ba2925d52e1Peter Dunlap "ddi_regs_map_setup() failed");
a6d42e7d71324c5193c3b94d57d96ba2925d52e1Peter Dunlap /* initialize the ral rate */
a6d42e7d71324c5193c3b94d57d96ba2925d52e1Peter Dunlap /* retrieve RT2560 rev. no */
a6d42e7d71324c5193c3b94d57d96ba2925d52e1Peter Dunlap /* retrieve MAC address */
a6d42e7d71324c5193c3b94d57d96ba2925d52e1Peter Dunlap /* retrieve RF rev. no and various other things from EEPROM */
a6d42e7d71324c5193c3b94d57d96ba2925d52e1Peter Dunlap RAL_DEBUG(RAL_DBG_GLD, "MAC/BBP RT2560 (rev 0x%02x), RF %s\n",
a6d42e7d71324c5193c3b94d57d96ba2925d52e1Peter Dunlap * Allocate Tx and Rx rings.
a6d42e7d71324c5193c3b94d57d96ba2925d52e1Peter Dunlap err = rt2560_alloc_tx_ring(sc, &sc->txq, RT2560_TX_RING_COUNT);
30e7468f8f41aa30ada067b2c1d5d284046514daPeter Dunlap RAL_DEBUG(RAL_DBG_GLD, "could not allocate Tx ring\n");
30e7468f8f41aa30ada067b2c1d5d284046514daPeter Dunlap err = rt2560_alloc_tx_ring(sc, &sc->prioq, RT2560_PRIO_RING_COUNT);
a6d42e7d71324c5193c3b94d57d96ba2925d52e1Peter Dunlap RAL_DEBUG(RAL_DBG_GLD, "could not allocate Prio ring\n");
a6d42e7d71324c5193c3b94d57d96ba2925d52e1Peter Dunlap err = rt2560_alloc_rx_ring(sc, &sc->rxq, RT2560_RX_RING_COUNT);
a6d42e7d71324c5193c3b94d57d96ba2925d52e1Peter Dunlap RAL_DEBUG(RAL_DBG_GLD, "could not allocate Rx ring\n");
a6d42e7d71324c5193c3b94d57d96ba2925d52e1Peter Dunlap mutex_init(&sc->sc_genlock, NULL, MUTEX_DRIVER, NULL);
a6d42e7d71324c5193c3b94d57d96ba2925d52e1Peter Dunlap mutex_init(&sc->txq.tx_lock, NULL, MUTEX_DRIVER, NULL);
a6d42e7d71324c5193c3b94d57d96ba2925d52e1Peter Dunlap mutex_init(&sc->prioq.tx_lock, NULL, MUTEX_DRIVER, NULL);
a6d42e7d71324c5193c3b94d57d96ba2925d52e1Peter Dunlap mutex_init(&sc->rxq.rx_lock, NULL, MUTEX_DRIVER, NULL);
a6d42e7d71324c5193c3b94d57d96ba2925d52e1Peter Dunlap ic->ic_phytype = IEEE80211_T_OFDM; /* not only, but not used */
a6d42e7d71324c5193c3b94d57d96ba2925d52e1Peter Dunlap ic->ic_opmode = IEEE80211_M_STA; /* default to BSS mode */
d618d68dcf9c6c8f2c1e2fbbd4de1de0cf30150ePriya Krishnan /* set device capabilities */
a6d42e7d71324c5193c3b94d57d96ba2925d52e1Peter Dunlap IEEE80211_C_SHPREAMBLE | /* short preamble supported */
a6d42e7d71324c5193c3b94d57d96ba2925d52e1Peter Dunlap IEEE80211_C_SHSLOT; /* short slot time supported */
d618d68dcf9c6c8f2c1e2fbbd4de1de0cf30150ePriya Krishnan ic->ic_caps |= IEEE80211_C_WPA; /* Support WPA/WPA2 */
a6d42e7d71324c5193c3b94d57d96ba2925d52e1Peter Dunlap /* set supported .11a rates */
a6d42e7d71324c5193c3b94d57d96ba2925d52e1Peter Dunlap ic->ic_sup_rates[IEEE80211_MODE_11A] = rt2560_rateset_11a;
a6d42e7d71324c5193c3b94d57d96ba2925d52e1Peter Dunlap /* set supported .11a channels */
a6d42e7d71324c5193c3b94d57d96ba2925d52e1Peter Dunlap ic->ic_sup_channels[i].ich_flags = IEEE80211_CHAN_A;
a6d42e7d71324c5193c3b94d57d96ba2925d52e1Peter Dunlap ic->ic_sup_channels[i].ich_flags = IEEE80211_CHAN_A;
a6d42e7d71324c5193c3b94d57d96ba2925d52e1Peter Dunlap ic->ic_sup_channels[i].ich_flags = IEEE80211_CHAN_A;
a6d42e7d71324c5193c3b94d57d96ba2925d52e1Peter Dunlap /* set supported .11b and .11g rates */
a6d42e7d71324c5193c3b94d57d96ba2925d52e1Peter Dunlap ic->ic_sup_rates[IEEE80211_MODE_11B] = rt2560_rateset_11b;
a6d42e7d71324c5193c3b94d57d96ba2925d52e1Peter Dunlap ic->ic_sup_rates[IEEE80211_MODE_11G] = rt2560_rateset_11g;
a6d42e7d71324c5193c3b94d57d96ba2925d52e1Peter Dunlap /* set supported .11b and .11g channels (1 through 14) */
a6d42e7d71324c5193c3b94d57d96ba2925d52e1Peter Dunlap /* register WPA door */
a6d42e7d71324c5193c3b94d57d96ba2925d52e1Peter Dunlap ieee80211_register_door(ic, ddi_driver_name(devinfo),
a6d42e7d71324c5193c3b94d57d96ba2925d52e1Peter Dunlap /* override state transition machine */
a6d42e7d71324c5193c3b94d57d96ba2925d52e1Peter Dunlap err = ddi_add_softintr(devinfo, DDI_SOFTINT_LOW,
a6d42e7d71324c5193c3b94d57d96ba2925d52e1Peter Dunlap &sc->sc_softint_id, NULL, 0, ral_softint_handler, (caddr_t)sc);
a6d42e7d71324c5193c3b94d57d96ba2925d52e1Peter Dunlap RAL_DEBUG(RAL_DBG_GLD, "ral: rt2560_attach(): "
a6d42e7d71324c5193c3b94d57d96ba2925d52e1Peter Dunlap "ddi_add_softintr() failed");
a6d42e7d71324c5193c3b94d57d96ba2925d52e1Peter Dunlap err = ddi_get_iblock_cookie(devinfo, 0, &sc->sc_iblock);
a6d42e7d71324c5193c3b94d57d96ba2925d52e1Peter Dunlap RAL_DEBUG(RAL_DBG_GLD, "ral: rt2560_attach(): "
a6d42e7d71324c5193c3b94d57d96ba2925d52e1Peter Dunlap "Can not get iblock cookie for INT\n");
a6d42e7d71324c5193c3b94d57d96ba2925d52e1Peter Dunlap err = ddi_add_intr(devinfo, 0, NULL, NULL, rt2560_intr, (caddr_t)sc);
a6d42e7d71324c5193c3b94d57d96ba2925d52e1Peter Dunlap "unable to add device interrupt handler\n");
a6d42e7d71324c5193c3b94d57d96ba2925d52e1Peter Dunlap * Provide initial settings for the WiFi plugin; whenever this
a6d42e7d71324c5193c3b94d57d96ba2925d52e1Peter Dunlap * information changes, we need to call mac_plugindata_update()
a6d42e7d71324c5193c3b94d57d96ba2925d52e1Peter Dunlap IEEE80211_ADDR_COPY(wd.wd_bssid, ic->ic_bss->in_bssid);
a6d42e7d71324c5193c3b94d57d96ba2925d52e1Peter Dunlap RAL_DEBUG(RAL_DBG_GLD, "ral: rt2560_attach(): "
a6d42e7d71324c5193c3b94d57d96ba2925d52e1Peter Dunlap "MAC version mismatch\n");
a6d42e7d71324c5193c3b94d57d96ba2925d52e1Peter Dunlap RAL_DEBUG(RAL_DBG_GLD, "ral: rt2560_attach(): "
a6d42e7d71324c5193c3b94d57d96ba2925d52e1Peter Dunlap * Create minor node of type DDI_NT_NET_WIFI
a6d42e7d71324c5193c3b94d57d96ba2925d52e1Peter Dunlap (void) snprintf(strbuf, sizeof (strbuf), "%s%d",
a6d42e7d71324c5193c3b94d57d96ba2925d52e1Peter Dunlap err = ddi_create_minor_node(devinfo, strbuf, S_IFCHR,
a6d42e7d71324c5193c3b94d57d96ba2925d52e1Peter Dunlap RAL_DEBUG(RAL_DBG_GLD, "ddi_create_minor_node() failed\n");
a6d42e7d71324c5193c3b94d57d96ba2925d52e1Peter Dunlap * Notify link is down now
a6d42e7d71324c5193c3b94d57d96ba2925d52e1Peter Dunlap RAL_DEBUG(RAL_DBG_GLD, "rt2560_attach() exit successfully.\n");
a6d42e7d71324c5193c3b94d57d96ba2925d52e1Peter Dunlap ddi_soft_state_free(ral_soft_state_p, ddi_get_instance(devinfo));
60220f10412f6a7c5b45f950f6f6aa364658a179Priya Krishnanrt2560_detach(dev_info_t *devinfo, ddi_detach_cmd_t cmd)
a6d42e7d71324c5193c3b94d57d96ba2925d52e1Peter Dunlap RAL_DEBUG(RAL_DBG_GLD, "enter rt2560_detach()\n");
a6d42e7d71324c5193c3b94d57d96ba2925d52e1Peter Dunlap sc = ddi_get_soft_state(ral_soft_state_p, ddi_get_instance(devinfo));
a6d42e7d71324c5193c3b94d57d96ba2925d52e1Peter Dunlap * Unregister from the MAC layer subsystem
a6d42e7d71324c5193c3b94d57d96ba2925d52e1Peter Dunlap * detach ieee80211 layer
a6d42e7d71324c5193c3b94d57d96ba2925d52e1Peter Dunlap ddi_soft_state_free(ral_soft_state_p, ddi_get_instance(devinfo));