pcie.c revision fc256490629fe68815f7e0f23cf9b3545720cfac
25c28e83beb90e7c80452a7c818c5e6f73a07dc8Piotr Jasiukajtis * CDDL HEADER START
25c28e83beb90e7c80452a7c818c5e6f73a07dc8Piotr Jasiukajtis * The contents of this file are subject to the terms of the
25c28e83beb90e7c80452a7c818c5e6f73a07dc8Piotr Jasiukajtis * Common Development and Distribution License (the "License").
25c28e83beb90e7c80452a7c818c5e6f73a07dc8Piotr Jasiukajtis * You may not use this file except in compliance with the License.
25c28e83beb90e7c80452a7c818c5e6f73a07dc8Piotr Jasiukajtis * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
25c28e83beb90e7c80452a7c818c5e6f73a07dc8Piotr Jasiukajtis * or http://www.opensolaris.org/os/licensing.
25c28e83beb90e7c80452a7c818c5e6f73a07dc8Piotr Jasiukajtis * See the License for the specific language governing permissions
25c28e83beb90e7c80452a7c818c5e6f73a07dc8Piotr Jasiukajtis * and limitations under the License.
25c28e83beb90e7c80452a7c818c5e6f73a07dc8Piotr Jasiukajtis * When distributing Covered Code, include this CDDL HEADER in each
25c28e83beb90e7c80452a7c818c5e6f73a07dc8Piotr Jasiukajtis * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
25c28e83beb90e7c80452a7c818c5e6f73a07dc8Piotr Jasiukajtis * If applicable, add the following below this CDDL HEADER, with the
25c28e83beb90e7c80452a7c818c5e6f73a07dc8Piotr Jasiukajtis * fields enclosed by brackets "[]" replaced with your own identifying
25c28e83beb90e7c80452a7c818c5e6f73a07dc8Piotr Jasiukajtis * information: Portions Copyright [yyyy] [name of copyright owner]
25c28e83beb90e7c80452a7c818c5e6f73a07dc8Piotr Jasiukajtis * CDDL HEADER END
25c28e83beb90e7c80452a7c818c5e6f73a07dc8Piotr Jasiukajtis * Copyright 2010 Sun Microsystems, Inc. All rights reserved.
25c28e83beb90e7c80452a7c818c5e6f73a07dc8Piotr Jasiukajtis * Use is subject to license terms.
#ifdef DEBUG
int pcie_disable_ari = 0;
int *max_supported);
(void *)&modlmisc,
char *pcie_nv_buf;
_init(void)
int rval;
return (rval);
_fini()
int rval;
return (rval);
return (ret);
#if defined(__sparc)
return (ret);
return (DDI_SUCCESS);
return (ret);
return (ret);
return (DDI_SUCCESS);
return (DDI_SUCCESS);
return (EINVAL);
return (EBUSY);
return (EINVAL);
switch (cmd) {
case DEVCTL_DEVICE_GETSTATE:
case DEVCTL_DEVICE_ONLINE:
case DEVCTL_DEVICE_OFFLINE:
case DEVCTL_BUS_GETSTATE:
return (EFAULT);
switch (cmd) {
case DEVCTL_BUS_QUIESCE:
case DEVCTL_BUS_UNQUIESCE:
case DEVCTL_BUS_RESET:
case DEVCTL_BUS_RESETALL:
case DEVCTL_DEVICE_RESET:
return (rv);
goto skip;
skip:
return (DDI_FAILURE);
return (DDI_FAILURE);
return (DDI_SUCCESS);
return (DDI_FAILURE);
return (DDI_FAILURE);
reg16);
== PCIE_ARI_DEVICE)) {
return (DDI_FAILURE);
return (DDI_SUCCESS);
sizeof (pf_pcix_ecc_regs_t));
sizeof (pf_pcix_ecc_regs_t));
sizeof (pf_pcix_bdg_err_regs_t));
sizeof (pf_pcie_adv_rp_err_regs_t));
sizeof (pf_pcie_adv_bdg_err_regs_t));
sizeof (pf_pcie_adv_err_regs_t));
sizeof (pf_pcie_rp_err_regs_t));
sizeof (pf_pcix_ecc_regs_t));
sizeof (pf_pcix_ecc_regs_t));
sizeof (pf_pcix_bdg_err_regs_t));
sizeof (pf_pcix_ecc_regs_t));
sizeof (pf_pcix_err_regs_t));
sizeof (pf_pci_bdg_err_regs_t));
int range_size;
goto initial_done;
case PCI_HEADER_ZERO:
case PCI_HEADER_PPB:
case PCI_HEADER_CARDBUS:
goto caps_done;
switch (capid) {
case PCI_CAP_ID_PCI_E:
& PCIE_PCIECAP_SLOT_IMPL) &&
num_cap--;
case PCI_CAP_ID_PCIX:
num_cap--;
goto caps_done;
== PCIE_EXT_CAP_ID_AER) {
goto final_done;
!= DDI_PROP_SUCCESS) {
#ifdef DEBUG
return (bus_p);
if (!bus_p)
return (DDI_FAILURE);
return (rcdip);
static boolean_t
char *device_type;
return (B_FALSE);
return (B_FALSE);
return (B_TRUE);
goto out;
goto out;
return (DDI_WALK_CONTINUE);
out:
return (DDI_WALK_PRUNECHILD);
int circular_count;
int circular_count;
reg16);
reg32);
reg32);
goto root;
reg32);
root:
return (DDI_SUCCESS);
return (DDI_SUCCESS);
return (DDI_SUCCESS);
goto root;
goto root;
root:
if (!pcie_serr_disable_flag) {
int reglen;
return (DDI_FAILURE);
return (DDI_FAILURE);
return (DDI_SUCCESS);
return (cdip);
return (PCIE_INVALID_BDF);
return (pcie_aer_uce_mask);
return (pcie_aer_ce_mask);
return (pcie_aer_suce_mask);
return (pcie_serr_disable_flag);
pcie_ecrc_value = 0;
return (B_TRUE);
return (B_FALSE);
int max_payload_size;
return (DDI_FAILURE);
return (DDI_FAILURE);
return (DDI_SUCCESS);
return (DDI_SUCCESS);
int circular_count;
(void *)&max_pay_load_supported);
int rlen;
goto fail1;
goto fail1;
goto fail1;
goto fail2;
DDI_FAILURE) {
goto fail3;
return (DDI_WALK_CONTINUE);
int port_type;
return (DDI_SUCCESS);
return (DDI_FAILURE);
char *device_type;
!= DDI_PROP_SUCCESS) {
return (DDI_FAILURE);
return (rc);
int result;
return (result);
return (PCIE_ARI_FORW_NOT_SUPPORTED);
return (PCIE_ARI_FORW_NOT_SUPPORTED);
if (pcie_disable_ari) {
return (PCIE_ARI_FORW_NOT_SUPPORTED);
return (PCIE_ARI_FORW_NOT_SUPPORTED);
return (PCIE_ARI_FORW_SUPPORTED);
return (PCIE_ARI_FORW_NOT_SUPPORTED);
return (DDI_FAILURE);
return (DDI_SUCCESS);
return (DDI_FAILURE);
return (DDI_SUCCESS);
return (PCIE_ARI_FORW_DISABLED);
return (PCIE_ARI_FORW_ENABLED);
return (PCIE_ARI_FORW_DISABLED);
return (PCIE_NOT_ARI_DEVICE);
!= DDI_SUCCESS) {
return (PCIE_NOT_ARI_DEVICE);
return (PCIE_NOT_ARI_DEVICE);
return (PCIE_ARI_DEVICE);
return (DDI_FAILURE);
return (DDI_FAILURE);
return (DDI_SUCCESS);
return (NULL);
return (cdip);
return (NULL);
#ifdef DEBUG
int pcie_dbg_print = 0;
if (!pcie_debug_flags) {
if (servicing_interrupt()) {
if (pcie_dbg_print) {
if (val == 0)
if (val == 0)