pci_intr_lib.c revision 7c478bd95313f5f23a4c958a745db2134aa03244
/*
* CDDL HEADER START
*
* The contents of this file are subject to the terms of the
* Common Development and Distribution License, Version 1.0 only
* (the "License"). You may not use this file except in compliance
* with the License.
*
* You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
* See the License for the specific language governing permissions
* and limitations under the License.
*
* When distributing Covered Code, include this CDDL HEADER in each
* file and include the License file at usr/src/OPENSOLARIS.LICENSE.
* If applicable, add the following below this CDDL HEADER, with the
* fields enclosed by brackets "[]" replaced with your own identifying
* information: Portions Copyright [yyyy] [name of copyright owner]
*
* CDDL HEADER END
*/
/*
* Copyright 2005 Sun Microsystems, Inc. All rights reserved.
* Use is subject to license terms.
*/
#pragma ident "%Z%%M% %I% %E% SMI"
/*
* Support for MSI, MSIX and INTx
*/
/*
* Library utility functions
*/
/*
* pci_check_pciex:
*
* check whether the device has PCI-E capability
*/
int
{
"pci_config_setup() failed\n"));
return (DDI_FAILURE);
}
if (!(status & PCI_STAT_CAP))
goto notpciex;
cap));
if (cap == PCI_CAP_ID_PCI_E) {
"PCI-Express capability found\n"));
return (DDI_SUCCESS);
}
}
return (DDI_FAILURE);
}
/*
* pci_get_msi_ctrl:
*
* Helper function that returns with 'cfg_hdl', MSI/X ctrl pointer,
* and caps_ptr for MSI/X if these are found.
*/
static int
{
"%s%d can't get config handle",
return (DDI_FAILURE);
}
/* Are capabilities supported? */
"%p doesn't support capabilities\n", (void *)dip));
return (DDI_FAILURE);
}
*caps_ptr &= PCI_CAP_PTR_MASK;
*caps_ptr + PCI_MSI_CTRL);
return (DDI_SUCCESS);
}
*caps_ptr + PCI_MSIX_CTRL);
return (DDI_SUCCESS);
}
*caps_ptr + PCI_CAP_NEXT_PTR);
}
return (DDI_FAILURE);
}
/*
* pci_msi_get_cap:
*
* Get the capabilities of the MSI/X interrupt
*/
int
{
(void *)rdip));
*flagsp = 0;
return (DDI_FAILURE);
if (type == DDI_INTR_TYPE_MSI) {
if (msi_ctrl & PCI_MSI_64BIT_MASK)
if (msi_ctrl & PCI_MSI_PVM_MASK)
*flagsp |= (DDI_INTR_FLAG_MASKABLE |
else
} else if (type == DDI_INTR_TYPE_MSIX) {
/* MSI-X supports PVM, 64bit by default */
}
*flagsp |= DDI_INTR_FLAG_EDGE;
return (DDI_SUCCESS);
}
/*
* pci_msi_configure:
*
* capability structure.
*/
/* ARGSUSED */
int
{
(void *)rdip));
return (DDI_FAILURE);
if (type == DDI_INTR_TYPE_MSI) {
/* Set the bits to inform how many MSIs are enabled */
/* Set the "data" and "addr" bits */
if (msi_ctrl & PCI_MSI_64BIT_MASK) {
} else {
}
} else if (type == DDI_INTR_TYPE_MSIX) {
/* Offset into the "inum"th entry in the MSI-X table */
/* Set the "data" and "addr" bits */
}
return (DDI_SUCCESS);
}
/*
* pci_msi_unconfigure:
*
* capability structure.
*/
/* ARGSUSED */
int
{
(void *)rdip));
return (DDI_FAILURE);
if (type == DDI_INTR_TYPE_MSI) {
msi_ctrl &= (~PCI_MSI_MME_MASK);
caps_ptr + PCI_MSI_ADDR_OFFSET, 0);
if (msi_ctrl & PCI_MSI_64BIT_MASK) {
caps_ptr + PCI_MSI_64BIT_DATA, 0);
} else {
caps_ptr + PCI_MSI_32BIT_DATA, 0);
}
"msi_ctrl = %x\n",
} else if (type == DDI_INTR_TYPE_MSIX) {
/* Offset into the "inum"th entry in the MSI-X table */
/* Reset the "data" and "addr" bits */
}
return (DDI_SUCCESS);
}
/*
* pci_is_msi_enabled:
*
* This function returns DDI_SUCCESS if MSI/X is already enabled, otherwise
* it returns DDI_FAILURE.
*/
int
{
int ret = DDI_FAILURE;
return (DDI_FAILURE);
ret = DDI_SUCCESS;
ret = DDI_SUCCESS;
return (ret);
}
/*
* pci_msi_enable_mode:
*
* This function sets the MSI_ENABLE bit in the capability structure
* (for MSI) and MSIX_ENABLE bit in the MSI-X capability structure.
*/
int
{
return (DDI_FAILURE);
/* Disable INTx simulation, if applicable */
/* This write succeeds only for devices > PCI2.3 */
"Before CmdReg = 0x%x, After CmdReg = 0x%x\n",
if (type == DDI_INTR_TYPE_MSI) {
if (msi_ctrl & PCI_MSI_ENABLE_BIT)
goto finished;
} else if (type == DDI_INTR_TYPE_MSIX) {
if (msi_ctrl & PCI_MSIX_ENABLE_BIT)
goto finished;
/* Offset into the "inum"th entry in the MSI-X table */
/* Clear the Mask bit */
mask_bits &= ~0;
}
msi_ctrl));
return (DDI_SUCCESS);
}
/*
* pci_msi_disable_mode:
*
* This function resets the MSI_ENABLE bit in the capability structure
* (for MSI) and MSIX_ENABLE bit in the MSI-X capability structure.
*/
int
{
return (DDI_FAILURE);
/* Reset the "enable" bit */
if (type == DDI_INTR_TYPE_MSI) {
if (!(msi_ctrl & PCI_MSI_ENABLE_BIT))
goto finished;
} else if (type == DDI_INTR_TYPE_MSIX) {
if (!(msi_ctrl & PCI_MSIX_ENABLE_BIT))
goto finished;
/* Offset into the "inum"th entry in the MSI-X table */
/* Set the Mask bit */
}
msi_ctrl));
return (DDI_SUCCESS);
}
/*
* pci_msi_set_mask:
*
* Set the mask bit in the MSI/X capability structure
*/
/* ARGSUSED */
int
{
int offset;
int ret = DDI_FAILURE;
return (DDI_FAILURE);
if (type == DDI_INTR_TYPE_MSI) {
if (!(msi_ctrl & PCI_MSI_PVM_MASK))
goto done;
} else if (type == DDI_INTR_TYPE_MSIX) {
/* Set function mask */
if (msi_ctrl & PCI_MSIX_FUNCTION_MASK) {
ret = DDI_SUCCESS;
goto done;
}
/* Offset into the "inum"th entry in the MSI-X table */
/* Set the Mask bit */
}
ret = DDI_SUCCESS;
done:
return (ret);
}
/*
* pci_msi_clr_mask:
*
* Clear the mask bit in the MSI/X capability structure
*/
/* ARGSUSED */
int
{
int offset;
int ret = DDI_FAILURE;
return (DDI_FAILURE);
if (type == DDI_INTR_TYPE_MSI) {
if (!(msi_ctrl & PCI_MSI_PVM_MASK))
goto done;
} else if (type == DDI_INTR_TYPE_MSIX) {
if (msi_ctrl & PCI_MSIX_FUNCTION_MASK) {
ret = DDI_SUCCESS;
goto done;
}
/* Offset into the "inum"th entry in the MSI-X table */
/* Clear the Mask bit */
mask_bits &= ~0;
}
ret = DDI_SUCCESS;
done:
return (ret);
}
/*
* pci_msi_get_pending:
*
* Get the pending bit from the MSI/X capability structure
*/
/* ARGSUSED */
int
{
int offset;
int ret = DDI_FAILURE;
(void *)rdip));
return (DDI_FAILURE);
if (type == DDI_INTR_TYPE_MSI) {
if (!(msi_ctrl & PCI_MSI_PVM_MASK)) {
"PVM is not supported\n"));
goto done;
}
} else if (type == DDI_INTR_TYPE_MSIX) {
/* Offset into the PBA array which has entry for "inum" */
/* Read the PBA array */
}
ret = DDI_SUCCESS;
done:
return (ret);
}
/*
* pci_msi_get_nintrs:
*
* For a given type (MSI/X) returns the number of interrupts supported
*/
int
{
(void *)rdip));
return (DDI_FAILURE);
if (type == DDI_INTR_TYPE_MSI) {
} else if (type == DDI_INTR_TYPE_MSIX) {
if (msi_ctrl & PCI_MSIX_TBL_SIZE_MASK)
}
"nintr = 0x%x\n", *nintrs));
return (DDI_SUCCESS);
}
/*
* pci_msi_set_nintrs:
*
* For a given type (MSI/X) sets the number of interrupts supported
* by the system.
* For MSI: Return an error if this func is called for navail > 32
* For MSI-X: Return an error if this func is called for navail > 2048
*/
int
{
/* Check for valid input argument */
return (DDI_EINVAL);
return (DDI_FAILURE);
if (type == DDI_INTR_TYPE_MSI) {
} else if (type == DDI_INTR_TYPE_MSIX) {
}
return (DDI_SUCCESS);
}
/*
* pci_msi_get_supported_type:
*
* types if device supports them. A DDI_FAILURE is returned otherwise.
*/
int
{
"rdip = 0x%p\n", (void *)rdip));
*typesp = 0;
*typesp |= DDI_INTR_TYPE_MSI;
}
*typesp |= DDI_INTR_TYPE_MSIX;
}
}
/*
* pci_msix_init:
* needed for MSI-X support. It also allocates a private
* structure to keep track of these.
*/
{
return (NULL);
/*
* Initialize the devacc structure
*/
/*
* Map the entire MSI-X vector table
*/
if (ddi_regs_map_setup(rdip,
&msix_p->msix_tbl_hdl) !=
DDI_SUCCESS) {
"ddi_regs_map_setup failed\n"));
return (NULL);
}
/*
* Map in the MSI-X Pending Bit Array
*/
if (msi_ctrl & PCI_MSIX_TBL_SIZE_MASK)
if (ddi_regs_map_setup(rdip,
"ddi_regs_map_setup failed\n"));
return (NULL);
}
(void *)msix_p));
return (msix_p);
}
/*
* pci_msix_fini:
* It is only called if no more MSI-X interrupts are being used.
*/
void
{
(void *)msix_p));
}
/*
* Next set of routines are for INTx (legacy) PCI interrupt
* support only.
*/
/*
* pci_intx_get_cap:
* For non-MSI devices that comply to PCI v2.3 or greater;
* read the command register. Bit 10 implies interrupt disable.
* Set this bit and then read the status register bit 3.
* Bit 3 of status register is Interrupt state.
* If it is set; then the device supports 'Masking'
*
* Reset the device back to the original state.
*/
int
{
#ifdef DEBUG
#endif /* DEBUG */
*flagsp = 0;
"config handle\n"));
return (DDI_FAILURE);
}
"command register was 0x%x\n", savereg));
/* Disable the interrupts */
#ifdef DEBUG
"status register is 0x%x\n", statreg));
#endif /* DEBUG */
/* Read the bit back */
"command register is now 0x%x\n", cmdreg));
if (cmdreg & PCI_COMM_INTX_DISABLE) {
"masking supported\n"));
*flagsp = (DDI_INTR_FLAG_MASKABLE |
}
/* Restore the device back to the original state and return */
return (DDI_SUCCESS);
}
/*
* pci_intx_clr_mask:
* For non-MSI devices that comply to PCI v2.3 or greater;
* clear the bit10 in the command register.
*/
int
{
"config handle\n"));
return (DDI_FAILURE);
}
"command register was 0x%x\n", cmdreg));
/* Enable the interrupts */
return (DDI_SUCCESS);
}
/*
* pci_intx_set_mask:
* For non-MSI devices that comply to PCI v2.3 or greater;
* set the bit10 in the command register.
*/
int
{
"config handle\n"));
return (DDI_FAILURE);
}
"command register was 0x%x\n", cmdreg));
/* Disable the interrupts */
return (DDI_SUCCESS);
}
/*
* pci_intx_get_pending:
* For non-MSI devices that comply to PCI v2.3 or greater;
* read the status register. Bit 3 of status register is
* Interrupt state. If it is set; then the interrupt is
* 'Pending'.
*/
int
{
*pendingp = 0;
"config handle\n"));
return (DDI_FAILURE);
}
if (statreg & PCI_STAT_INTR) {
"interrupt is pending\n"));
*pendingp = 1;
}
return (DDI_SUCCESS);
}
/*
* pci_devclass_to_ipl:
* translate from device class to ipl
* NOTE: This function is added here as pci_intx_get_ispec()
* calls this to figure out the priority.
* It is moved over from x86 pci.c
*/
int
pci_devclass_to_ipl(int class)
{
int base_cl;
int ipl;
/*
* Use the class code values to construct an ipl for the device.
*/
switch (base_cl) {
default:
case PCI_CLASS_NONE:
ipl = 1;
break;
case PCI_CLASS_MASS:
ipl = 0x5;
break;
case PCI_CLASS_NET:
ipl = 0x6;
break;
case PCI_CLASS_DISPLAY:
ipl = 0x9;
break;
/*
* for high priority interrupt handlers, use level 12
* as the highest for device drivers
*/
case PCI_CLASS_MM:
ipl = 0xc;
break;
case PCI_CLASS_MEM:
ipl = 0xc;
break;
case PCI_CLASS_BRIDGE:
ipl = 0xc;
break;
}
return (ipl);
}
/*
* pci_intx_get_ispec:
* Get intrspec for PCI devices (legacy support)
* NOTE: This is moved here from x86 pci.c and is
* needed here as pci-ide.c uses it as well
*/
/*ARGSUSED*/
{
int class, *intpriorities;
struct ddi_parent_private_data *pdptr;
return (NULL);
/* check if the intrspec_pri has been initialized */
if (!ispec->intrspec_pri) {
DDI_PROP_DONTPASS, "interrupt-priorities",
if (inum < num_intpriorities)
}
/* If still no priority, guess based on the class code */
if (ispec->intrspec_pri == 0) {
/* get 'class' property to derive the intr priority */
}
}
/* Get interrupt line value */
if (!ispec->intrspec_vec) {
"can't get config handle\n"));
return (NULL);
}
}
return ((ddi_intrspec_t)ispec);
}