nxge_send.c revision adfcba552dfc70ff685a2e8703fe1761b244f3e8
/*
* CDDL HEADER START
*
* The contents of this file are subject to the terms of the
* Common Development and Distribution License (the "License").
* You may not use this file except in compliance with the License.
*
* You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
* See the License for the specific language governing permissions
* and limitations under the License.
*
* When distributing Covered Code, include this CDDL HEADER in each
* file and include the License file at usr/src/OPENSOLARIS.LICENSE.
* If applicable, add the following below this CDDL HEADER, with the
* fields enclosed by brackets "[]" replaced with your own identifying
* information: Portions Copyright [yyyy] [name of copyright owner]
*
* CDDL HEADER END
*/
/*
* Copyright 2007 Sun Microsystems, Inc. All rights reserved.
* Use is subject to license terms.
*/
#pragma ident "%Z%%M% %I% %E% SMI"
extern uint32_t nxge_reclaim_pending;
extern uint32_t nxge_bcopy_thresh;
extern uint32_t nxge_dvma_thresh;
extern uint32_t nxge_dma_stream_thresh;
extern uint32_t nxge_tx_minfree;
extern uint32_t nxge_tx_intr_thres;
extern uint32_t nxge_tx_max_gathers;
extern uint32_t nxge_tx_tiny_pack;
extern uint32_t nxge_tx_use_bcopy;
extern uint32_t nxge_tx_lb_policy;
extern uint32_t nxge_no_tx_lb;
extern nxge_tx_mode_t nxge_tx_scheme;
typedef struct _mac_tx_hint {
void *hash;
int
{
int status = 0;
int last_bidx;
int len;
t_uscalar_t start_offset = 0;
t_uscalar_t stuff_offset = 0;
t_uscalar_t end_offset = 0;
t_uscalar_t value = 0;
t_uscalar_t cksum_flags = 0;
#ifdef NXGE_DEBUG
int dump_len;
int sad_len;
int xfer_len;
#endif
"==> nxge_start: Starting tdc %d desc pending %d",
"link not up or LB mode"));
goto nxge_start_fail1;
}
}
start_offset += sizeof (ether_header_t);
stuff_offset += sizeof (ether_header_t);
} else {
start_offset += sizeof (struct ether_vlan_header);
stuff_offset += sizeof (struct ether_vlan_header);
}
if (cksum_flags & HCK_PARTIALCKSUM) {
"==> nxge_start: cksum_flags 0x%x (partial checksum) ",
cksum_flags));
}
#ifdef NXGE_DEBUG
if (tx_ring_p->descs_pending) {
}
"==> nxge_start: tdc %d: dumping ...: b_rptr $%p "
"(Before header reserve: ORIGINAL LEN %d)",
dump_len));
#endif
< nxge_tx_minfree));
"TX Descriptor ring is channel %d mark mode %d",
"TX Descriptor ring is full: channel %d",
tdc_stats->tx_no_desc++;
}
status = 1;
goto nxge_start_fail1;
}
nmblks = 0;
ngathers = 0;
pkt_len = 0;
pack_len = 0;
clen = 0;
last_bidx = -1;
#ifdef NXGE_DEBUG
#endif
sop_index, i));
#ifdef NXGE_DEBUG
"==> nxge_start(1): wr_index %d i %d msgdsize %d",
#endif
/*
* The first 16 bytes of the premapped buffer are reserved
* for header. No padding will be used.
*/
} else {
}
while (nmp) {
if (len <= 0) {
continue;
}
nmblks++;
"len %d pkt_len %d pack_len %d",
/*
* Hardware limits the transfer length to 4K for NIU and
* 4076 (TX_MAX_TRANSFER_LENGTH) for Neptune. But we just
* use TX_MAX_TRANSFER_LENGTH as the limit for both.
* If len is longer than the limit, then we break nmp into
* two chunks: Make the first chunk equal to the limit and
* the second chunk for the remaining data. If the second
* chunk is still larger than the limit, then it will be
* broken into two in the next pass.
*/
}
tx_desc_p = &tx_desc_ring_vp[i];
#ifdef NXGE_DEBUG
tx_desc_pp = &tx_desc_ring_pp[i];
#endif
tx_msg_p = &tx_msg_ring[i];
#if defined(__i386)
#else
#endif
if (!header_set &&
(len >= bcopy_thresh))) {
header_set = B_TRUE;
boff = 0;
pack_len = 0;
(void) ddi_dma_sync(dma_handle,
}
"desc entry %d "
"DESC IOADDR $%p "
"desc_vp $%p tx_desc_p $%p "
"desc_pp $%p tx_desc_pp $%p "
"len %d pkt_len %d pack_len %d",
i,
if (len < bcopy_thresh) {
"USE BCOPY: "));
if (nxge_tx_tiny_pack) {
TXDMA_DESC_NEXT_INDEX(i, -1,
"==> nxge_start(5): pack"));
if ((pack_len <= bcopy_thresh) &&
"==> nxge_start: pack(6) "
"(pkt_len %d pack_len %d)",
i = blst;
tx_desc_p = &tx_desc_ring_vp[i];
#ifdef NXGE_DEBUG
tx_desc_pp = &tx_desc_ring_pp[i];
#endif
tx_msg_p = &tx_msg_ring[i];
ngathers--;
} else if (pack_len > bcopy_thresh &&
header_set) {
boff = 0;
"==> nxge_start(7): > max NEW "
"bcopy thresh %d "
"pkt_len %d pack_len %d(next)",
}
last_bidx = i;
}
header_set = B_TRUE;
"==> nxge_start(7_x2): "
"pkt_len %d pack_len %d (new hdrp $%p)",
}
"USE BCOPY: before bcopy "
"DESC IOADDR $%p entry %d "
"bcopy packets %d "
"bcopy kaddr $%p "
"bcopy ioaddr (SAD) $%p "
"bcopy clen %d "
"bcopy boff %d",
clen,
boff));
"1USE BCOPY: "));
"2USE BCOPY: "));
"last USE BCOPY: copy from b_rptr $%p "
"to KADDR $%p (len %d offset %d",
#ifdef NXGE_DEBUG
"==> nxge_start: dump packets "
"(After BCOPY len %d)"
dump_len)));
#endif
(void) ddi_dma_sync(dma_handle,
tdc_stats->tx_hdr_pkts++;
"USE BCOPY: "
"DESC IOADDR $%p entry %d "
"bcopy packets %d "
"bcopy kaddr $%p "
"bcopy ioaddr (SAD) $%p "
"bcopy clen %d "
"bcopy boff %d",
i,
clen,
boff));
} else {
"USE DVMA: len %d", len));
if (len < nxge_dma_stream_thresh) {
} else {
}
&dma_cookie, &ncookies);
if (status == DDI_DMA_MAPPED) {
"==> nxge_start(12_1): "
"USE DVMA: len %d clen %d "
"ngathers %d",
ngathers));
#if defined(__i386)
#else
#endif
while (ncookies > 1) {
ngathers++;
/*
* this is the fix for multiple
* cookies, which are basicaly
* a descriptor entry, we don't set
* SOP bit as well as related fields
*/
(void) npi_txdma_desc_gather_set(
&tx_desc,
(ngathers -1),
clen);
"==> nxge_start: DMA "
"ncookie %d "
"ngathers %d "
"dma_ioaddr $%p len %d"
"desc $%p descp $%p (%d)",
&dma_cookie);
"==> nxge_start(12_2): "
"USE DVMA: len %d clen %d ",
i = TXDMA_DESC_NEXT_INDEX(i, 1,
tx_desc_p = &tx_desc_ring_vp[i];
#if defined(__i386)
#else
#endif
tx_msg_p = &tx_msg_ring[i];
ncookies--;
}
tdc_stats->tx_ddi_pkts++;
"DMA: ddi packets %d",
tdc_stats->tx_ddi_pkts));
} else {
"dma mapping failed for %d "
"bytes addr $%p flags %x (%d)",
goto nxge_start_fail2;
}
} /* ddi dvma */
#if defined(__i386)
#else
#endif
ngathers++;
if (ngathers == 1) {
#ifdef NXGE_DEBUG
#endif
sop_tx_desc_p->value = 0;
} else {
#ifdef NXGE_DEBUG
save_desc_p = &tx_desc;
#endif
tmp_desc_p = &tx_desc;
tmp_desc_p->value = 0;
}
"Desc_entry %d ngathers %d "
"desc_vp $%p tx_desc_p $%p "
"len %d clen %d pkt_len %d pack_len %d nmblks %d "
"dma_ioaddr (SAD) $%p mark %d",
i, ngathers,
dma_ioaddr, mark_mode));
#ifdef NXGE_DEBUG
"\t\tsad $%p\ttr_len %d len %d\tnptrs %d\t"
"mark %d sop %d\n",
sad,
#endif
if (ngathers > nxge_tx_max_gathers) {
&cksum_flags);
"==> nxge_start(14): pull msg - "
"len %d pkt_len %d ngathers %d",
/* Pull all message blocks from b_cont */
goto nxge_start_fail2;
}
goto nxge_start_fail2;
}
} /* while (nmp) */
#if defined(__i386)
#else
#endif
if (pkt_len > NXGE_MTU_DEFAULT_MAX) {
}
/* Assume we use bcopy to premapped buffers */
"==> nxge_start(14-1): < (msg_min + 16)"
"len %d pkt_len %d min_len %d bzero %d ngathers %d",
"==> nxge_start(14-2): < msg_min - "
"len %d pkt_len %d min_len %d ngathers %d",
}
cksum_flags));
if (cksum_flags & HCK_PARTIALCKSUM) {
"==> nxge_start: cksum_flags 0x%x (partial checksum) ",
cksum_flags));
"==> nxge_start: from IP cksum_flags 0x%x "
"(partial checksum) "
"start_offset %d stuff_offset %d",
"==> nxge_start: from IP cksum_flags 0x%x "
"(partial checksum) "
"after SHIFT start_offset %d stuff_offset %d",
}
{
/* pkt_len already includes 16 + paddings!! */
/* Update the control header length */
"==> nxge_start(15_x1): setting SOP "
"tot_xfer_len 0x%llx (%d) pkt_len %d tmp_len "
"0x%llx hdrp->value 0x%llx",
#if defined(_BIG_ENDIAN)
#else
#endif
TX_CTL, "==> nxge_start(15_x2): setting SOP "
"after SWAP: tot_xfer_len 0x%llx pkt_len %d "
"tmp_len 0x%llx hdrp->value 0x%llx",
}
"wr_index %d "
"tot_xfer_len (%d) pkt_len %d npads %d",
npads));
#ifdef NXGE_DEBUG
"\t\tsad $%p\ttr_len %d len %d\tnptrs %d\tmark %d sop %d\n",
sad,
"==> nxge_start: dump packets(17) (after sop set, len "
" (len/dump_len/pkt_len/tot_xfer_len) %d/%d/%d/%d):\n"
(char *)hdrp,
"==> nxge_start(18): TX desc sync: sop_index %d",
sop_index));
#endif
(void) ddi_dma_sync(tx_desc_dma_handle,
"cs_off = 0x%02X cs_s_off = 0x%02X "
"pkt_len %d ngathers %d sop_index %d\n",
} else { /* more than one descriptor and wrap around */
(void) ddi_dma_sync(tx_desc_dma_handle,
"cs_off = 0x%02X cs_s_off = 0x%02X "
"pkt_len %d ngathers %d sop_index %d\n",
(void) ddi_dma_sync(tx_desc_dma_handle,
0,
"cs_off = 0x%02X cs_s_off = 0x%02X "
"pkt_len %d ngathers %d sop_index %d\n",
}
}
"channel %d wr_index %d wrap %d ngathers %d desc_pend %d",
{
/* Kick start the Transmit kick register */
}
return (status);
if (good_packet == B_FALSE) {
for (i = 0; i < ngathers; i++) {
#if defined(__i386)
#else
#endif
"tx_desc_p = %X index = %d",
(void) dvma_unload(
0, -1);
if (tx_ring_p->dvma_wr_index ==
tx_ring_p->dvma_wr_index = 0;
else
USE_DMA) {
"ddi_dma_unbind_handle failed");
}
}
}
/* Add FMA to check the access handle nxge_hregh */
return (status);
}
int
{
}
{
tx_rings));
switch (nxge_tx_scheme) {
case NXGE_USE_START:
"ring index %d", ring_index));
return (B_FALSE);
}
break;
case NXGE_USE_SERIAL:
default:
break;
}
ring_index));
return (B_TRUE);
}
/*
* nxge_m_tx() - send a chain of packets
*/
mblk_t *
{
"==> nxge_m_tx: hardware not initialized"));
"<== nxge_m_tx"));
return (mp);
}
/*
* Until Nemo tx resource works, the mac driver
* does the load balancing based on TCP port,
* or CPU. For debugging, we use a system
* configurable parameter.
*/
break;
}
}
return (mp);
}
int
{
uint8_t ring_index = 0;
IP_MAX_HDR_LENGTH + sizeof (uint32_t)];
/*
* allocate space big enough to cover
* the max ip header length and the first
*/
}
switch (nxge_tx_lb_policy) {
case NXGE_TX_LB_TCPUDP: /* default IPv4 TCP/UDP */
default:
if (!nxge_no_tx_lb && !qos &&
== ETHERTYPE_IP)) {
if (mblk_len > sizeof (struct ether_header) +
sizeof (uint8_t)) {
sizeof (struct ether_header);
mblk_len -= sizeof (struct ether_header);
} else {
}
}
hdrs_size = 0;
sizeof (hdrs_buf))) {
if (mblk_len >=
}
}
tcp_port += sizeof (ether_header_t);
switch (tcp_port[9]) {
case IPPROTO_TCP:
case IPPROTO_UDP:
case IPPROTO_ESP:
((tcp_port[0] ^
tcp_port[1] ^
tcp_port[2] ^
break;
case IPPROTO_AH:
/* SPI starts at the 4th byte */
((tcp_port[4] ^
tcp_port[5] ^
tcp_port[6] ^
break;
default:
break;
}
} else { /* fragmented packet */
}
} else {
}
break;
case NXGE_TX_LB_HASH:
#if defined(__i386)
#else
#endif
} else {
}
break;
case NXGE_TX_LB_DEST_MAC: /* Use destination MAC address */
break;
}
return (ring_index);
}
{
nxgep->resched_needed) {
}
return (DDI_INTR_CLAIMED);
}