nxge_main.c revision d62bc4badc1c1f1549c961cfb8b420e650e1272b
/*
* CDDL HEADER START
*
* The contents of this file are subject to the terms of the
* Common Development and Distribution License (the "License").
* You may not use this file except in compliance with the License.
*
* You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
* See the License for the specific language governing permissions
* and limitations under the License.
*
* When distributing Covered Code, include this CDDL HEADER in each
* file and include the License file at usr/src/OPENSOLARIS.LICENSE.
* If applicable, add the following below this CDDL HEADER, with the
* fields enclosed by brackets "[]" replaced with your own identifying
* information: Portions Copyright [yyyy] [name of copyright owner]
*
* CDDL HEADER END
*/
/*
* Copyright 2008 Sun Microsystems, Inc. All rights reserved.
* Use is subject to license terms.
*/
#pragma ident "%Z%%M% %I% %E% SMI"
/*
*/
/*
* PSARC/2007/453 MSI-X interrupt limit override
* (This PSARC case is limited to MSI-X vectors
* and SPARC platforms only).
*/
#if defined(_BIG_ENDIAN)
#else
#endif
/*
*
*/
/* MAX LSO size */
#define NXGE_LSO_MAXLEN 65535
/* Enable Software LSO flag */
/*
* Debugging flags:
* nxge_no_tx_lb : transmit load balancing
* nxge_tx_lb_policy: 0 - TCP port (default)
* 3 - DEST MAC
*/
uint32_t nxge_no_tx_lb = 0;
/*
* Add tunable to reduce the amount of time spent in the
* ISR doing Rx Processing.
*/
/*
* Tunables to manage the receive buffer blocks.
*
* nxge_rx_threshold_hi: copy all buffers.
* nxge_rx_bcopy_size_type: receive buffer block size type.
* nxge_rx_threshold_lo: copy only up to tunable block size type.
*/
#if defined(sun4v)
/*
*/
static hsvc_info_t niu_hsvc = {
NIU_MINOR_VER, "nxge"
};
#endif
/*
* Function Prototypes
*/
static void nxge_unattach(p_nxge_t);
#if NXGE_PROPERTY
static void nxge_remove_hard_properties(p_nxge_t);
#endif
static void nxge_destroy_mutexes(p_nxge_t);
#ifdef NXGE_DEBUG
#endif
static void nxge_suspend(p_nxge_t);
static void nxge_destroy_dev(p_nxge_t);
static void nxge_free_mem_pool(p_nxge_t);
static void nxge_free_rx_mem_pool(p_nxge_t);
static void nxge_free_tx_mem_pool(p_nxge_t);
struct ddi_dma_attr *,
static void nxge_dma_mem_free(p_nxge_dma_common_t);
size_t);
static int nxge_init_common_dev(p_nxge_t);
static void nxge_uninit_common_dev(p_nxge_t);
/*
* The next declarations are for the GLDv3 interface.
*/
static int nxge_m_start(void *);
static void nxge_m_stop(void *);
static int nxge_m_unicst(void *, const uint8_t *);
static int nxge_m_promisc(void *, boolean_t);
static void nxge_m_resources(void *);
#define NXGE_NEPTUNE_MAGIC 0x4E584745UL
#define MAX_DUMP_SZ 256
static mac_callbacks_t nxge_m_callbacks = {
};
void
/* PSARC/2007/453 MSI-X interrupt limit override. */
#define NXGE_MSIX_REQUEST_10G 8
#define NXGE_MSIX_REQUEST_1G 2
static int nxge_create_msi_property(p_nxge_t);
/*
* These global variables control the message
* output.
*/
uint64_t nxge_debug_level = 0;
/*
* This list contains the instance structures for the Neptune
* devices present in the system. The lock exists to guarantee
* mutually exclusive access to the list.
*/
void *nxge_hw_list = NULL;
extern uint64_t npi_debug_level;
extern void nxge_fm_init(p_nxge_t,
ddi_dma_attr_t *);
extern void nxge_fm_fini(p_nxge_t);
/*
* Count used to maintain the number of buffers being used
* by Neptune instances and loaned up to the upper layers.
*/
/*
* Device register access attributes for PIO.
*/
static ddi_device_acc_attr_t nxge_dev_reg_acc_attr = {
};
/*
* Device descriptor access attributes for DMA.
*/
static ddi_device_acc_attr_t nxge_dev_desc_dma_acc_attr = {
};
/*
* Device buffer access attributes for DMA.
*/
static ddi_device_acc_attr_t nxge_dev_buf_dma_acc_attr = {
};
DMA_ATTR_V0, /* version number. */
0, /* low address */
0xffffffffffffffff, /* high address */
0xffffffffffffffff, /* address counter max */
#ifndef NIU_PA_WORKAROUND
0x100000, /* alignment */
#else
0x2000,
#endif
0xfc00fc, /* dlim_burstsizes */
0x1, /* minimum transfer size */
0xffffffffffffffff, /* maximum transfer size */
0xffffffffffffffff, /* maximum segment size */
(unsigned int) 1, /* granularity */
0 /* attribute flags */
};
DMA_ATTR_V0, /* version number. */
0, /* low address */
0xffffffffffffffff, /* high address */
0xffffffffffffffff, /* address counter max */
#if defined(_BIG_ENDIAN)
0x2000, /* alignment */
#else
0x1000, /* alignment */
#endif
0xfc00fc, /* dlim_burstsizes */
0x1, /* minimum transfer size */
0xffffffffffffffff, /* maximum transfer size */
0xffffffffffffffff, /* maximum segment size */
(unsigned int) 1, /* granularity */
0 /* attribute flags */
};
DMA_ATTR_V0, /* version number. */
0, /* low address */
0xffffffffffffffff, /* high address */
0xffffffffffffffff, /* address counter max */
0x2000, /* alignment */
0xfc00fc, /* dlim_burstsizes */
0x1, /* minimum transfer size */
0xffffffffffffffff, /* maximum transfer size */
0xffffffffffffffff, /* maximum segment size */
(unsigned int) 1, /* granularity */
DDI_DMA_RELAXED_ORDERING /* attribute flags */
};
(uint_t)0, /* dlim_addr_lo */
0x1, /* dlim_minxfer */
1024 /* dlim_speed */
};
/*
* dma chunk sizes.
*
* Try to allocate the largest possible size
* so that fewer number of dma chunks would be managed
*/
#ifdef NIU_PA_WORKAROUND
#else
0x10000, 0x20000, 0x40000, 0x80000,
0x100000, 0x200000, 0x400000, 0x800000,
0x1000000, 0x2000000, 0x4000000};
#endif
/*
* Translate "dev_t" to a pointer to the associated "dev_info_t".
*/
static int
{
int instance;
int status = DDI_SUCCESS;
/*
* Get the device instance since we'll need to setup
* or retrieve a soft state for this instance.
*/
switch (cmd) {
case DDI_ATTACH:
break;
case DDI_RESUME:
break;
}
break;
}
} else {
}
goto nxge_attach_exit;
case DDI_PM_RESUME:
break;
}
break;
}
goto nxge_attach_exit;
default:
goto nxge_attach_exit;
}
goto nxge_attach_exit;
}
status = NXGE_ERROR;
goto nxge_attach_fail2;
}
goto nxge_attach_fail3;
}
"nxge_init_common_dev failed"));
goto nxge_attach_fail4;
}
" function %d. Only functions 0 and 1 are "
status = NXGE_ERROR;
goto nxge_attach_fail4;
}
}
else
/*
* Neptune has 4 ports, the first 2 ports use XMAC (10G MAC)
* internally, the rest 2 ports use BMAC (1G "Big" MAC).
* The two types of MACs have different characterizations.
*/
} else {
}
/*
* Setup the Ndd parameters for the this instance.
*/
/*
* Setup Register Tracing Buffer.
*/
/* init stats ptr */
/*
* read the vpd info from the eeprom into local data
* structure and check for the VPD info validity
*/
" Couldn't determine card type"
" .... exit "));
goto nxge_attach_fail5;
}
goto nxge_attach_fail;
}
/*
* Setup the Kstats for the driver.
*/
goto nxge_attach_fail;
}
#if defined(sun4v)
if ((status =
&nxgep->niu_min_ver)) != 0) {
"nxge_attach: "
"%s: cannot negotiate "
"hypervisor services "
"revision %d "
"group: 0x%lx "
"major: 0x%lx minor: 0x%lx "
"errno: %d",
status));
goto nxge_attach_fail;
}
"NIU Hypervisor service enabled"));
}
#endif
goto nxge_attach_fail;
}
if (status != DDI_SUCCESS) {
goto nxge_attach_fail;
}
if (status != DDI_SUCCESS) {
goto nxge_attach_fail;
}
if (status != DDI_SUCCESS) {
goto nxge_attach_fail;
}
/*
* Enable interrupts.
*/
"unable to register to mac layer (%d)", status));
goto nxge_attach_fail;
}
instance));
goto nxge_attach_exit;
goto nxge_attach_fail1;
/*
* Tear down the ndd parameters setup.
*/
/*
* Tear down the kstat setup.
*/
}
/*
* Unmap the register setup.
*/
status));
return (status);
}
static int
{
int status = DDI_SUCCESS;
int instance;
goto nxge_detach_exit;
}
switch (cmd) {
case DDI_DETACH:
break;
case DDI_PM_SUSPEND:
break;
case DDI_SUSPEND:
}
break;
default:
}
if (cmd != DDI_DETACH)
goto nxge_detach_exit;
/*
* Stop the xcvr polling.
*/
"<== nxge_detach status = 0x%08X", status));
return (DDI_FAILURE);
}
"<== nxge_detach (mac_unregister) status = 0x%08X", status));
status));
return (status);
}
static void
{
return;
}
nxgep->nxge_magic = 0;
if (nxgep->nxge_timerid) {
nxgep->nxge_timerid = 0;
}
}
#if defined(sun4v)
}
#endif
/*
* Stop any further interrupts.
*/
/* remove soft interrups */
/*
* Stop the device and free resources.
*/
/*
* Tear down the ndd parameters setup.
*/
/*
* Tear down the kstat setup.
*/
/*
* Destroy all mutexes.
*/
/*
* Remove the list of ndd parameters which
* were setup during attach.
*/
" nxge_unattach: remove all properties"));
}
#if NXGE_PROPERTY
#endif
/*
* Unmap the register setup.
*/
}
static char n2_siu_name[] = "niu";
static nxge_status_t
{
int ddi_status = DDI_SUCCESS;
char *devname;
#ifdef NXGE_DEBUG
char *sysname;
#endif
#if !defined(_BIG_ENDIAN)
#endif
"nxge_map_regs: pathname devname %s", devname));
/* get function number */
nxgep->function_num));
} else {
int *prop_val;
0, "reg",
"Reg property not found"));
goto nxge_map_regs_fail0;
} else {
"Reg property found: fun # %d",
func_num));
}
}
default:
"nxge_map_regs: pci config size 0x%x", regsize));
if (ddi_status != DDI_SUCCESS) {
"ddi_map_regs, nxge bus config regs failed"));
goto nxge_map_regs_fail0;
}
"nxge_map_reg: PCI config addr 0x%0llx "
dev_regs->nxge_pciregh));
/*
* IMP IMP
* workaround for bit swapping bug in HW
* which ends up in no-snoop = yes
* resulting, in DMA not synched properly
*/
#if !defined(_BIG_ENDIAN)
/* workarounds for x86 systems */
pcie_devctl = 0x0;
#endif
"nxge_map_regs: pio size 0x%x", regsize));
/* set up the device mapped register */
if (ddi_status != DDI_SUCCESS) {
"ddi_map_regs for Neptune global reg failed"));
goto nxge_map_regs_fail1;
}
"nxge_map_regs: msix size 0x%x", regsize));
if (ddi_status != DDI_SUCCESS) {
"ddi_map_regs for msi reg failed"));
goto nxge_map_regs_fail2;
}
/* set up the vio region mapped register */
"nxge_map_regs: vio size 0x%x", regsize));
if (ddi_status != DDI_SUCCESS) {
"ddi_map_regs for nxge vio reg failed"));
goto nxge_map_regs_fail3;
}
break;
case N2_NIU:
/*
* Set up the device mapped register (FWARC 2006/556)
* (changed back to 1: reg starts at 1!)
*/
"nxge_map_regs: dev size 0x%x", regsize));
if (ddi_status != DDI_SUCCESS) {
goto nxge_map_regs_fail1;
}
/* set up the vio region mapped register */
"nxge_map_regs: vio (1) size 0x%x", regsize));
if (ddi_status != DDI_SUCCESS) {
"ddi_map_regs for nxge vio reg failed"));
goto nxge_map_regs_fail2;
}
/* set up the vio region mapped register */
"nxge_map_regs: vio (3) size 0x%x", regsize));
if (ddi_status != DDI_SUCCESS) {
"ddi_map_regs for nxge vio2 reg failed"));
goto nxge_map_regs_fail3;
}
break;
}
goto nxge_map_regs_exit;
if (dev_regs->nxge_msix_regh) {
}
if (dev_regs->nxge_vir_regh) {
}
}
if (dev_regs->nxge_pciregh) {
}
if (ddi_status != DDI_SUCCESS)
return (status);
}
static void
{
"==> nxge_unmap_regs: bus"));
}
"==> nxge_unmap_regs: device registers"));
}
"==> nxge_unmap_regs: device interrupts"));
}
"==> nxge_unmap_regs: vio region"));
}
"==> nxge_unmap_regs: vio2 region"));
}
}
}
static nxge_status_t
{
int ddi_status = DDI_SUCCESS;
int partition;
/*
* Get the interrupt cookie so the mutexes can be
* Initialized.
*/
if (ddi_status != DDI_SUCCESS) {
"<== nxge_setup_mutexes: failed 0x%x", ddi_status));
goto nxge_setup_mutexes_exit;
}
/*
* Initialize mutexes for this device.
*/
/*
* FFLP Mutexes are never used in interrupt context
* as fflp operation can take very long time to
* complete and hence not suitable to invoke from interrupt
* handlers.
*/
if (NXGE_IS_VALID_NEPTUNE_TYPE(nxgep)) {
}
}
"<== nxge_setup_mutexes status = %x", status));
if (ddi_status != DDI_SUCCESS)
return (status);
}
static void
{
int partition;
/* Destroy all polling resources. */
/* free data structures, based on HW type */
if (NXGE_IS_VALID_NEPTUNE_TYPE(nxgep)) {
}
}
}
{
return (status);
}
/*
*/
goto nxge_init_fail1;
}
/*
* Initialize and enable TXC registers
* (Globally enable TX controller,
* enable a port, configure dma channel bitmap,
* configure the max burst size).
*/
goto nxge_init_fail2;
}
/*
* Initialize and enable TXDMA channels.
*/
goto nxge_init_fail3;
}
/*
* Initialize and enable RXDMA channels.
*/
goto nxge_init_fail4;
}
/*
* Initialize TCAM and FCRAM (Neptune).
*/
goto nxge_init_fail5;
}
/*
* Initialize ZCP
*/
goto nxge_init_fail5;
}
/*
* Initialize IPP.
*/
goto nxge_init_fail5;
}
/*
* Initialize the MAC block.
*/
goto nxge_init_fail5;
}
/*
* Enable hardware interrupts.
*/
goto nxge_init_exit;
(void) nxge_txc_uninit(nxgep);
"<== nxge_init status (failed) = 0x%08x", status));
return (status);
status));
return (status);
}
{
}
return (NULL);
}
/*ARGSUSED*/
void
{
if (timerid) {
}
}
void
{
"==> nxge_uninit: not initialized"));
"<== nxge_uninit"));
return;
}
/* stop timer */
if (nxgep->nxge_timerid) {
nxgep->nxge_timerid = 0;
}
(void) nxge_intr_hw_disable(nxgep);
/*
* Reset the receive MAC side.
*/
(void) nxge_rx_mac_disable(nxgep);
/* Disable and soft reset the IPP */
(void) nxge_ipp_disable(nxgep);
/* Free classification resources */
(void) nxge_classify_uninit(nxgep);
/*
*/
/*
* Reset the transmit MAC side.
*/
(void) nxge_tx_mac_disable(nxgep);
"nxge_mblks_pending %d", nxge_mblks_pending));
}
void
{
#if defined(__i386)
#else
#endif
int i, retry;
regdata = 0;
retry = 1;
for (i = 0; i < retry; i++) {
}
}
void
{
#if defined(__i386)
#else
#endif
#if defined(__i386)
#else
#endif
}
int nxge_debug_init = 0;
/*ARGSUSED*/
/*VARARGS*/
void
{
char msg_buffer[1048];
char prefix_buffer[32];
int instance;
if ((level & debug_level) ||
(level == NXGE_ERR_CTL)) {
/* do the msg processing */
if (nxge_debug_init == 0) {
nxge_debug_init = 1;
}
}
if (level & NXGE_ERR_CTL) {
}
instance = -1;
} else {
(void) sprintf(prefix_buffer,
}
}
}
char *
{
int i;
static char etherbuf[1024];
char digits[] = "0123456789abcdef";
if (!size)
size = 60;
if (size > MAX_DUMP_SZ) {
/* Dump the leading bytes */
for (i = 0; i < MAX_DUMP_SZ/2; i++) {
if (*ap > 0x0f)
*cp++ = ':';
}
for (i = 0; i < 20; i++)
*cp++ = '.';
/* Dump the last MAX_DUMP_SZ/2 bytes */
for (i = 0; i < MAX_DUMP_SZ/2; i++) {
if (*ap > 0x0f)
*cp++ = ':';
}
} else {
for (i = 0; i < size; i++) {
if (*ap > 0x0f)
*cp++ = ':';
}
}
*--cp = 0;
return (etherbuf);
}
#ifdef NXGE_DEBUG
static void
{
char *dev_ptr;
int i;
if (NXGE_IS_VALID_NEPTUNE_TYPE(nxgep)) {
"Neptune PCI regp cfg_ptr 0x%llx", (char *)cfg_ptr));
"Neptune PCI cfg_ptr vendor id ptr 0x%llx",
"\tvendorid 0x%x devid 0x%x",
"PCI BAR: base 0x%x base14 0x%x base 18 0x%x "
"bar1c 0x%x",
"\nNeptune PCI BAR: base20 0x%x base24 0x%x "
"base 28 0x%x bar2c 0x%x\n",
"\nNeptune PCI BAR: base30 0x%x\n",
"first 0x%llx second 0x%llx third 0x%llx "
"last 0x%llx ",
}
}
#endif
static void
{
}
static nxge_status_t
{
(void) nxge_rx_mac_enable(nxgep);
(void) nxge_tx_mac_enable(nxgep);
"<== nxge_resume status = 0x%x", status));
return (status);
}
static nxge_status_t
{
status = NXGE_ERROR;
}
" nxge_setup_dev status "
"(xcvr init 0x%08x)", status));
goto nxge_setup_dev_exit;
}
"<== nxge_setup_dev port %d status = 0x%08x",
return (status);
}
static void
{
(void) nxge_hw_stop(nxgep);
}
static nxge_status_t
{
int ddi_status = DDI_SUCCESS;
" nxge_setup_system_dma_pages: page %d (ddi_ptob %d) "
" default_block_size %d iommu_pagesize %d",
if (iommu_pagesize != 0) {
if (iommu_pagesize > 0x4000)
} else {
}
}
}
"==> nxge_setup_system_dma_pages: page %d (ddi_ptob %d) "
"default_block_size %d page mask %d",
nxgep->sys_page_mask));
switch (nxgep->sys_page_sz) {
default:
break;
case 0x1000:
break;
case 0x2000:
break;
case 0x4000:
break;
case 0x8000:
break;
}
#ifndef USE_RX_BIG_BUF
#else
#endif
/*
* Get the system DMA burst size.
*/
DDI_DMA_DONTWAIT, 0,
&nxgep->dmasparehandle);
if (ddi_status != DDI_SUCCESS) {
"ddi_dma_alloc_handle: failed "
" status 0x%x", ddi_status));
}
sizeof (nxgep->dmasparehandle),
DDI_DMA_DONTWAIT, 0,
if (ddi_status != DDI_DMA_MAPPED) {
"Binding spare handle to find system"
" burstsize failed."));
}
if (ddi_status != DDI_SUCCESS)
"<== nxge_setup_system_dma_pages status = 0x%08x", status));
return (status);
}
static nxge_status_t
{
return (NXGE_ERROR);
}
return (NXGE_ERROR);
}
return (NXGE_OK);
}
static void
{
}
static nxge_status_t
{
int i, j;
/*
* Allocate memory for each receive DMA channel.
*/
KM_SLEEP);
/*
* Assume that each DMA channel will be configured with default
* block size.
* rbr block counts are mod of batch count (16).
*/
if (!nxge_port_rbr_size) {
}
if (nxge_port_rbr_size % NXGE_RXDMA_POST_BATCH) {
}
}
if (nxge_port_rbr_size > RBR_DEFAULT_MAX_BLKS) {
"nxge_alloc_rx_mem_pool: RBR size too high %d, "
"set to default %d",
}
if (nxge_port_rcr_size > RCR_DEFAULT_MAX) {
"nxge_alloc_rx_mem_pool: RCR too high %d, "
"set to default %d",
}
/*
* memory allocation on data buffers to 4M (contig_mem_alloc)
* function).
*/
#if defined(sun4v) && defined(NIU_LP_WORKAROUND)
if ((nxge_port_rbr_size > NXGE_NIU_CONTIG_RBR_MAX) ||
(!ISP2(nxge_port_rbr_size))) {
}
if ((nxge_port_rcr_size > NXGE_NIU_CONTIG_RCR_MAX) ||
(!ISP2(nxge_port_rcr_size))) {
}
}
#endif
/*
* Addresses of receive block ring, receive completion ring and the
* mailbox must be all cache-aligned (64 bytes).
*/
rx_cntl_alloc_size *= (sizeof (rx_desc_t));
rx_cntl_alloc_size += sizeof (rxdma_mailbox_t);
"nxge_port_rbr_size = %d nxge_port_rbr_spare_size = %d "
"nxge_port_rcr_size = %d "
"rx_cntl_alloc_size = %d",
#if defined(sun4v) && defined(NIU_LP_WORKAROUND)
if (!ISP2(rx_buf_alloc_size)) {
"==> nxge_alloc_rx_mem_pool: "
" must be power of 2"));
}
"==> nxge_alloc_rx_mem_pool: "
" limit size to 4M"));
}
if (rx_cntl_alloc_size < 0x2000) {
rx_cntl_alloc_size = 0x2000;
}
}
#endif
/*
* Allocate memory for receive buffers and descriptor rings.
* Replace allocation functions with interface functions provided
* by the partition manager when it is available.
*/
/*
* Allocate memory for the receive buffer blocks.
*/
for (i = 0; i < ndmas; i++) {
" nxge_alloc_rx_mem_pool to alloc mem: "
" dma %d dma_buf_p %llx &dma_buf_p %llx",
num_chunks[i] = 0;
break;
}
st_rdc++;
" nxge_alloc_rx_mem_pool DONE alloc mem: "
"dma %d dma_buf_p %llx &dma_buf_p %llx", i,
}
if (i < ndmas) {
goto nxge_alloc_rx_mem_fail1;
}
/*
* Allocate memory for descriptor rings and mailbox.
*/
for (j = 0; j < ndmas; j++) {
break;
}
st_rdc++;
}
if (j < ndmas) {
goto nxge_alloc_rx_mem_fail2;
}
/* Free control buffers */
j--;
"==> nxge_alloc_rx_mem_pool: freeing control bufs (%d)", j));
for (; j >= 0; j--) {
"==> nxge_alloc_rx_mem_pool: control bufs freed (%d)",
j));
}
"==> nxge_alloc_rx_mem_pool: control bufs freed (%d)", j));
/* Free data buffers */
i--;
"==> nxge_alloc_rx_mem_pool: freeing data bufs (%d)", i));
for (; i >= 0; i--) {
num_chunks[i]);
}
"==> nxge_alloc_rx_mem_pool: data bufs freed (%d)", i));
"<== nxge_alloc_rx_mem_pool:status 0x%08x", status));
return (status);
}
static void
{
"<== nxge_free_rx_mem_pool "
"(null rx buf pool or buf not allocated"));
return;
}
"<== nxge_free_rx_mem_pool "
"(null rx cntl buf pool or cntl buf not allocated"));
return;
}
for (i = 0; i < ndmas; i++) {
}
for (i = 0; i < ndmas; i++) {
}
for (i = 0; i < ndmas; i++) {
sizeof (nxge_dma_common_t) * NXGE_DMA_BLOCK);
}
}
static nxge_status_t
{
int i, size_index, array_size;
KM_SLEEP);
" alloc_rx_buf_dma rdc %d asize %x bsize %x bbuf %llx ",
#if defined(RX_USE_RECLAIM_POST)
#endif
i = 0;
size_index = 0;
(size_index < array_size))
size_index++;
if (size_index >= array_size) {
}
while ((allocated < total_alloc_size) &&
(size_index >= 0) && (i < NXGE_DMA_BLOCK)) {
rx_dmap[i].dma_chunk_index = i;
/*
* needs to call Hypervisor api to set up
* logical pages.
*/
}
"alloc_rx_buf_dma rdc %d chunk %d bufp %llx size %x "
"i %d nblocks %d alength %d",
(p_nxge_dma_common_t)(&rx_dmap[i]));
" nxge_alloc_rx_buf_dma: Alloc Failed "));
size_index--;
} else {
" alloc_rx_buf_dma allocated rdc %d "
"chunk %d size %x dvma %x bufp %llx ",
i++;
}
}
if (allocated < total_alloc_size) {
"==> nxge_alloc_rx_buf_dma: not enough for channe %d "
"allocated 0x%x requested 0x%x",
status = NXGE_ERROR;
goto nxge_alloc_rx_mem_fail1;
}
"==> nxge_alloc_rx_buf_dma: Allocated for channe %d "
"allocated 0x%x requested 0x%x",
" alloc_rx_buf_dma rdc %d allocated %d chunks",
dma_channel, i));
*num_chunks = i;
goto nxge_alloc_rx_mem_exit;
"<== nxge_alloc_rx_buf_dma status 0x%08x", status));
return (status);
}
/*ARGSUSED*/
static void
{
int i;
"==> nxge_free_rx_buf_dma: # of chunks %d", num_chunks));
for (i = 0; i < num_chunks; i++) {
"==> nxge_free_rx_buf_dma: chunk %d dmap 0x%llx",
i, dmap));
}
}
/*ARGSUSED*/
static nxge_status_t
{
size,
rx_dmap);
}
"<== nxge_alloc_rx_cntl_dma status 0x%08x", status));
return (status);
}
/*ARGSUSED*/
static void
{
}
static nxge_status_t
{
int i, j;
"p_cfgp 0x%016llx start_tdc %d ndmas %d nxgep->max_tdcs %d",
/*
* Allocate memory for each transmit DMA channel.
*/
KM_SLEEP);
if (nxge_tx_ring_size > TDC_DEFAULT_MAX) {
"nxge_alloc_tx_mem_pool: TDC too high %d, "
"set to default %d",
}
#if defined(sun4v) && defined(NIU_LP_WORKAROUND)
/*
* memory allocation on data buffers to 4M (contig_mem_alloc)
* function). The transmit ring is limited to 8K (includes the
* mailbox).
*/
if ((nxge_tx_ring_size > NXGE_NIU_CONTIG_TX_MAX) ||
(!ISP2(nxge_tx_ring_size))) {
}
}
#endif
/*
* Assume that each DMA channel will be configured with default
* transmit bufer size for copying transmit data.
* (For packet payload over this limit, packets will not be
* copied.)
*/
} else {
}
/*
* Addresses of transmit descriptor ring and the
* mailbox must be all cache-aligned (64 bytes).
*/
tx_cntl_alloc_size *= (sizeof (tx_desc_t));
tx_cntl_alloc_size += sizeof (txdma_mailbox_t);
#if defined(sun4v) && defined(NIU_LP_WORKAROUND)
if (!ISP2(tx_buf_alloc_size)) {
"==> nxge_alloc_tx_mem_pool: "
" must be power of 2"));
}
"==> nxge_alloc_tx_mem_pool: "
" limit size to 4M"));
}
if (tx_cntl_alloc_size < 0x2000) {
tx_cntl_alloc_size = 0x2000;
}
}
#endif
/*
* Allocate memory for transmit buffers and descriptor rings.
* Replace allocation functions with interface functions provided
* by the partition manager when it is available.
*
* Allocate memory for the transmit buffer pool.
*/
for (i = 0; i < ndmas; i++) {
num_chunks[i] = 0;
bcopy_thresh, &num_chunks[i]);
break;
}
st_tdc++;
}
if (i < ndmas) {
}
/*
* Allocate memory for descriptor rings and mailbox.
*/
for (j = 0; j < ndmas; j++) {
break;
}
st_tdc++;
}
if (j < ndmas) {
}
"==> nxge_alloc_tx_mem_pool: start_tdc %d "
"ndmas %d poolp->ndmas %d",
/* Free control buffers */
j--;
for (; j >= 0; j--) {
}
/* Free data buffers */
i--;
for (; i >= 0; i--) {
num_chunks[i]);
}
"<== nxge_alloc_tx_mem_pool:status 0x%08x", status));
return (status);
}
static nxge_status_t
{
int i, size_index, array_size;
KM_SLEEP);
i = 0;
size_index = 0;
(size_index < array_size))
size_index++;
if (size_index >= array_size) {
}
while ((allocated < total_alloc_size) &&
(size_index >= 0) && (i < NXGE_DMA_BLOCK)) {
tx_dmap[i].dma_chunk_index = i;
/*
* needs to call Hypervisor api to set up
* logical pages.
*/
}
(p_nxge_dma_common_t)(&tx_dmap[i]));
size_index--;
} else {
i++;
}
}
if (allocated < total_alloc_size) {
"==> nxge_alloc_tx_buf_dma: not enough channel %d: "
"allocated 0x%x requested 0x%x",
status = NXGE_ERROR;
goto nxge_alloc_tx_mem_fail1;
}
"==> nxge_alloc_tx_buf_dma: Allocated for channel %d: "
"allocated 0x%x requested 0x%x",
*num_chunks = i;
"==> nxge_alloc_tx_buf_dma dmap 0x%016llx num chunks %d",
*dmap, i));
goto nxge_alloc_tx_mem_exit;
"<== nxge_alloc_tx_buf_dma status 0x%08x", status));
return (status);
}
/*ARGSUSED*/
static void
{
int i;
for (i = 0; i < num_chunks; i++) {
}
}
/*ARGSUSED*/
static nxge_status_t
{
size,
tx_dmap);
}
"<== nxge_alloc_tx_cntl_dma status 0x%08x", status));
return (status);
}
/*ARGSUSED*/
static void
{
}
static void
{
"<== nxge_free_tx_mem_pool "
"(null rx buf pool or buf not allocated"));
return;
}
"<== nxge_free_tx_mem_pool "
"(null tx cntl buf pool or cntl buf not allocated"));
return;
}
for (i = 0; i < ndmas; i++) {
}
for (i = 0; i < ndmas; i++) {
}
for (i = 0; i < ndmas; i++) {
sizeof (nxge_dma_common_t) * NXGE_DMA_BLOCK);
}
}
/*ARGSUSED*/
static nxge_status_t
struct ddi_dma_attr *dma_attrp,
{
int ddi_status = DDI_SUCCESS;
/*
* contig_alloc_type for contiguous memory only allowed
*/
"nxge_dma_mem_alloc: alloc type not allows (%d)",
return (NXGE_ERROR | NXGE_DDI_FAILED);
}
if (ddi_status != DDI_SUCCESS) {
"nxge_dma_mem_alloc:ddi_dma_alloc_handle failed."));
return (NXGE_ERROR | NXGE_DDI_FAILED);
}
switch (contig_alloc_type) {
case B_FALSE:
&dma_p->acc_handle);
if (ddi_status != DDI_SUCCESS) {
"nxge_dma_mem_alloc:ddi_dma_mem_alloc failed"));
return (NXGE_ERROR | NXGE_DDI_FAILED);
}
"nxge_dma_mem_alloc:ddi_dma_mem_alloc "
"< length."));
return (NXGE_ERROR);
}
if (ddi_status != DDI_DMA_MAPPED) {
"nxge_dma_mem_alloc:di_dma_addr_bind failed "
"(staus 0x%x ncookies %d.)", ddi_status,
if (dma_p->acc_handle) {
}
return (NXGE_ERROR | NXGE_DDI_FAILED);
}
"nxge_dma_mem_alloc:ddi_dma_addr_bind "
"> 1 cookie"
"(staus 0x%x ncookies %d.)", ddi_status,
if (dma_p->acc_handle) {
}
return (NXGE_ERROR);
}
break;
#if defined(sun4v) && defined(NIU_LP_WORKAROUND)
case B_TRUE:
"nxge_dma_mem_alloc:contig_mem_alloc failed."));
return (NXGE_ERROR | NXGE_DDI_FAILED);
}
if (ddi_status != DDI_DMA_MAPPED) {
"nxge_dma_mem_alloc:di_dma_addr_bind failed "
"(status 0x%x ncookies %d.)", ddi_status,
"==> nxge_dma_mem_alloc: (not mapped)"
"length %lu (0x%x) "
"free contig kaddrp $%p "
"va_to_pa $%p",
return (NXGE_ERROR | NXGE_DDI_FAILED);
}
"nxge_dma_mem_alloc:di_dma_addr_bind > 1 "
"cookie or "
"dmac_laddress is NULL $%p size %d "
" (status 0x%x ncookies %d.)",
return (NXGE_ERROR | NXGE_DDI_FAILED);
}
break;
#else
case B_TRUE:
"nxge_dma_mem_alloc: invalid alloc type for !sun4v"));
return (NXGE_ERROR | NXGE_DDI_FAILED);
#endif
}
#if defined(__i386)
#else
#endif
#if defined(__i386)
#else
#endif
#if defined(sun4v) && defined(NIU_LP_WORKAROUND)
#endif
"dma buffer allocated: dma_p $%p "
"return dmac_ladress from cookie $%p cookie dmac_size %d "
"dma_p->ioaddr_p $%p "
"dma_p->orig_ioaddr_p $%p "
"orig_vatopa $%p "
"alength %d (0x%x) "
"kaddrp $%p "
"length %d (0x%x)",
return (NXGE_OK);
}
static void
{
}
}
}
#if defined(sun4v) && defined(NIU_LP_WORKAROUND)
if (dma_p->contig_alloc_type &&
"kaddrp $%p (orig_kaddrp $%p)"
"mem type %d ",
"orig_alength %d "
"alength 0x%x (%d)",
}
#endif
}
/*
* nxge_m_start() -- start transmitting and receiving.
*
* This function is called by the MAC layer when the first
* stream is open to prepare the hardware ready for sending
* and transmitting packets.
*/
static int
nxge_m_start(void *arg)
{
"<== nxge_m_start: initialization failed"));
return (EIO);
}
goto nxge_m_start_exit;
/*
* Start timer to check the system error and tx hangs
*/
return (0);
}
/*
* nxge_m_stop(): stop transmitting and receiving.
*/
static void
nxge_m_stop(void *arg)
{
if (nxgep->nxge_timerid) {
nxgep->nxge_timerid = 0;
}
}
static int
{
struct ether_addr addrp;
"<== nxge_m_unicst: set unitcast failed"));
return (EINVAL);
}
return (0);
}
static int
{
struct ether_addr addrp;
"==> nxge_m_multicst: add %d", add));
if (add) {
"<== nxge_m_multicst: add multicast failed"));
return (EINVAL);
}
} else {
"<== nxge_m_multicst: del multicast failed"));
return (EINVAL);
}
}
return (0);
}
static int
{
"==> nxge_m_promisc: on %d", on));
"<== nxge_m_promisc: set promisc failed"));
return (EINVAL);
}
"<== nxge_m_promisc: on %d", on));
return (0);
}
static void
{
int err;
int cmd;
switch (cmd) {
default:
return;
case LB_GET_INFO_SIZE:
case LB_GET_INFO:
case LB_GET_MODE:
break;
case LB_SET_MODE:
break;
case ND_GET:
break;
case ND_SET:
break;
case NXGE_GET_MII:
case NXGE_PUT_MII:
case NXGE_GET64:
case NXGE_PUT64:
case NXGE_GET_TX_RING_SZ:
case NXGE_GET_TX_DESC:
case NXGE_TX_SIDE_RESET:
case NXGE_RX_SIDE_RESET:
case NXGE_GLOBAL_RESET:
case NXGE_RESET_MAC:
case NXGE_TX_REGS_DUMP:
case NXGE_RX_REGS_DUMP:
case NXGE_INT_REGS_DUMP:
case NXGE_VIR_INT_REGS_DUMP:
case NXGE_PUT_TCAM:
case NXGE_GET_TCAM:
case NXGE_RTRACE:
case NXGE_RDUMP:
break;
case NXGE_INJECT_ERR:
break;
}
if (need_privilege) {
if (err != 0) {
"<== nxge_m_ioctl: no priv"));
return;
}
}
switch (cmd) {
case ND_GET:
case ND_SET:
break;
case LB_GET_MODE:
case LB_SET_MODE:
case LB_GET_INFO_SIZE:
case LB_GET_INFO:
break;
case NXGE_GET_MII:
case NXGE_PUT_MII:
case NXGE_PUT_TCAM:
case NXGE_GET_TCAM:
case NXGE_GET64:
case NXGE_PUT64:
case NXGE_GET_TX_RING_SZ:
case NXGE_GET_TX_DESC:
case NXGE_TX_SIDE_RESET:
case NXGE_RX_SIDE_RESET:
case NXGE_GLOBAL_RESET:
case NXGE_RESET_MAC:
case NXGE_TX_REGS_DUMP:
case NXGE_RX_REGS_DUMP:
case NXGE_INT_REGS_DUMP:
case NXGE_VIR_INT_REGS_DUMP:
"==> nxge_m_ioctl: cmd 0x%x", cmd));
break;
}
}
static void
nxge_m_resources(void *arg)
{
/*
* CR 6492541 Check to see if the drv_state has been initialized,
* if not * call nxge_init().
*/
goto nxge_m_resources_exit;
}
/*
* Export our receive resources to the MAC layer.
*/
for (i = 0; i < ndmas; i++) {
(mac_resource_t *)&mrf);
"==> nxge_m_resources: vdma %d dma %d "
"rcrptr 0x%016llx mac_handle 0x%016llx",
rcr_p[i],
}
}
static void
{
int i;
for (i = 0; i < ETHERADDRL; i++) {
if (factory) {
} else {
}
}
}
/*
* nxge_altmac_set() -- Set an alternate MAC address
*/
static int
{
return (EIO);
/*
* Set the rdc table number for the host info entry
* for this mac address slot.
*/
return (EIO);
}
/*
* Enable comparison with the alternate MAC address.
* While the first alternate addr is enabled by bit 1 of register
* BMAC_ALTAD_CMPEN, it is enabled by bit 0 of register
* XMAC_ADDR_CMPEN, so slot needs to be converted to addrn
* accordingly before calling npi_mac_altaddr_entry.
*/
else
!= NPI_SUCCESS)
return (EIO);
return (0);
}
/*
* nxeg_m_mmac_add() - find an unused address slot, set the address
* value to the one specified, enable the port to start filtering on
* the new MAC address. Returns 0 on success.
*/
static int
{
int err;
/*
* Make sure that nxge is initialized, if _start() has
* not been called.
*/
return (ENXIO);
}
}
return (ENOSPC);
}
maddr->mma_addrlen)) {
return (EINVAL);
}
/*
* Search for the first available slot. Because naddrfree
* is not zero, we are guaranteed to find one.
* Slot 0 is for unique (primary) MAC. The first alternate
* MAC slot is slot 1.
* Each of the first two ports of Neptune has 16 alternate
* MAC slots but only the first 7 (or 15) slots have assigned factory
* MAC addresses. We first search among the slots without bundled
* factory MACs. If we fail to find one in that range, then we
* search the slots with bundled factory MACs. A factory MAC
* will be wasted while the slot is used with a user MAC address.
* But the slot could be used by factory MAC again after calling
* nxge_m_mmac_remove and nxge_m_mmac_reserve.
*/
break;
}
slot++) {
& MMAC_SLOT_USED))
break;
}
}
} else {
break;
}
}
return (err);
}
return (0);
}
/*
* This function reserves an unused slot and programs the slot and the HW
* with a factory mac address.
*/
static int
{
int err;
/*
* Make sure that nxge is initialized, if _start() has
* not been called.
*/
return (ENXIO);
}
}
return (ENOSPC);
}
break;
}
return (ENOSPC);
}
}
/*
* Do not support factory MAC at a slot greater than
* num_factory_mmac even when there are available factory
* MAC addresses because the alternate MACs are bundled with
* slot[1] through slot[num_factory_mmac]
*/
return (EINVAL);
}
return (EBUSY);
}
/* Verify the address to be reserved */
return (EINVAL);
}
return (err);
}
/* Pass info back to the caller */
return (0);
}
/*
* Remove the specified mac address and update the HW not to filter
* the mac address anymore.
*/
static int
{
int err = 0;
/*
* Make sure that nxge is initialized, if _start() has
* not been called.
*/
return (ENXIO);
}
}
return (EINVAL);
}
else
== NPI_SUCCESS) {
/*
* Regardless if the MAC we just stopped filtering
* is a user addr or a facory addr, we must set
* the MMAC_VENDOR_ADDR flag if this slot has an
* associated factory MAC to indicate that a factory
* MAC is available.
*/
|= MMAC_VENDOR_ADDR;
}
/*
* Clear mac_pool[slot].addr so that kstat shows 0
* alternate MAC address if the slot is not used.
* (But nxge_m_mmac_get returns the factory MAC even
* when the slot is not used!)
*/
} else {
}
} else {
}
return (err);
}
/*
* Modify a mac address added by nxge_m_mmac_add or nxge_m_mmac_reserve().
*/
static int
{
int err = 0;
maddr->mma_addrlen))
return (EINVAL);
/*
* Make sure that nxge is initialized, if _start() has
* not been called.
*/
return (ENXIO);
}
}
return (EINVAL);
}
!= 0) {
/*
* Assume that the MAC passed down from the caller
* is not a factory MAC address (The user should
* call mmac_remove followed by mmac_reserve if
* he wants to use the factory MAC for this slot).
*/
}
} else {
}
return (err);
}
/*
* nxge_m_mmac_get() - Get the MAC address and other information
* related to the slot. mma_flags should be set to 0 in the call.
* Note: although kstat shows MAC address as zero when a slot is
* not used, Crossbow expects nxge_m_mmac_get to copy factory MAC
* to the caller as long as the slot is not using a user MAC address.
* The following table shows the rules,
*
* USED VENDOR mma_addr
* ------------------------------------------------------------
* (1) Slot uses a user MAC: yes no user MAC
* (2) Slot uses a factory MAC: yes yes factory MAC
* (3) Slot is not used but is
* factory MAC capable: no yes factory MAC
* (4) Slot is not used and is
* not factory MAC capable: no no 0
* ------------------------------------------------------------
*/
static int
{
/*
* Make sure that nxge is initialized, if _start() has
* not been called.
*/
return (ENXIO);
}
}
return (EINVAL);
}
} else {
} else {
maddr->mma_addrlen = 0;
}
}
return (0);
}
static boolean_t
{
switch (cap) {
case MAC_CAPAB_HCKSUM:
break;
case MAC_CAPAB_POLL:
/*
* There's nothing for us to fill in, simply returning
* B_TRUE stating that we support polling is sufficient.
*/
break;
case MAC_CAPAB_MULTIADDRESS:
/*
* maddr_handle is driver's private data, passed back to
* entry point functions as arg.
*/
break;
case MAC_CAPAB_LSO: {
if (nxge_lso_enable) {
if (nxge_lso_max > NXGE_LSO_MAXLEN) {
}
break;
} else {
return (B_FALSE);
}
}
default:
return (B_FALSE);
}
return (B_TRUE);
}
/*
* Module loading and removing entry points.
*/
static struct cb_ops nxge_cb_ops = {
nodev, /* cb_open */
nodev, /* cb_close */
nodev, /* cb_strategy */
nodev, /* cb_print */
nodev, /* cb_dump */
nodev, /* cb_read */
nodev, /* cb_write */
nodev, /* cb_ioctl */
nodev, /* cb_devmap */
nodev, /* cb_mmap */
nodev, /* cb_segmap */
nochpoll, /* cb_chpoll */
ddi_prop_op, /* cb_prop_op */
NULL,
D_MP, /* cb_flag */
CB_REV, /* rev */
nodev, /* int (*cb_aread)() */
nodev /* int (*cb_awrite)() */
};
static struct dev_ops nxge_dev_ops = {
DEVO_REV, /* devo_rev */
0, /* devo_refcnt */
nulldev, /* devo_identify */
nulldev, /* devo_probe */
nxge_attach, /* devo_attach */
nxge_detach, /* devo_detach */
nodev, /* devo_reset */
&nxge_cb_ops, /* devo_cb_ops */
ddi_power /* devo_power */
};
extern struct mod_ops mod_driverops;
#define NXGE_DESC_VER "Sun NIU 10Gb Ethernet"
/*
* Module linkage information for the kernel.
*/
static struct modldrv nxge_modldrv = {
};
static struct modlinkage modlinkage = {
};
int
_init(void)
{
int status;
if (status != 0) {
"failed to init device soft state"));
goto _init_exit;
}
if (status != 0) {
goto _init_exit;
}
return (status);
}
int
_fini(void)
{
int status;
if (nxge_mblks_pending)
return (EBUSY);
if (status != DDI_SUCCESS) {
"Module removal failed 0x%08x",
status));
goto _fini_exit;
}
return (status);
}
int
{
int status;
return (status);
}
/*ARGSUSED*/
static nxge_status_t
{
int intr_types;
int type = 0;
int ddi_status = DDI_SUCCESS;
} else if (nxge_msi_enable) {
}
/* Get the supported interrupt types */
!= DDI_SUCCESS) {
"ddi_intr_get_supported_types failed: status 0x%08x",
ddi_status));
return (NXGE_ERROR | NXGE_DDI_FAILED);
}
"ddi_intr_get_supported_types: 0x%08x", intr_types));
/*
* Solaris MSIX is not supported yet. use MSI for now.
* nxge_msi_enable (1):
* 1 - MSI 2 - MSI-X others - FIXED
*/
switch (nxge_msi_enable) {
default:
"use fixed (intx emulation) type %08x",
type));
break;
case 2:
"ddi_intr_get_supported_types: 0x%08x", intr_types));
if (intr_types & DDI_INTR_TYPE_MSIX) {
"ddi_intr_get_supported_types: MSIX 0x%08x",
type));
} else if (intr_types & DDI_INTR_TYPE_MSI) {
"ddi_intr_get_supported_types: MSI 0x%08x",
type));
} else if (intr_types & DDI_INTR_TYPE_FIXED) {
"ddi_intr_get_supported_types: MSXED0x%08x",
type));
}
break;
case 1:
if (intr_types & DDI_INTR_TYPE_MSI) {
"ddi_intr_get_supported_types: MSI 0x%08x",
type));
} else if (intr_types & DDI_INTR_TYPE_MSIX) {
"ddi_intr_get_supported_types: MSIX 0x%08x",
type));
} else if (intr_types & DDI_INTR_TYPE_FIXED) {
"ddi_intr_get_supported_types: MSXED0x%08x",
type));
}
}
type == DDI_INTR_TYPE_FIXED) &&
" nxge_add_intrs: "
" nxge_add_intrs_adv failed: status 0x%08x",
status));
return (status);
} else {
"interrupts registered : type %d", type));
"\nAdded advanced nxge add_intr_adv "
"intr type 0x%x\n", type));
return (status);
}
}
"failed to register interrupts"));
return (NXGE_ERROR | NXGE_DDI_FAILED);
}
return (status);
}
/*ARGSUSED*/
static nxge_status_t
{
int ddi_status = DDI_SUCCESS;
&nxgep->resched_id,
if (ddi_status != DDI_SUCCESS) {
"ddi_add_softintrs failed: status 0x%08x",
ddi_status));
return (NXGE_ERROR | NXGE_DDI_FAILED);
}
return (status);
}
static nxge_status_t
{
int intr_type;
intr_type));
switch (intr_type) {
case DDI_INTR_TYPE_MSI: /* 0x2 */
case DDI_INTR_TYPE_MSIX: /* 0x4 */
case DDI_INTR_TYPE_FIXED: /* 0x1 */
default:
return (NXGE_ERROR);
}
}
/*ARGSUSED*/
static nxge_status_t
{
int behavior;
int inum = 0;
int x, y;
int ddi_status = DDI_SUCCESS;
intrp->start_inum = 0;
"ddi_intr_get_nintrs() failed, status: 0x%x%, "
return (NXGE_ERROR | NXGE_DDI_FAILED);
}
"ddi_intr_get_navail() failed, status: 0x%x%, "
return (NXGE_ERROR | NXGE_DDI_FAILED);
}
"ddi_intr_get_navail() returned: nintrs %d, navail %d",
/* PSARC/2007/453 MSI-X interrupt limit override */
if (int_type == DDI_INTR_TYPE_MSIX) {
"nxge_add_intrs_adv_type: nintrs %d "
"navail %d (nrequest %d)",
}
}
/* MSI must be power of 2 */
navail = 16;
navail = 8;
navail = 4;
navail = 2;
} else {
navail = 1;
}
"ddi_intr_get_navail(): (msi power of 2) nintrs %d, "
}
" ddi_intr_alloc() failed: %d",
ddi_status));
return (NXGE_ERROR | NXGE_DDI_FAILED);
}
" ddi_intr_get_pri() failed: %d",
ddi_status));
/* Free already allocated interrupts */
for (y = 0; y < nactual; y++) {
}
return (NXGE_ERROR | NXGE_DDI_FAILED);
}
nrequired = 0;
default:
break;
case N2_NIU:
break;
}
"nxge_add_intrs_adv_typ:nxge_ldgv_init "
"failed: 0x%x", status));
/* Free already allocated interrupts */
for (y = 0; y < nactual; y++) {
}
return (status);
}
"nxge_add_intrs_adv_type: "
"arg1 0x%x arg2 0x%x: "
"1-1 int handler (entry %d intdata 0x%x)\n",
"nxge_add_intrs_adv_type: "
"arg1 0x%x arg2 0x%x: "
"nldevs %d int handler "
"(entry %d intdata 0x%x)\n",
}
"==> nxge_add_intrs_adv_type: ddi_add_intr(inum) #%d "
!= DDI_SUCCESS) {
"==> nxge_add_intrs_adv_type: failed #%d "
"status 0x%x", x, ddi_status));
for (y = 0; y < intrp->intr_added; y++) {
(void) ddi_intr_remove_handler(
}
/* Free already allocated intr */
for (y = 0; y < nactual; y++) {
}
(void) nxge_ldgv_uninit(nxgep);
return (NXGE_ERROR | NXGE_DDI_FAILED);
}
intrp->intr_added++;
}
"Requested: %d, Allowed: %d msi_intx_cnt %d intr_added %d",
intrp->intr_added));
(void) nxge_intr_ldgv_init(nxgep);
return (status);
}
/*ARGSUSED*/
static nxge_status_t
{
int behavior;
int inum = 0;
int x, y;
int ddi_status = DDI_SUCCESS;
intrp->start_inum = 0;
"ddi_intr_get_nintrs() failed, status: 0x%x%, "
return (NXGE_ERROR | NXGE_DDI_FAILED);
}
"ddi_intr_get_navail() failed, status: 0x%x%, "
return (NXGE_ERROR | NXGE_DDI_FAILED);
}
"ddi_intr_get_navail() returned: nintrs %d, naavail %d",
" ddi_intr_alloc() failed: %d",
ddi_status));
return (NXGE_ERROR | NXGE_DDI_FAILED);
}
" ddi_intr_get_pri() failed: %d",
ddi_status));
/* Free already allocated interrupts */
for (y = 0; y < nactual; y++) {
}
return (NXGE_ERROR | NXGE_DDI_FAILED);
}
nrequired = 0;
default:
break;
case N2_NIU:
break;
}
"nxge_add_intrs_adv_type_fix:nxge_ldgv_init "
"failed: 0x%x", status));
/* Free already allocated interrupts */
for (y = 0; y < nactual; y++) {
}
return (status);
}
}
"nxge_add_intrs_adv_type_fix: "
"1-1 int handler(%d) ldg %d ldv %d "
"arg1 $%p arg2 $%p\n",
"nxge_add_intrs_adv_type_fix: "
"shared ldv %d int handler(%d) ldv %d ldg %d"
"arg1 0x%016llx arg2 0x%016llx\n",
}
!= DDI_SUCCESS) {
"==> nxge_add_intrs_adv_type_fix: failed #%d "
"status 0x%x", x, ddi_status));
for (y = 0; y < intrp->intr_added; y++) {
(void) ddi_intr_remove_handler(
}
for (y = 0; y < nactual; y++) {
}
/* Free already allocated intr */
(void) nxge_ldgv_uninit(nxgep);
return (NXGE_ERROR | NXGE_DDI_FAILED);
}
intrp->intr_added++;
}
return (status);
}
static void
{
int i, inum;
if (!intrp->intr_registered) {
"<== nxge_remove_intrs: interrupts not registered"));
return;
}
intrp->intr_added);
} else {
for (i = 0; i < intrp->intr_added; i++) {
}
}
}
}
"nxge_remove_intrs: ddi_intr_free inum %d "
"msi_intx_cnt %d intr_added %d",
inum,
intrp->intr_added));
}
}
intrp->msi_intx_cnt = 0;
intrp->intr_added = 0;
(void) nxge_ldgv_uninit(nxgep);
"#msix-request");
}
/*ARGSUSED*/
static void
{
if (nxgep->resched_id) {
"==> nxge_remove_soft_intrs: removed"));
}
}
/*ARGSUSED*/
static void
{
int i;
int status;
if (!intrp->intr_registered) {
"interrupts are not registered"));
return;
}
if (intrp->intr_enabled) {
"<== nxge_intrs_enable: already enabled"));
return;
}
intrp->intr_added);
"block enable - status 0x%x total inums #%d\n",
} else {
for (i = 0; i < intrp->intr_added; i++) {
"ddi_intr_enable:enable - status 0x%x "
"total inums %d enable inum #%d\n",
if (status == DDI_SUCCESS) {
}
}
}
}
/*ARGSUSED*/
static void
{
int i;
if (!intrp->intr_registered) {
"interrupts are not registered"));
return;
}
intrp->intr_added);
} else {
for (i = 0; i < intrp->intr_added; i++) {
}
}
}
static nxge_status_t
{
int status;
return (NXGE_ERROR);
if (status != 0) {
"!nxge_mac_register failed (status %d instance %d)",
return (NXGE_ERROR);
}
return (NXGE_OK);
}
void
{
size = 1024;
switch (blk_id) {
case MAC_BLK_ID:
break;
case TXMAC_BLK_ID:
break;
case RXMAC_BLK_ID:
break;
case MIF_BLK_ID:
break;
case IPP_BLK_ID:
break;
case TXC_BLK_ID:
break;
case TXDMA_BLK_ID:
break;
case RXDMA_BLK_ID:
break;
case ZCP_BLK_ID:
break;
case ESPC_BLK_ID:
break;
case FFLP_BLK_ID:
break;
case PHY_BLK_ID:
break;
case ETHER_SERDES_BLK_ID:
break;
case PCIE_SERDES_BLK_ID:
break;
case VIR_BLK_ID:
break;
}
}
static int
{
"==> nxge_init_common_dev:func # %d",
nxgep->function_num));
/*
* Loop through existing per neptune hardware list.
*/
"==> nxge_init_common_device:func # %d "
"hw_p $%p parent dip $%p",
hw_p,
p_dip));
"==> nxge_init_common_device:func # %d "
"hw_p $%p parent dip $%p "
"ndevs %d (found)",
hw_p,
break;
}
}
"==> nxge_init_common_device:func # %d "
"parent dip $%p (new)",
p_dip));
} else {
}
nxge_hw_list = hw_p;
}
}
"==> nxge_init_common_device (nxge_hw_list) $%p",
nxge_hw_list));
return (NXGE_OK);
}
static void
{
"<== nxge_uninit_common_device (no common)"));
return;
}
"==> nxge_uninit_common_device:func # %d "
"hw_p $%p parent dip $%p "
"ndevs %d (found)",
hw_p,
}
"==> nxge_uninit_common_device: "
"func # %d "
"hw_p $%p parent dip $%p "
"ndevs %d (last)",
hw_p,
if (hw_p == nxge_hw_list) {
"==> nxge_uninit_common_device:"
"remove head func # %d "
"hw_p $%p parent dip $%p "
"ndevs %d (head)",
hw_p,
} else {
"==> nxge_uninit_common_device:"
"remove middle func # %d "
"hw_p $%p parent dip $%p "
"ndevs %d (middle)",
hw_p,
}
}
break;
} else {
}
}
"==> nxge_uninit_common_device (nxge_hw_list) $%p",
nxge_hw_list));
}
/*
* Determines the number of ports from the niu_type or the platform type.
* Returns the number of ports, or returns zero on failure.
*/
int
{
int nports = 0;
case N2_NIU:
case NEPTUNE_2_10GF:
nports = 2;
break;
case NEPTUNE_4_1GC:
case NEPTUNE_2_10GF_2_1GC:
case NEPTUNE_1_10GF_3_1GC:
nports = 4;
break;
default:
switch (nxgep->platform_type) {
case P_NEPTUNE_NIU:
case P_NEPTUNE_ATLAS_2PORT:
nports = 2;
break;
case P_NEPTUNE_ATLAS_4PORT:
case P_NEPTUNE_MARAMBA_P0:
case P_NEPTUNE_MARAMBA_P1:
case P_NEPTUNE_ALONSO:
nports = 4;
break;
default:
break;
}
break;
}
return (nports);
}
/*
* The following two functions are to support
* PSARC/2007/453 MSI-X interrupt limit override.
*/
static int
{
int nmsi;
extern int ncpus;
case PORT_10G_COPPER:
case PORT_10G_FIBER:
/*
* The maximum MSI-X requested will be 8.
* If the # of CPUs is less than 8, we will reqeust
* # MSI-X based on the # of CPUs.
*/
if (ncpus >= NXGE_MSIX_REQUEST_10G) {
} else {
}
"==>nxge_create_msi_property(10G): exists 0x%x (nmsi %d)",
break;
default:
"==>nxge_create_msi_property(1G): exists 0x%x (nmsi %d)",
break;
}
return (nmsi);
}