nxge_main.c revision 9d5b8bc52bffb83a81625224a3b60481b39a6ba9
8c4f9701439555b41fbfe7848508f53b52166007Janice Chang * CDDL HEADER START
a7a845e4bf22fd1b2a284729ccd95c7370a0438cSteven Hartland * The contents of this file are subject to the terms of the
2654012f83cec5dc15b61dfe3e4a4915f186e7a6Reza Sabdar * Common Development and Distribution License (the "License").
2654012f83cec5dc15b61dfe3e4a4915f186e7a6Reza Sabdar * You may not use this file except in compliance with the License.
2654012f83cec5dc15b61dfe3e4a4915f186e7a6Reza Sabdar * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
2654012f83cec5dc15b61dfe3e4a4915f186e7a6Reza Sabdar * See the License for the specific language governing permissions
2654012f83cec5dc15b61dfe3e4a4915f186e7a6Reza Sabdar * and limitations under the License.
2654012f83cec5dc15b61dfe3e4a4915f186e7a6Reza Sabdar * When distributing Covered Code, include this CDDL HEADER in each
2654012f83cec5dc15b61dfe3e4a4915f186e7a6Reza Sabdar * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
2654012f83cec5dc15b61dfe3e4a4915f186e7a6Reza Sabdar * If applicable, add the following below this CDDL HEADER, with the
2654012f83cec5dc15b61dfe3e4a4915f186e7a6Reza Sabdar * fields enclosed by brackets "[]" replaced with your own identifying
2654012f83cec5dc15b61dfe3e4a4915f186e7a6Reza Sabdar * information: Portions Copyright [yyyy] [name of copyright owner]
2654012f83cec5dc15b61dfe3e4a4915f186e7a6Reza Sabdar * CDDL HEADER END
2654012f83cec5dc15b61dfe3e4a4915f186e7a6Reza Sabdar * Copyright 2008 Sun Microsystems, Inc. All rights reserved.
2654012f83cec5dc15b61dfe3e4a4915f186e7a6Reza Sabdar * Use is subject to license terms.
2654012f83cec5dc15b61dfe3e4a4915f186e7a6Reza Sabdar * SunOs MT STREAMS NIU/Neptune 10Gb Ethernet Device Driver.
2654012f83cec5dc15b61dfe3e4a4915f186e7a6Reza Sabdaruint32_t nxge_use_partition = 0; /* debug partition flag */
2654012f83cec5dc15b61dfe3e4a4915f186e7a6Reza Sabdaruint32_t nxge_dma_obp_props_only = 1; /* use obp published props */
2654012f83cec5dc15b61dfe3e4a4915f186e7a6Reza Sabdaruint32_t nxge_use_rdc_intr = 1; /* debug to assign rdc intr */
2654012f83cec5dc15b61dfe3e4a4915f186e7a6Reza Sabdar * PSARC/2007/453 MSI-X interrupt limit override
2654012f83cec5dc15b61dfe3e4a4915f186e7a6Reza Sabdar * (This PSARC case is limited to MSI-X vectors
2654012f83cec5dc15b61dfe3e4a4915f186e7a6Reza Sabdar * and SPARC platforms only).
876b86efac620aaabc70ad2ed4bfb715ce714875Reza Sabdar * Software workaround for a Neptune (PCI-E)
2654012f83cec5dc15b61dfe3e4a4915f186e7a6Reza Sabdar * hardware interrupt bug which the hardware
876b86efac620aaabc70ad2ed4bfb715ce714875Reza Sabdar * may generate spurious interrupts after the
2654012f83cec5dc15b61dfe3e4a4915f186e7a6Reza Sabdar * device interrupt handler was removed. If this flag
2654012f83cec5dc15b61dfe3e4a4915f186e7a6Reza Sabdar * is enabled, the driver will reset the
2654012f83cec5dc15b61dfe3e4a4915f186e7a6Reza Sabdar * hardware when devices are being detached.
2654012f83cec5dc15b61dfe3e4a4915f186e7a6Reza Sabdar * Software workaround for the hardware
2654012f83cec5dc15b61dfe3e4a4915f186e7a6Reza Sabdar * checksum bugs that affect packet transmission
2654012f83cec5dc15b61dfe3e4a4915f186e7a6Reza Sabdar * and receive:
2654012f83cec5dc15b61dfe3e4a4915f186e7a6Reza Sabdar * Usage of nxge_cksum_offload:
2654012f83cec5dc15b61dfe3e4a4915f186e7a6Reza Sabdar * (1) nxge_cksum_offload = 0 (default):
2654012f83cec5dc15b61dfe3e4a4915f186e7a6Reza Sabdar * - transmits packets:
2654012f83cec5dc15b61dfe3e4a4915f186e7a6Reza Sabdar * TCP: uses the hardware checksum feature.
2654012f83cec5dc15b61dfe3e4a4915f186e7a6Reza Sabdar * UDP: driver will compute the software checksum
2654012f83cec5dc15b61dfe3e4a4915f186e7a6Reza Sabdar * based on the partial checksum computed
2654012f83cec5dc15b61dfe3e4a4915f186e7a6Reza Sabdar * by the IP layer.
2654012f83cec5dc15b61dfe3e4a4915f186e7a6Reza Sabdar * - receives packets
876b86efac620aaabc70ad2ed4bfb715ce714875Reza Sabdar * TCP: marks packets checksum flags based on hardware result.
2654012f83cec5dc15b61dfe3e4a4915f186e7a6Reza Sabdar * UDP: will not mark checksum flags.
2654012f83cec5dc15b61dfe3e4a4915f186e7a6Reza Sabdar * (2) nxge_cksum_offload = 1:
876b86efac620aaabc70ad2ed4bfb715ce714875Reza Sabdar * - transmit packets:
2654012f83cec5dc15b61dfe3e4a4915f186e7a6Reza Sabdar * TCP/UDP: uses the hardware checksum feature.
2654012f83cec5dc15b61dfe3e4a4915f186e7a6Reza Sabdar * - receives packets
2654012f83cec5dc15b61dfe3e4a4915f186e7a6Reza Sabdar * TCP/UDP: marks packet checksum flags based on hardware result.
876b86efac620aaabc70ad2ed4bfb715ce714875Reza Sabdar * (3) nxge_cksum_offload = 2:
2654012f83cec5dc15b61dfe3e4a4915f186e7a6Reza Sabdar * - The driver will not register its checksum capability.
2654012f83cec5dc15b61dfe3e4a4915f186e7a6Reza Sabdar * Checksum for both TCP and UDP will be computed
2654012f83cec5dc15b61dfe3e4a4915f186e7a6Reza Sabdar * by the stack.
2654012f83cec5dc15b61dfe3e4a4915f186e7a6Reza Sabdar * - The software LSO is not allowed in this case.
2654012f83cec5dc15b61dfe3e4a4915f186e7a6Reza Sabdar * (4) nxge_cksum_offload > 2:
876b86efac620aaabc70ad2ed4bfb715ce714875Reza Sabdar * - Will be treated as it is set to 2
2654012f83cec5dc15b61dfe3e4a4915f186e7a6Reza Sabdar * (stack will compute the checksum).
2654012f83cec5dc15b61dfe3e4a4915f186e7a6Reza Sabdar * (5) If the hardware bug is fixed, this workaround
2654012f83cec5dc15b61dfe3e4a4915f186e7a6Reza Sabdar * needs to be updated accordingly to reflect
2654012f83cec5dc15b61dfe3e4a4915f186e7a6Reza Sabdar * the new hardware revision.
2654012f83cec5dc15b61dfe3e4a4915f186e7a6Reza Sabdar * Globals: tunable parameters (/etc/system or adb)
876b86efac620aaabc70ad2ed4bfb715ce714875Reza Sabdaruint32_t nxge_tx_ring_size = NXGE_TX_RING_DEFAULT;
2654012f83cec5dc15b61dfe3e4a4915f186e7a6Reza Sabdarboolean_t nxge_no_msg = B_TRUE; /* control message display */
2654012f83cec5dc15b61dfe3e4a4915f186e7a6Reza Sabdaruint32_t nxge_no_link_notify = 0; /* control DL_NOTIFY */
2654012f83cec5dc15b61dfe3e4a4915f186e7a6Reza Sabdaruint16_t nxge_rcr_timeout = NXGE_RDC_RCR_TIMEOUT;
2654012f83cec5dc15b61dfe3e4a4915f186e7a6Reza Sabdaruint16_t nxge_rcr_threshold = NXGE_RDC_RCR_THRESHOLD;
876b86efac620aaabc70ad2ed4bfb715ce714875Reza Sabdar/* MAX LSO size */
2654012f83cec5dc15b61dfe3e4a4915f186e7a6Reza Sabdar * Debugging flags:
876b86efac620aaabc70ad2ed4bfb715ce714875Reza Sabdar * nxge_no_tx_lb : transmit load balancing
2654012f83cec5dc15b61dfe3e4a4915f186e7a6Reza Sabdar * nxge_tx_lb_policy: 0 - TCP port (default)
2654012f83cec5dc15b61dfe3e4a4915f186e7a6Reza Sabdar * 3 - DEST MAC
876b86efac620aaabc70ad2ed4bfb715ce714875Reza Sabdar * Add tunable to reduce the amount of time spent in the
2654012f83cec5dc15b61dfe3e4a4915f186e7a6Reza Sabdar * ISR doing Rx Processing.
876b86efac620aaabc70ad2ed4bfb715ce714875Reza Sabdar * Tunables to manage the receive buffer blocks.
2654012f83cec5dc15b61dfe3e4a4915f186e7a6Reza Sabdar * nxge_rx_threshold_hi: copy all buffers.
876b86efac620aaabc70ad2ed4bfb715ce714875Reza Sabdar * nxge_rx_bcopy_size_type: receive buffer block size type.
876b86efac620aaabc70ad2ed4bfb715ce714875Reza Sabdar * nxge_rx_threshold_lo: copy only up to tunable block size type.
876b86efac620aaabc70ad2ed4bfb715ce714875Reza Sabdarnxge_rxbuf_threshold_t nxge_rx_threshold_hi = NXGE_RX_COPY_6;
2654012f83cec5dc15b61dfe3e4a4915f186e7a6Reza Sabdarnxge_rxbuf_type_t nxge_rx_buf_size_type = RCR_PKTBUFSZ_0;
876b86efac620aaabc70ad2ed4bfb715ce714875Reza Sabdarnxge_rxbuf_threshold_t nxge_rx_threshold_lo = NXGE_RX_COPY_3;
2654012f83cec5dc15b61dfe3e4a4915f186e7a6Reza Sabdar/* Use kmem_alloc() to allocate data buffers. */
876b86efac620aaabc70ad2ed4bfb715ce714875Reza Sabdar * The hardware sometimes fails to allow enough time for the link partner
2654012f83cec5dc15b61dfe3e4a4915f186e7a6Reza Sabdar * to send an acknowledgement for packets that the hardware sent to it. The
2654012f83cec5dc15b61dfe3e4a4915f186e7a6Reza Sabdar * hardware resends the packets earlier than it should be in those instances.
2654012f83cec5dc15b61dfe3e4a4915f186e7a6Reza Sabdar * This behavior caused some switches to acknowledge the wrong packets
876b86efac620aaabc70ad2ed4bfb715ce714875Reza Sabdar * and it triggered the fatal error.
2654012f83cec5dc15b61dfe3e4a4915f186e7a6Reza Sabdar * This software workaround is to set the replay timer to a value
876b86efac620aaabc70ad2ed4bfb715ce714875Reza Sabdar * suggested by the hardware team.
876b86efac620aaabc70ad2ed4bfb715ce714875Reza Sabdar * PCI config space replay timer register:
2654012f83cec5dc15b61dfe3e4a4915f186e7a6Reza Sabdar * The following replay timeout value is 0xc
2654012f83cec5dc15b61dfe3e4a4915f186e7a6Reza Sabdar * for bit 14:18.
2654012f83cec5dc15b61dfe3e4a4915f186e7a6Reza Sabdar * The transmit serialization sometimes causes
876b86efac620aaabc70ad2ed4bfb715ce714875Reza Sabdar * longer sleep before calling the driver transmit
876b86efac620aaabc70ad2ed4bfb715ce714875Reza Sabdar * function as it sleeps longer than it should.
876b86efac620aaabc70ad2ed4bfb715ce714875Reza Sabdar * The performace group suggests that a time wait tunable
876b86efac620aaabc70ad2ed4bfb715ce714875Reza Sabdar * can be used to set the maximum wait time when needed
876b86efac620aaabc70ad2ed4bfb715ce714875Reza Sabdar * and the default is set to 1 tick.
876b86efac620aaabc70ad2ed4bfb715ce714875Reza Sabdar * Hypervisor N2/NIU services information.
876b86efac620aaabc70ad2ed4bfb715ce714875Reza Sabdar HSVC_REV_1, NULL, HSVC_GROUP_NIU, NIU_MAJOR_VER,
2654012f83cec5dc15b61dfe3e4a4915f186e7a6Reza Sabdar * Function Prototypes
876b86efac620aaabc70ad2ed4bfb715ce714875Reza Sabdarstatic int nxge_attach(dev_info_t *, ddi_attach_cmd_t);
876b86efac620aaabc70ad2ed4bfb715ce714875Reza Sabdarstatic int nxge_detach(dev_info_t *, ddi_detach_cmd_t);
876b86efac620aaabc70ad2ed4bfb715ce714875Reza Sabdarstatic void nxge_remove_hard_properties(p_nxge_t);
876b86efac620aaabc70ad2ed4bfb715ce714875Reza Sabdar * These two functions are required by nxge_hio.c
876b86efac620aaabc70ad2ed4bfb715ce714875Reza Sabdarextern int nxge_m_mmac_add(void *arg, mac_multi_addr_t *maddr);
876b86efac620aaabc70ad2ed4bfb715ce714875Reza Sabdarextern int nxge_m_mmac_remove(void *arg, mac_addr_slot_t slot);
2654012f83cec5dc15b61dfe3e4a4915f186e7a6Reza Sabdarstatic nxge_status_t nxge_setup_system_dma_pages(p_nxge_t);
2654012f83cec5dc15b61dfe3e4a4915f186e7a6Reza Sabdarstatic nxge_status_t nxge_setup_mutexes(p_nxge_t);
876b86efac620aaabc70ad2ed4bfb715ce714875Reza Sabdarstatic nxge_status_t nxge_map_regs(p_nxge_t nxgep);
876b86efac620aaabc70ad2ed4bfb715ce714875Reza Sabdarstatic nxge_status_t nxge_add_intrs(p_nxge_t nxgep);
876b86efac620aaabc70ad2ed4bfb715ce714875Reza Sabdarstatic nxge_status_t nxge_add_soft_intrs(p_nxge_t nxgep);
876b86efac620aaabc70ad2ed4bfb715ce714875Reza Sabdarstatic void nxge_remove_soft_intrs(p_nxge_t nxgep);
876b86efac620aaabc70ad2ed4bfb715ce714875Reza Sabdarstatic nxge_status_t nxge_add_intrs_adv(p_nxge_t nxgep);
876b86efac620aaabc70ad2ed4bfb715ce714875Reza Sabdarstatic nxge_status_t nxge_add_intrs_adv_type(p_nxge_t, uint32_t);
876b86efac620aaabc70ad2ed4bfb715ce714875Reza Sabdarstatic nxge_status_t nxge_add_intrs_adv_type_fix(p_nxge_t, uint32_t);
2654012f83cec5dc15b61dfe3e4a4915f186e7a6Reza Sabdarstatic nxge_status_t nxge_alloc_mem_pool(p_nxge_t);
876b86efac620aaabc70ad2ed4bfb715ce714875Reza Sabdarstatic nxge_status_t nxge_dma_mem_alloc(p_nxge_t, dma_method_t,
876b86efac620aaabc70ad2ed4bfb715ce714875Reza Sabdarstatic void nxge_dma_mem_free(p_nxge_dma_common_t);
876b86efac620aaabc70ad2ed4bfb715ce714875Reza Sabdarstatic void nxge_dma_free_rx_data_buf(p_nxge_dma_common_t);
876b86efac620aaabc70ad2ed4bfb715ce714875Reza Sabdarstatic nxge_status_t nxge_alloc_rx_buf_dma(p_nxge_t, uint16_t,
876b86efac620aaabc70ad2ed4bfb715ce714875Reza Sabdar p_nxge_dma_common_t *, size_t, size_t, uint32_t *);
876b86efac620aaabc70ad2ed4bfb715ce714875Reza Sabdarstatic void nxge_free_rx_buf_dma(p_nxge_t, p_nxge_dma_common_t, uint32_t);
876b86efac620aaabc70ad2ed4bfb715ce714875Reza Sabdarstatic nxge_status_t nxge_alloc_rx_cntl_dma(p_nxge_t, uint16_t,
876b86efac620aaabc70ad2ed4bfb715ce714875Reza Sabdarstatic void nxge_free_rx_cntl_dma(p_nxge_t, p_nxge_dma_common_t);
876b86efac620aaabc70ad2ed4bfb715ce714875Reza Sabdarextern nxge_status_t nxge_alloc_tx_buf_dma(p_nxge_t, uint16_t,
876b86efac620aaabc70ad2ed4bfb715ce714875Reza Sabdar p_nxge_dma_common_t *, size_t, size_t, uint32_t *);
876b86efac620aaabc70ad2ed4bfb715ce714875Reza Sabdarstatic void nxge_free_tx_buf_dma(p_nxge_t, p_nxge_dma_common_t, uint32_t);
876b86efac620aaabc70ad2ed4bfb715ce714875Reza Sabdarextern nxge_status_t nxge_alloc_tx_cntl_dma(p_nxge_t, uint16_t,
876b86efac620aaabc70ad2ed4bfb715ce714875Reza Sabdarstatic void nxge_free_tx_cntl_dma(p_nxge_t, p_nxge_dma_common_t);
2654012f83cec5dc15b61dfe3e4a4915f186e7a6Reza Sabdarextern int nxge_param_set_mac(p_nxge_t, queue_t *, mblk_t *,
2654012f83cec5dc15b61dfe3e4a4915f186e7a6Reza Sabdar * The next declarations are for the GLDv3 interface.
876b86efac620aaabc70ad2ed4bfb715ce714875Reza Sabdarstatic int nxge_m_start(void *);
2654012f83cec5dc15b61dfe3e4a4915f186e7a6Reza Sabdarstatic void nxge_m_stop(void *);
2654012f83cec5dc15b61dfe3e4a4915f186e7a6Reza Sabdarstatic int nxge_m_unicst(void *, const uint8_t *);
876b86efac620aaabc70ad2ed4bfb715ce714875Reza Sabdarstatic int nxge_m_multicst(void *, boolean_t, const uint8_t *);
2654012f83cec5dc15b61dfe3e4a4915f186e7a6Reza Sabdarstatic void nxge_m_ioctl(void *, queue_t *, mblk_t *);
876b86efac620aaabc70ad2ed4bfb715ce714875Reza Sabdarstatic void nxge_m_resources(void *);
876b86efac620aaabc70ad2ed4bfb715ce714875Reza Sabdarstatic nxge_status_t nxge_mac_register(p_nxge_t);
588541fbf64fffe619698198cef04af1900f1f86Reza Sabdarstatic int nxge_altmac_set(p_nxge_t nxgep, uint8_t *mac_addr,
2654012f83cec5dc15b61dfe3e4a4915f186e7a6Reza Sabdarvoid nxge_mmac_kstat_update(p_nxge_t nxgep, mac_addr_slot_t slot,
876b86efac620aaabc70ad2ed4bfb715ce714875Reza Sabdarstatic int nxge_m_mmac_reserve(void *arg, mac_multi_addr_t *maddr);
876b86efac620aaabc70ad2ed4bfb715ce714875Reza Sabdarstatic int nxge_m_mmac_modify(void *arg, mac_multi_addr_t *maddr);
876b86efac620aaabc70ad2ed4bfb715ce714875Reza Sabdarstatic int nxge_m_mmac_get(void *arg, mac_multi_addr_t *maddr);
876b86efac620aaabc70ad2ed4bfb715ce714875Reza Sabdarstatic boolean_t nxge_m_getcapab(void *, mac_capab_t, void *);
876b86efac620aaabc70ad2ed4bfb715ce714875Reza Sabdarstatic int nxge_m_setprop(void *, const char *, mac_prop_id_t,
876b86efac620aaabc70ad2ed4bfb715ce714875Reza Sabdar uint_t, const void *);
876b86efac620aaabc70ad2ed4bfb715ce714875Reza Sabdarstatic int nxge_m_getprop(void *, const char *, mac_prop_id_t,
876b86efac620aaabc70ad2ed4bfb715ce714875Reza Sabdarstatic int nxge_set_priv_prop(nxge_t *, const char *, uint_t,
876b86efac620aaabc70ad2ed4bfb715ce714875Reza Sabdar const void *);
876b86efac620aaabc70ad2ed4bfb715ce714875Reza Sabdarstatic int nxge_get_priv_prop(nxge_t *, const char *, uint_t, uint_t,
876b86efac620aaabc70ad2ed4bfb715ce714875Reza Sabdarstatic int nxge_get_def_val(nxge_t *, mac_prop_id_t, uint_t, void *);
876b86efac620aaabc70ad2ed4bfb715ce714875Reza Sabdarstatic void nxge_set_pci_replay_timeout(nxge_t *);
876b86efac620aaabc70ad2ed4bfb715ce714875Reza Sabdar (sizeof (nxge_priv_props)/sizeof (mac_priv_prop_t))
876b86efac620aaabc70ad2ed4bfb715ce714875Reza Sabdar (MC_RESOURCES | MC_IOCTL | MC_GETCAPAB | MC_SETPROP | MC_GETPROP)
2654012f83cec5dc15b61dfe3e4a4915f186e7a6Reza Sabdar (MC_RESOURCES | MC_IOCTL | MC_GETCAPAB | MC_SETPROP | MC_GETPROP)
NULL,
NULL,
ddi_dma_attr_t *);
#ifndef NIU_PA_WORKAROUND
#if defined(_BIG_ENDIAN)
#ifdef NIU_PA_WORKAROUND
int instance;
switch (cmd) {
case DDI_ATTACH:
case DDI_RESUME:
goto nxge_attach_exit;
case DDI_PM_RESUME:
goto nxge_attach_exit;
goto nxge_attach_exit;
goto nxge_attach_exit;
goto nxge_attach_fail2;
goto nxge_attach_fail3;
goto nxge_attach_fail4;
#if defined(sun4v)
goto nxge_attach_fail4;
goto nxge_attach_fail4;
goto nxge_attach_fail4;
int *regp;
int rv;
goto nxge_attach_fail5;
goto nxge_attach_fail5;
goto nxge_attach_fail5;
goto nxge_attach_fail5;
goto nxge_attach_fail;
goto nxge_attach_fail;
goto nxge_attach_fail;
#if defined(sun4v)
goto nxge_attach_exit;
goto nxge_attach_fail;
goto nxge_attach_fail;
goto nxge_attach_fail;
goto nxge_attach_fail;
/* nxge_link_monitor calls xcvr.check_link recursively */
goto nxge_attach_exit;
goto nxge_attach_fail1;
status));
return (status);
int instance;
goto nxge_detach_exit;
switch (cmd) {
case DDI_DETACH:
case DDI_PM_SUSPEND:
case DDI_SUSPEND:
goto nxge_detach_exit;
return (DDI_FAILURE);
status));
return (status);
#if defined(sun4v)
#if defined(sun4v)
#if NXGE_PROPERTY
#if defined(sun4v)
return (DDI_FAILURE);
return (DDI_SUCCESS);
static nxge_status_t
char *devname;
#ifdef NXGE_DEBUG
char *sysname;
#if !defined(_BIG_ENDIAN)
int *prop_val;
goto nxge_map_regs_fail0;
func_num));
return (NXGE_OK);
goto nxge_map_regs_fail0;
#if !defined(_BIG_ENDIAN)
goto nxge_map_regs_fail1;
goto nxge_map_regs_fail2;
goto nxge_map_regs_fail3;
case N2_NIU:
goto nxge_map_regs_fail1;
goto nxge_map_regs_fail2;
goto nxge_map_regs_fail3;
goto nxge_map_regs_exit;
return (status);
static nxge_status_t
int partition;
ddi_status));
goto nxge_setup_mutexes_exit;
return (status);
int partition;
return (status);
goto nxge_init_fail1;
goto nxge_init_fail2;
goto nxge_init_fail3;
goto nxge_init_fail4;
goto nxge_init_exit;
goto nxge_init_fail5;
goto nxge_init_fail5;
goto nxge_init_fail5;
goto nxge_init_fail5;
goto nxge_init_exit;
return (status);
status));
return (status);
return (NULL);
if (timerid) {
if (!nxge_peu_reset_enable) {
#if defined(__i386)
int i, retry;
regdata = 0;
for (i = 0; i < retry; i++) {
#if defined(__i386)
#if defined(__i386)
int nxge_debug_init = 0;
int instance;
if (nxge_debug_init == 0) {
if (!size)
for (i = 0; i < size; i++) {
*--cp = 0;
return (etherbuf);
#ifdef NXGE_DEBUG
char *dev_ptr;
static nxge_status_t
return (status);
static nxge_status_t
goto nxge_setup_dev_exit;
return (status);
static nxge_status_t
if (iommu_pagesize != 0) {
#ifndef USE_RX_BIG_BUF
DDI_DMA_DONTWAIT, 0,
DDI_DMA_DONTWAIT, 0,
return (status);
static nxge_status_t
return (NXGE_ERROR);
return (NXGE_ERROR);
return (NXGE_OK);
KM_SLEEP);
if (!nxge_port_rbr_size) {
return (status);
int channel)
return (status);
!= NXGE_OK) {
return (status);
return (status);
int channel)
static nxge_status_t
KM_SLEEP);
#if defined(RX_USE_RECLAIM_POST)
size_index = 0;
size_index++;
size_index = 0;
size_index));
} else if (use_kmem_alloc) {
size_index--;
&rx_dmap[i],
goto nxge_alloc_rx_mem_fail1;
dma_channel, i));
*num_chunks = i;
goto nxge_alloc_rx_mem_exit;
return (status);
if (dmap == 0)
for (i = 0; i < num_chunks; i++) {
i, dmap));
static nxge_status_t
size,
rx_dmap);
return (status);
if (dmap == 0)
return (NXGE_ERROR);
return (NXGE_ERROR);
return (NXGE_OK);
int channel)
return (NXGE_ERROR);
*num_chunks = 0;
return (status);
return (status);
return (NXGE_OK);
int channel)
int tdc_max;
KM_SLEEP);
return (NXGE_OK);
KM_SLEEP);
size_index = 0;
size_index++;
size_index--;
goto nxge_alloc_tx_mem_fail1;
*num_chunks = i;
*dmap, i));
goto nxge_alloc_tx_mem_exit;
return (status);
if (dmap == 0)
for (i = 0; i < num_chunks; i++) {
size,
tx_dmap);
return (status);
if (dmap == 0)
static nxge_status_t
switch (contig_alloc_type) {
case B_FALSE:
switch (kmem_alloc_type) {
case B_FALSE:
return (NXGE_ERROR);
NULL,
return (NXGE_ERROR);
case B_TRUE:
return (NXGE_ERROR);
DDI_DMA_DONTWAIT, 0,
return (NXGE_ERROR);
case B_TRUE:
case B_TRUE:
#if defined(__i386)
#if defined(__i386)
return (NXGE_OK);
#if defined(__i386)
return (EIO);
goto nxge_m_start_exit;
#if defined(sun4v)
return (EINVAL);
if (add) {
return (EINVAL);
return (EINVAL);
return (EINVAL);
int err;
int cmd;
switch (cmd) {
case LB_GET_INFO_SIZE:
case LB_GET_INFO:
case LB_GET_MODE:
case LB_SET_MODE:
case NXGE_GET_MII:
case NXGE_PUT_MII:
case NXGE_GET64:
case NXGE_PUT64:
case NXGE_GET_TX_RING_SZ:
case NXGE_GET_TX_DESC:
case NXGE_TX_SIDE_RESET:
case NXGE_RX_SIDE_RESET:
case NXGE_GLOBAL_RESET:
case NXGE_RESET_MAC:
case NXGE_TX_REGS_DUMP:
case NXGE_RX_REGS_DUMP:
case NXGE_INT_REGS_DUMP:
case NXGE_VIR_INT_REGS_DUMP:
case NXGE_PUT_TCAM:
case NXGE_GET_TCAM:
case NXGE_RTRACE:
case NXGE_RDUMP:
case NXGE_INJECT_ERR:
if (need_privilege) {
if (err != 0) {
switch (cmd) {
case LB_GET_MODE:
case LB_SET_MODE:
case LB_GET_INFO_SIZE:
case LB_GET_INFO:
case NXGE_GET_MII:
case NXGE_PUT_MII:
case NXGE_PUT_TCAM:
case NXGE_GET_TCAM:
case NXGE_GET64:
case NXGE_PUT64:
case NXGE_GET_TX_RING_SZ:
case NXGE_GET_TX_DESC:
case NXGE_TX_SIDE_RESET:
case NXGE_RX_SIDE_RESET:
case NXGE_GLOBAL_RESET:
case NXGE_RESET_MAC:
case NXGE_TX_REGS_DUMP:
case NXGE_RX_REGS_DUMP:
case NXGE_INT_REGS_DUMP:
case NXGE_VIR_INT_REGS_DUMP:
goto nxge_m_resources_exit;
goto nxge_m_resources_exit;
if (ring == 0) {
for (i = 0; i < ETHERADDRL; i++) {
if (factory) {
return (EIO);
return (EIO);
!= NPI_SUCCESS)
return (EIO);
int err;
return (ENXIO);
return (ENOSPC);
return (EINVAL);
slot++) {
& MMAC_SLOT_USED))
return (err);
int err;
return (ENXIO);
return (ENOSPC);
return (ENOSPC);
return (EINVAL);
return (EBUSY);
return (EINVAL);
return (err);
int err = 0;
return (ENXIO);
return (EINVAL);
== NPI_SUCCESS) {
|= MMAC_VENDOR_ADDR;
return (err);
int err = 0;
return (EINVAL);
return (ENXIO);
return (EINVAL);
return (err);
return (ENXIO);
return (EINVAL);
static boolean_t
switch (cap) {
case MAC_CAPAB_HCKSUM:
case MAC_CAPAB_POLL:
case MAC_CAPAB_MULTIADDRESS:
case MAC_CAPAB_LSO: {
return (B_FALSE);
#if defined(sun4v)
case MAC_CAPAB_RINGS: {
return (B_FALSE);
case MAC_CAPAB_SHARES: {
return (B_FALSE);
return (B_FALSE);
return (B_TRUE);
static boolean_t
switch (pr_num) {
case MAC_PROP_ADV_1000FDX_CAP:
case MAC_PROP_EN_1000FDX_CAP:
case MAC_PROP_ADV_1000HDX_CAP:
case MAC_PROP_EN_1000HDX_CAP:
case MAC_PROP_ADV_100FDX_CAP:
case MAC_PROP_EN_100FDX_CAP:
case MAC_PROP_ADV_100HDX_CAP:
case MAC_PROP_EN_100HDX_CAP:
case MAC_PROP_ADV_10FDX_CAP:
case MAC_PROP_EN_10FDX_CAP:
case MAC_PROP_ADV_10HDX_CAP:
case MAC_PROP_EN_10HDX_CAP:
case MAC_PROP_AUTONEG:
case MAC_PROP_FLOWCTRL:
return (B_TRUE);
return (B_FALSE);
int err = 0;
return (EBUSY);
switch (pr_num) {
case MAC_PROP_EN_1000FDX_CAP:
goto reprogram;
case MAC_PROP_EN_100FDX_CAP:
goto reprogram;
case MAC_PROP_EN_10FDX_CAP:
goto reprogram;
case MAC_PROP_EN_1000HDX_CAP:
case MAC_PROP_EN_100HDX_CAP:
case MAC_PROP_EN_10HDX_CAP:
case MAC_PROP_ADV_1000FDX_CAP:
case MAC_PROP_ADV_1000HDX_CAP:
case MAC_PROP_ADV_100FDX_CAP:
case MAC_PROP_ADV_100HDX_CAP:
case MAC_PROP_ADV_10FDX_CAP:
case MAC_PROP_ADV_10HDX_CAP:
case MAC_PROP_STATUS:
case MAC_PROP_SPEED:
case MAC_PROP_DUPLEX:
pr_num));
case MAC_PROP_AUTONEG:
goto reprogram;
case MAC_PROP_MTU:
err = 0;
if (err) {
case MAC_PROP_FLOWCTRL:
switch (fl) {
case LINK_FLOWCTRL_NONE:
case LINK_FLOWCTRL_RX:
case LINK_FLOWCTRL_TX:
case LINK_FLOWCTRL_BI:
if (err == 0) {
case MAC_PROP_PRIVATE:
pr_val);
return (err);
int err = 0;
if (pr_valsize == 0)
return (EINVAL);
return (err);
switch (pr_num) {
case MAC_PROP_DUPLEX:
case MAC_PROP_SPEED:
return (EINVAL);
case MAC_PROP_STATUS:
return (EINVAL);
case MAC_PROP_AUTONEG:
case MAC_PROP_FLOWCTRL:
return (EINVAL);
case MAC_PROP_ADV_1000FDX_CAP:
case MAC_PROP_EN_1000FDX_CAP:
case MAC_PROP_ADV_100FDX_CAP:
case MAC_PROP_EN_100FDX_CAP:
case MAC_PROP_ADV_10FDX_CAP:
case MAC_PROP_EN_10FDX_CAP:
case MAC_PROP_EN_1000HDX_CAP:
case MAC_PROP_EN_100HDX_CAP:
case MAC_PROP_EN_10HDX_CAP:
case MAC_PROP_ADV_1000HDX_CAP:
case MAC_PROP_ADV_100HDX_CAP:
case MAC_PROP_ADV_10HDX_CAP:
case MAC_PROP_PRIVATE:
return (err);
const void *pr_val)
int err = 0;
long result;
result));
if (result) {
return (err);
(char *)pr_val,
if (err) {
err = 0;
return (err);
(char *)pr_val,
if (err) {
err = 0;
return (err);
return (err);
return (err);
return (err);
return (err);
return (err);
return (err);
return (err);
return (err);
return (err);
return (err);
return (err);
return (err);
return (err);
return (err);
return (err);
return (err);
return (err);
return (err);
return (err);
return (err);
return (err);
return (EINVAL);
if (is_default)
return (ENOTSUP);
err = 0;
goto done;
if (is_default)
return (ENOTSUP);
err = 0;
goto done;
if (is_default)
return (ENOTSUP);
case PORT_1G_COPPER:
case PORT_1G_FIBER:
case PORT_10G_COPPER:
case PORT_10G_FIBER:
case PORT_10G_SERDES:
case PORT_1G_SERDES:
case PORT_1G_TN1010:
case PORT_10G_TN1010:
case PORT_1G_RGMII_FIBER:
case PORT_HSP_MODE:
err = 0;
goto done;
if (is_default)
return (ENOTSUP);
err = 0;
goto done;
if (is_default)
err = 0;
goto done;
err = 0;
if (is_default) {
goto done;
goto done;
err = 0;
if (is_default) {
goto done;
goto done;
if (is_default) {
err = 0;
goto done;
goto done;
if (is_default) {
err = 0;
goto done;
goto done;
if (is_default) {
err = 0;
goto done;
goto done;
if (is_default) {
err = 0;
goto done;
goto done;
if (is_default) {
err = 0;
goto done;
goto done;
if (is_default) {
err = 0;
goto done;
goto done;
if (is_default) {
err = 0;
goto done;
goto done;
if (is_default) {
err = 0;
goto done;
goto done;
if (is_default) {
err = 0;
goto done;
err = 0;
goto done;
err = 0;
if (is_default ||
goto done;
goto done;
err = 0;
if (is_default ||
goto done;
goto done;
done:
if (err == 0) {
return (err);
_init(void)
int status;
if (status != 0) {
goto _init_exit;
if (status != 0) {
goto _init_exit;
return (status);
_fini(void)
int status;
if (nxge_mblks_pending)
return (EBUSY);
status));
goto _fini_exit;
return (status);
int status;
return (status);
static nxge_status_t
int intr_types;
int type = 0;
} else if (nxge_msi_enable) {
!= DDI_SUCCESS) {
ddi_status));
switch (nxge_msi_enable) {
type));
type));
type));
type));
type));
type));
type));
status));
return (status);
return (status);
return (status);
static nxge_status_t
ddi_status));
return (status);
static nxge_status_t
int intr_type;
intr_type));
switch (intr_type) {
return (NXGE_ERROR);
static nxge_status_t
int behavior;
int inum = 0;
ddi_status));
ddi_status));
for (y = 0; y < nactual; y++) {
nrequired = 0;
case N2_NIU:
for (y = 0; y < nactual; y++) {
return (status);
!= DDI_SUCCESS) {
(void) ddi_intr_remove_handler(
for (y = 0; y < nactual; y++) {
return (status);
static nxge_status_t
int behavior;
int inum = 0;
ddi_status));
ddi_status));
for (y = 0; y < nactual; y++) {
nrequired = 0;
case N2_NIU:
for (y = 0; y < nactual; y++) {
return (status);
!= DDI_SUCCESS) {
(void) ddi_intr_remove_handler(
for (y = 0; y < nactual; y++) {
return (status);
int i, inum;
inum,
int status;
static nxge_status_t
int status;
return (NXGE_ERROR);
if (status != 0) {
return (NXGE_ERROR);
return (NXGE_OK);
switch (blk_id) {
case MAC_BLK_ID:
case TXMAC_BLK_ID:
case RXMAC_BLK_ID:
case MIF_BLK_ID:
case IPP_BLK_ID:
case TXC_BLK_ID:
case TXDMA_BLK_ID:
case RXDMA_BLK_ID:
case ZCP_BLK_ID:
case ESPC_BLK_ID:
case FFLP_BLK_ID:
case PHY_BLK_ID:
case ETHER_SERDES_BLK_ID:
case PCIE_SERDES_BLK_ID:
case VIR_BLK_ID:
hw_p,
p_dip));
hw_p,
p_dip));
nxge_hw_list));
return (NXGE_OK);
hw_p,
p_cfgp =
hw_p,
hw_p,
hw_p,
nxge_hw_list));
int nports = 0;
case N2_NIU:
case NEPTUNE_2_10GF:
case NEPTUNE_4_1GC:
case NEPTUNE_2_10GF_2_1GC:
case NEPTUNE_1_10GF_3_1GC:
case NEPTUNE_2_10GF_2_1GRF:
case P_NEPTUNE_NIU:
case P_NEPTUNE_ATLAS_2PORT:
case P_NEPTUNE_ATLAS_4PORT:
case P_NEPTUNE_MARAMBA_P0:
case P_NEPTUNE_MARAMBA_P1:
case P_NEPTUNE_ALONSO:
return (nports);
int nmsi;
extern int ncpus;
case PORT_10G_COPPER:
case PORT_10G_FIBER:
case PORT_10G_TN1010:
return (nmsi);
void *pr_val)
int err = 0;
switch (pr_num) {
case MAC_PROP_AUTONEG:
case MAC_PROP_FLOWCTRL:
return (EINVAL);
case MAC_PROP_ADV_1000FDX_CAP:
case MAC_PROP_EN_1000FDX_CAP:
case MAC_PROP_ADV_100FDX_CAP:
case MAC_PROP_EN_100FDX_CAP:
return (err);
NXGE_GLU_RESET | \
for (i = 0; i < NXGE_MAX_PORTS; i++) {
#ifdef NXGE_DEBUG
if (fnxgep) {
for (j = 0; j < NXGE_WAIT_QUITE_RETRY; j++) {
rvalue));
rvalue));
if (!nxge_set_replay_timer) {
dev_regs));
value);