nxge_main.c revision 2e59129a8dc96d4082395c338ad696e29471d4e0
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1d4b38e0077763e7c9b20768eacb841957e787bcrsmaeda * Copyright 2007 Sun Microsystems, Inc. All rights reserved.
1d4b38e0077763e7c9b20768eacb841957e787bcrsmaeda * Use is subject to license terms.
1d4b38e0077763e7c9b20768eacb841957e787bcrsmaeda#pragma ident "%Z%%M% %I% %E% SMI"
1d4b38e0077763e7c9b20768eacb841957e787bcrsmaeda * SunOs MT STREAMS NIU/Neptune 10Gb Ethernet Device Driver.
1d4b38e0077763e7c9b20768eacb841957e787bcrsmaedauint32_t nxge_use_partition = 0; /* debug partition flag */
1d4b38e0077763e7c9b20768eacb841957e787bcrsmaedauint32_t nxge_dma_obp_props_only = 1; /* use obp published props */
1d4b38e0077763e7c9b20768eacb841957e787bcrsmaedauint32_t nxge_use_rdc_intr = 1; /* debug to assign rdc intr */
1d4b38e0077763e7c9b20768eacb841957e787bcrsmaeda * until MSIX supported, assume msi, use 2 for msix
1d4b38e0077763e7c9b20768eacb841957e787bcrsmaedauint32_t nxge_msi_enable = 1; /* debug: turn msi off */
1d4b38e0077763e7c9b20768eacb841957e787bcrsmaeda * Globals: tunable parameters (/etc/system or adb)
1d4b38e0077763e7c9b20768eacb841957e787bcrsmaedaboolean_t nxge_no_msg = B_TRUE; /* control message display */
1d4b38e0077763e7c9b20768eacb841957e787bcrsmaedauint32_t nxge_no_link_notify = 0; /* control DL_NOTIFY */
1d4b38e0077763e7c9b20768eacb841957e787bcrsmaedauint16_t nxge_rcr_threshold = NXGE_RDC_RCR_THRESHOLD;
1d4b38e0077763e7c9b20768eacb841957e787bcrsmaeda * Debugging flags:
1d4b38e0077763e7c9b20768eacb841957e787bcrsmaeda * nxge_no_tx_lb : transmit load balancing
1d4b38e0077763e7c9b20768eacb841957e787bcrsmaeda * nxge_tx_lb_policy: 0 - TCP port (default)
1d4b38e0077763e7c9b20768eacb841957e787bcrsmaeda * 3 - DEST MAC
1d4b38e0077763e7c9b20768eacb841957e787bcrsmaeda * Add tunable to reduce the amount of time spent in the
1d4b38e0077763e7c9b20768eacb841957e787bcrsmaeda * ISR doing Rx Processing.
1d4b38e0077763e7c9b20768eacb841957e787bcrsmaeda * Tunables to manage the receive buffer blocks.
1d4b38e0077763e7c9b20768eacb841957e787bcrsmaeda * nxge_rx_threshold_hi: copy all buffers.
1d4b38e0077763e7c9b20768eacb841957e787bcrsmaeda * nxge_rx_bcopy_size_type: receive buffer block size type.
1d4b38e0077763e7c9b20768eacb841957e787bcrsmaeda * nxge_rx_threshold_lo: copy only up to tunable block size type.
1d4b38e0077763e7c9b20768eacb841957e787bcrsmaedanxge_rxbuf_threshold_t nxge_rx_threshold_hi = NXGE_RX_COPY_6;
1d4b38e0077763e7c9b20768eacb841957e787bcrsmaedanxge_rxbuf_type_t nxge_rx_buf_size_type = RCR_PKTBUFSZ_0;
1d4b38e0077763e7c9b20768eacb841957e787bcrsmaedanxge_rxbuf_threshold_t nxge_rx_threshold_lo = NXGE_RX_COPY_3;
1d4b38e0077763e7c9b20768eacb841957e787bcrsmaeda#if defined(sun4v)
1d4b38e0077763e7c9b20768eacb841957e787bcrsmaeda * Hypervisor N2/NIU services information.
1d4b38e0077763e7c9b20768eacb841957e787bcrsmaeda * Function Prototypes
1d4b38e0077763e7c9b20768eacb841957e787bcrsmaedastatic int nxge_attach(dev_info_t *, ddi_attach_cmd_t);
1d4b38e0077763e7c9b20768eacb841957e787bcrsmaedastatic int nxge_detach(dev_info_t *, ddi_detach_cmd_t);
1d4b38e0077763e7c9b20768eacb841957e787bcrsmaedastatic nxge_status_t nxge_setup_system_dma_pages(p_nxge_t);
1d4b38e0077763e7c9b20768eacb841957e787bcrsmaedastatic nxge_status_t nxge_add_soft_intrs(p_nxge_t nxgep);
1d4b38e0077763e7c9b20768eacb841957e787bcrsmaedastatic nxge_status_t nxge_add_intrs_adv(p_nxge_t nxgep);
1d4b38e0077763e7c9b20768eacb841957e787bcrsmaedastatic nxge_status_t nxge_add_intrs_adv_type(p_nxge_t, uint32_t);
1d4b38e0077763e7c9b20768eacb841957e787bcrsmaedastatic nxge_status_t nxge_add_intrs_adv_type_fix(p_nxge_t, uint32_t);
1d4b38e0077763e7c9b20768eacb841957e787bcrsmaedastatic nxge_status_t nxge_alloc_rx_mem_pool(p_nxge_t);
1d4b38e0077763e7c9b20768eacb841957e787bcrsmaedastatic nxge_status_t nxge_alloc_tx_mem_pool(p_nxge_t);
1d4b38e0077763e7c9b20768eacb841957e787bcrsmaedastatic nxge_status_t nxge_dma_mem_alloc(p_nxge_t, dma_method_t,
1d4b38e0077763e7c9b20768eacb841957e787bcrsmaedastatic nxge_status_t nxge_alloc_rx_buf_dma(p_nxge_t, uint16_t,
1d4b38e0077763e7c9b20768eacb841957e787bcrsmaedastatic void nxge_free_rx_buf_dma(p_nxge_t, p_nxge_dma_common_t, uint32_t);
1d4b38e0077763e7c9b20768eacb841957e787bcrsmaedastatic nxge_status_t nxge_alloc_rx_cntl_dma(p_nxge_t, uint16_t,
1d4b38e0077763e7c9b20768eacb841957e787bcrsmaedastatic void nxge_free_rx_cntl_dma(p_nxge_t, p_nxge_dma_common_t);
1d4b38e0077763e7c9b20768eacb841957e787bcrsmaedastatic nxge_status_t nxge_alloc_tx_buf_dma(p_nxge_t, uint16_t,
1d4b38e0077763e7c9b20768eacb841957e787bcrsmaedastatic void nxge_free_tx_buf_dma(p_nxge_t, p_nxge_dma_common_t, uint32_t);
1d4b38e0077763e7c9b20768eacb841957e787bcrsmaedastatic nxge_status_t nxge_alloc_tx_cntl_dma(p_nxge_t, uint16_t,
1d4b38e0077763e7c9b20768eacb841957e787bcrsmaedastatic void nxge_free_tx_cntl_dma(p_nxge_t, p_nxge_dma_common_t);
1d4b38e0077763e7c9b20768eacb841957e787bcrsmaeda * The next declarations are for the GLDv3 interface.
1d4b38e0077763e7c9b20768eacb841957e787bcrsmaedastatic int nxge_m_start(void *);
1d4b38e0077763e7c9b20768eacb841957e787bcrsmaedastatic void nxge_m_stop(void *);
1d4b38e0077763e7c9b20768eacb841957e787bcrsmaedastatic int nxge_m_multicst(void *, boolean_t, const uint8_t *);
1d4b38e0077763e7c9b20768eacb841957e787bcrsmaedastatic void nxge_m_ioctl(void *, queue_t *, mblk_t *);
1d4b38e0077763e7c9b20768eacb841957e787bcrsmaedastatic void nxge_m_resources(void *);
1d4b38e0077763e7c9b20768eacb841957e787bcrsmaedastatic int nxge_altmac_set(p_nxge_t nxgep, uint8_t *mac_addr,
1d4b38e0077763e7c9b20768eacb841957e787bcrsmaedastatic void nxge_mmac_kstat_update(p_nxge_t nxgep, mac_addr_slot_t slot,
1d4b38e0077763e7c9b20768eacb841957e787bcrsmaedastatic int nxge_m_mmac_add(void *arg, mac_multi_addr_t *maddr);
1d4b38e0077763e7c9b20768eacb841957e787bcrsmaedastatic int nxge_m_mmac_reserve(void *arg, mac_multi_addr_t *maddr);
1d4b38e0077763e7c9b20768eacb841957e787bcrsmaedastatic int nxge_m_mmac_remove(void *arg, mac_addr_slot_t slot);
1d4b38e0077763e7c9b20768eacb841957e787bcrsmaedastatic int nxge_m_mmac_modify(void *arg, mac_multi_addr_t *maddr);
1d4b38e0077763e7c9b20768eacb841957e787bcrsmaedastatic int nxge_m_mmac_get(void *arg, mac_multi_addr_t *maddr);
1d4b38e0077763e7c9b20768eacb841957e787bcrsmaeda#define NXGE_M_CALLBACK_FLAGS (MC_RESOURCES | MC_IOCTL | MC_GETCAPAB)
1d4b38e0077763e7c9b20768eacb841957e787bcrsmaedastatic boolean_t nxge_m_getcapab(void *, mac_capab_t, void *);
1d4b38e0077763e7c9b20768eacb841957e787bcrsmaeda * These global variables control the message
1d4b38e0077763e7c9b20768eacb841957e787bcrsmaedaout_dbgmsg_t nxge_dbgmsg_out = DBG_CONSOLE | STR_LOG;
1d4b38e0077763e7c9b20768eacb841957e787bcrsmaeda * This list contains the instance structures for the Neptune
1d4b38e0077763e7c9b20768eacb841957e787bcrsmaeda * devices present in the system. The lock exists to guarantee
1d4b38e0077763e7c9b20768eacb841957e787bcrsmaeda * mutually exclusive access to the list.
1d4b38e0077763e7c9b20768eacb841957e787bcrsmaedaextern nxge_status_t nxge_ldgv_init(p_nxge_t, int *, int *);
1d4b38e0077763e7c9b20768eacb841957e787bcrsmaedaextern nxge_status_t nxge_ldgv_init_n2(p_nxge_t, int *, int *);
1d4b38e0077763e7c9b20768eacb841957e787bcrsmaedaextern npi_status_t npi_mac_altaddr_disable(npi_handle_t, uint8_t, uint8_t);
1d4b38e0077763e7c9b20768eacb841957e787bcrsmaeda * Count used to maintain the number of buffers being used
1d4b38e0077763e7c9b20768eacb841957e787bcrsmaeda * by Neptune instances and loaned up to the upper layers.
1d4b38e0077763e7c9b20768eacb841957e787bcrsmaeda * Device register access attributes for PIO.
1d4b38e0077763e7c9b20768eacb841957e787bcrsmaedastatic ddi_device_acc_attr_t nxge_dev_reg_acc_attr = {
1d4b38e0077763e7c9b20768eacb841957e787bcrsmaeda * Device descriptor access attributes for DMA.
1d4b38e0077763e7c9b20768eacb841957e787bcrsmaedastatic ddi_device_acc_attr_t nxge_dev_desc_dma_acc_attr = {
1d4b38e0077763e7c9b20768eacb841957e787bcrsmaeda * Device buffer access attributes for DMA.
1d4b38e0077763e7c9b20768eacb841957e787bcrsmaedastatic ddi_device_acc_attr_t nxge_dev_buf_dma_acc_attr = {
1d4b38e0077763e7c9b20768eacb841957e787bcrsmaeda 0, /* low address */
1d4b38e0077763e7c9b20768eacb841957e787bcrsmaeda 0 /* attribute flags */
1d4b38e0077763e7c9b20768eacb841957e787bcrsmaeda 0, /* low address */
1d4b38e0077763e7c9b20768eacb841957e787bcrsmaeda 0 /* attribute flags */
1d4b38e0077763e7c9b20768eacb841957e787bcrsmaeda 0, /* low address */
1d4b38e0077763e7c9b20768eacb841957e787bcrsmaeda (uint_t)0xfc00fc, /* dlim_burstsizes for 32 and 64 bit xfers */
1d4b38e0077763e7c9b20768eacb841957e787bcrsmaeda * dma chunk sizes.
1d4b38e0077763e7c9b20768eacb841957e787bcrsmaeda * Try to allocate the largest possible size
1d4b38e0077763e7c9b20768eacb841957e787bcrsmaeda * so that fewer number of dma chunks would be managed
1d4b38e0077763e7c9b20768eacb841957e787bcrsmaedasize_t alloc_sizes [] = {0x1000, 0x2000, 0x4000, 0x8000,
1d4b38e0077763e7c9b20768eacb841957e787bcrsmaeda * Translate "dev_t" to a pointer to the associated "dev_info_t".
1d4b38e0077763e7c9b20768eacb841957e787bcrsmaeda NXGE_DEBUG_MSG((nxgep, DDI_CTL, "==> nxge_attach"));
1d4b38e0077763e7c9b20768eacb841957e787bcrsmaeda * Get the device instance since we'll need to setup
1d4b38e0077763e7c9b20768eacb841957e787bcrsmaeda * or retrieve a soft state for this instance.
1d4b38e0077763e7c9b20768eacb841957e787bcrsmaeda NXGE_DEBUG_MSG((nxgep, DDI_CTL, "doing DDI_ATTACH"));
1d4b38e0077763e7c9b20768eacb841957e787bcrsmaeda NXGE_DEBUG_MSG((nxgep, DDI_CTL, "doing DDI_RESUME"));
1d4b38e0077763e7c9b20768eacb841957e787bcrsmaeda nxgep = (p_nxge_t)ddi_get_soft_state(nxge_list, instance);
1d4b38e0077763e7c9b20768eacb841957e787bcrsmaeda NXGE_DEBUG_MSG((nxgep, DDI_CTL, "doing DDI_PM_RESUME"));
1d4b38e0077763e7c9b20768eacb841957e787bcrsmaeda nxgep = (p_nxge_t)ddi_get_soft_state(nxge_list, instance);
1d4b38e0077763e7c9b20768eacb841957e787bcrsmaeda if (ddi_soft_state_zalloc(nxge_list, instance) == DDI_FAILURE) {
1d4b38e0077763e7c9b20768eacb841957e787bcrsmaeda nxge_fm_init(nxgep, &nxge_dev_reg_acc_attr, &nxge_dev_desc_dma_acc_attr,
1d4b38e0077763e7c9b20768eacb841957e787bcrsmaeda NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, "nxge_map_regs failed"));
1d4b38e0077763e7c9b20768eacb841957e787bcrsmaeda "nxge_init_common_dev failed"));
1d4b38e0077763e7c9b20768eacb841957e787bcrsmaeda " function %d. Only functions 0 and 1 are "
1d4b38e0077763e7c9b20768eacb841957e787bcrsmaeda * Neptune has 4 ports, the first 2 ports use XMAC (10G MAC)
1d4b38e0077763e7c9b20768eacb841957e787bcrsmaeda * internally, the rest 2 ports use BMAC (1G "Big" MAC).
1d4b38e0077763e7c9b20768eacb841957e787bcrsmaeda * The two types of MACs have different characterizations.
1d4b38e0077763e7c9b20768eacb841957e787bcrsmaeda * Setup the Ndd parameters for the this instance.
1d4b38e0077763e7c9b20768eacb841957e787bcrsmaeda * Setup Register Tracing Buffer.
1d4b38e0077763e7c9b20768eacb841957e787bcrsmaeda /* init stats ptr */
1d4b38e0077763e7c9b20768eacb841957e787bcrsmaeda * read the vpd info from the eeprom into local data
1d4b38e0077763e7c9b20768eacb841957e787bcrsmaeda * structure and check for the VPD info validity
1d4b38e0077763e7c9b20768eacb841957e787bcrsmaeda NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, "nxge_attach: "
1d4b38e0077763e7c9b20768eacb841957e787bcrsmaeda " Couldn't determine card type"
1d4b38e0077763e7c9b20768eacb841957e787bcrsmaeda " .... exit "));
1d4b38e0077763e7c9b20768eacb841957e787bcrsmaeda NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, "get_hw create failed"));
1d4b38e0077763e7c9b20768eacb841957e787bcrsmaeda * Setup the Kstats for the driver.
1d4b38e0077763e7c9b20768eacb841957e787bcrsmaeda NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, "set dma page failed"));
1d4b38e0077763e7c9b20768eacb841957e787bcrsmaeda#if defined(sun4v)
1d4b38e0077763e7c9b20768eacb841957e787bcrsmaeda bcopy(&niu_hsvc, &nxgep->niu_hsvc, sizeof (hsvc_info_t));
1d4b38e0077763e7c9b20768eacb841957e787bcrsmaeda "nxge_attach: "
1d4b38e0077763e7c9b20768eacb841957e787bcrsmaeda "%s: cannot negotiate "
1d4b38e0077763e7c9b20768eacb841957e787bcrsmaeda "hypervisor services "
1d4b38e0077763e7c9b20768eacb841957e787bcrsmaeda "revision %d "
1d4b38e0077763e7c9b20768eacb841957e787bcrsmaeda "group: 0x%lx "
1d4b38e0077763e7c9b20768eacb841957e787bcrsmaeda "major: 0x%lx minor: 0x%lx "
1d4b38e0077763e7c9b20768eacb841957e787bcrsmaeda "errno: %d",
1d4b38e0077763e7c9b20768eacb841957e787bcrsmaeda "NIU Hypervisor service enabled"));
1d4b38e0077763e7c9b20768eacb841957e787bcrsmaeda NXGE_DEBUG_MSG((nxgep, DDI_CTL, "set mutex failed"));
1d4b38e0077763e7c9b20768eacb841957e787bcrsmaeda NXGE_DEBUG_MSG((nxgep, DDI_CTL, "add_intr failed"));
1d4b38e0077763e7c9b20768eacb841957e787bcrsmaeda NXGE_DEBUG_MSG((nxgep, NXGE_ERR_CTL, "add_soft_intr failed"));
1d4b38e0077763e7c9b20768eacb841957e787bcrsmaeda * Enable interrupts.
1d4b38e0077763e7c9b20768eacb841957e787bcrsmaeda if ((status = nxge_mac_register(nxgep)) != NXGE_OK) {
1d4b38e0077763e7c9b20768eacb841957e787bcrsmaeda NXGE_DEBUG_MSG((nxgep, DDI_CTL, "registered to mac (instance %d)",
1d4b38e0077763e7c9b20768eacb841957e787bcrsmaeda (void) nxge_link_monitor(nxgep, LINK_MONITOR_START);
1d4b38e0077763e7c9b20768eacb841957e787bcrsmaeda * Tear down the ndd parameters setup.
1d4b38e0077763e7c9b20768eacb841957e787bcrsmaeda * Tear down the kstat setup.
1d4b38e0077763e7c9b20768eacb841957e787bcrsmaeda * Unmap the register setup.
1d4b38e0077763e7c9b20768eacb841957e787bcrsmaeda NXGE_DEBUG_MSG((nxgep, DDI_CTL, "<== nxge_attach status = 0x%08x",
1d4b38e0077763e7c9b20768eacb841957e787bcrsmaeda NXGE_DEBUG_MSG((nxgep, DDI_CTL, "==> nxge_detach"));
1d4b38e0077763e7c9b20768eacb841957e787bcrsmaeda NXGE_DEBUG_MSG((nxgep, DDI_CTL, "doing DDI_DETACH"));
1d4b38e0077763e7c9b20768eacb841957e787bcrsmaeda NXGE_DEBUG_MSG((nxgep, DDI_CTL, "doing DDI_PM_SUSPEND"));
1d4b38e0077763e7c9b20768eacb841957e787bcrsmaeda NXGE_DEBUG_MSG((nxgep, DDI_CTL, "doing DDI_SUSPEND"));
1d4b38e0077763e7c9b20768eacb841957e787bcrsmaeda * Stop the xcvr polling.
1d4b38e0077763e7c9b20768eacb841957e787bcrsmaeda if (nxgep->mach && (status = mac_unregister(nxgep->mach)) != 0) {
1d4b38e0077763e7c9b20768eacb841957e787bcrsmaeda "<== nxge_detach (mac_unregister) status = 0x%08X", status));
1d4b38e0077763e7c9b20768eacb841957e787bcrsmaeda NXGE_DEBUG_MSG((nxgep, DDI_CTL, "<== nxge_detach status = 0x%08X",
1d4b38e0077763e7c9b20768eacb841957e787bcrsmaeda NXGE_DEBUG_MSG((nxgep, DDI_CTL, "==> nxge_unattach"));
1d4b38e0077763e7c9b20768eacb841957e787bcrsmaeda#if defined(sun4v)
1d4b38e0077763e7c9b20768eacb841957e787bcrsmaeda if (nxgep->niu_type == N2_NIU && nxgep->niu_hsvc_available == B_TRUE) {
1d4b38e0077763e7c9b20768eacb841957e787bcrsmaeda * Stop any further interrupts.
1d4b38e0077763e7c9b20768eacb841957e787bcrsmaeda /* remove soft interrups */
1d4b38e0077763e7c9b20768eacb841957e787bcrsmaeda * Stop the device and free resources.
1d4b38e0077763e7c9b20768eacb841957e787bcrsmaeda * Tear down the ndd parameters setup.
1d4b38e0077763e7c9b20768eacb841957e787bcrsmaeda * Tear down the kstat setup.
1d4b38e0077763e7c9b20768eacb841957e787bcrsmaeda * Destroy all mutexes.
1d4b38e0077763e7c9b20768eacb841957e787bcrsmaeda * Remove the list of ndd parameters which
1d4b38e0077763e7c9b20768eacb841957e787bcrsmaeda * were setup during attach.
1d4b38e0077763e7c9b20768eacb841957e787bcrsmaeda " nxge_unattach: remove all properties"));
1d4b38e0077763e7c9b20768eacb841957e787bcrsmaeda * Unmap the register setup.
1d4b38e0077763e7c9b20768eacb841957e787bcrsmaeda NXGE_DEBUG_MSG((NULL, DDI_CTL, "<== nxge_unattach"));
1d4b38e0077763e7c9b20768eacb841957e787bcrsmaeda NXGE_DEBUG_MSG((nxgep, DDI_CTL, "==> nxge_map_regs"));
1d4b38e0077763e7c9b20768eacb841957e787bcrsmaeda dev_regs = KMEM_ZALLOC(sizeof (dev_regs_t), KM_SLEEP);
1d4b38e0077763e7c9b20768eacb841957e787bcrsmaeda /* get function number */
1d4b38e0077763e7c9b20768eacb841957e787bcrsmaeda "nxge_map_regs: N2/NIU function number %d",
1d4b38e0077763e7c9b20768eacb841957e787bcrsmaeda if (ddi_prop_lookup_int_array(DDI_DEV_T_ANY, nxgep->dip,
1d4b38e0077763e7c9b20768eacb841957e787bcrsmaeda "Reg property not found"));
1d4b38e0077763e7c9b20768eacb841957e787bcrsmaeda "Reg property found: fun # %d",
1d4b38e0077763e7c9b20768eacb841957e787bcrsmaeda "ddi_map_regs, nxge bus config regs failed"));
1d4b38e0077763e7c9b20768eacb841957e787bcrsmaeda "nxge_map_reg: PCI config addr 0x%0llx "
1d4b38e0077763e7c9b20768eacb841957e787bcrsmaeda * workaround for bit swapping bug in HW
1d4b38e0077763e7c9b20768eacb841957e787bcrsmaeda * which ends up in no-snoop = yes
1d4b38e0077763e7c9b20768eacb841957e787bcrsmaeda * resulting, in DMA not synched properly
1d4b38e0077763e7c9b20768eacb841957e787bcrsmaeda /* workarounds for x86 systems */
1d4b38e0077763e7c9b20768eacb841957e787bcrsmaeda pci_config_put16(dev_regs->nxge_pciregh, pci_offset,
1d4b38e0077763e7c9b20768eacb841957e787bcrsmaeda /* set up the device mapped register */
1d4b38e0077763e7c9b20768eacb841957e787bcrsmaeda "ddi_map_regs for Neptune global reg failed"));
1d4b38e0077763e7c9b20768eacb841957e787bcrsmaeda /* set up the msi/msi-x mapped register */
1d4b38e0077763e7c9b20768eacb841957e787bcrsmaeda "ddi_map_regs for msi reg failed"));
1d4b38e0077763e7c9b20768eacb841957e787bcrsmaeda /* set up the vio region mapped register */
1d4b38e0077763e7c9b20768eacb841957e787bcrsmaeda "ddi_map_regs for nxge vio reg failed"));
1d4b38e0077763e7c9b20768eacb841957e787bcrsmaeda NPI_PCI_ACC_HANDLE_SET(nxgep, dev_regs->nxge_pciregh);
1d4b38e0077763e7c9b20768eacb841957e787bcrsmaeda NPI_MSI_ACC_HANDLE_SET(nxgep, dev_regs->nxge_msix_regh);
1d4b38e0077763e7c9b20768eacb841957e787bcrsmaeda NPI_ADD_HANDLE_SET(nxgep, (npi_reg_ptr_t)dev_regs->nxge_regp);
1d4b38e0077763e7c9b20768eacb841957e787bcrsmaeda NPI_VREG_ACC_HANDLE_SET(nxgep, dev_regs->nxge_vir_regh);
1d4b38e0077763e7c9b20768eacb841957e787bcrsmaeda NXGE_DEBUG_MSG((nxgep, DDI_CTL, "ddi_map_regs, NIU"));
1d4b38e0077763e7c9b20768eacb841957e787bcrsmaeda * Set up the device mapped register (FWARC 2006/556)
1d4b38e0077763e7c9b20768eacb841957e787bcrsmaeda * (changed back to 1: reg starts at 1!)
goto nxge_map_regs_fail1;
goto nxge_map_regs_fail2;
goto nxge_map_regs_fail3;
goto nxge_map_regs_exit;
return (status);
static nxge_status_t
int partition;
goto nxge_setup_mutexes_exit;
if (nxge_mdio_lock_init == 0) {
if (nxge_mii_lock_init == 0) {
return (status);
int partition;
return (status);
goto nxge_init_fail1;
goto nxge_init_fail2;
goto nxge_init_fail3;
goto nxge_init_fail4;
goto nxge_init_fail5;
goto nxge_init_fail5;
goto nxge_init_fail5;
goto nxge_init_fail5;
goto nxge_init_exit;
return (status);
status));
return (status);
return (NULL);
if (timerid) {
int i, retry;
regdata = 0;
for (i = 0; i < retry; i++) {
int nxge_debug_init = 0;
int instance;
if (nxge_debug_init == 0) {
if (!size)
for (i = 0; i < size; i++) {
*--cp = 0;
return (etherbuf);
#ifdef NXGE_DEBUG
char *dev_ptr;
static nxge_status_t
return (status);
static nxge_status_t
goto nxge_setup_dev_exit;
return (status);
static nxge_status_t
if (iommu_pagesize != 0) {
#ifndef USE_RX_BIG_BUF
DDI_DMA_DONTWAIT, 0,
DDI_DMA_DONTWAIT, 0,
return (status);
static nxge_status_t
return (NXGE_ERROR);
return (NXGE_ERROR);
return (NXGE_OK);
static nxge_status_t
KM_SLEEP);
if (!nxge_port_rbr_size) {
for (i = 0; i < ndmas; i++) {
num_chunks[i] = 0;
st_rdc++;
if (i < ndmas) {
goto nxge_alloc_rx_mem_fail1;
for (j = 0; j < ndmas; j++) {
st_rdc++;
if (j < ndmas) {
goto nxge_alloc_rx_mem_fail2;
num_chunks[i]);
return (status);
for (i = 0; i < ndmas; i++) {
for (i = 0; i < ndmas; i++) {
for (i = 0; i < ndmas; i++) {
static nxge_status_t
KM_SLEEP);
#if defined(RX_USE_RECLAIM_POST)
size_index = 0;
size_index++;
size_index--;
goto nxge_alloc_rx_mem_fail1;
dma_channel, i));
*num_chunks = i;
goto nxge_alloc_rx_mem_exit;
return (status);
for (i = 0; i < num_chunks; i++) {
i, dmap));
static nxge_status_t
size,
rx_dmap);
return (status);
static nxge_status_t
KM_SLEEP);
for (i = 0; i < ndmas; i++) {
num_chunks[i] = 0;
st_tdc++;
if (i < ndmas) {
for (j = 0; j < ndmas; j++) {
st_tdc++;
if (j < ndmas) {
num_chunks[i]);
return (status);
static nxge_status_t
KM_SLEEP);
size_index = 0;
size_index++;
size_index--;
goto nxge_alloc_tx_mem_fail1;
*num_chunks = i;
*dmap, i));
goto nxge_alloc_tx_mem_exit;
return (status);
for (i = 0; i < num_chunks; i++) {
static nxge_status_t
size,
tx_dmap);
return (status);
for (i = 0; i < ndmas; i++) {
for (i = 0; i < ndmas; i++) {
for (i = 0; i < ndmas; i++) {
static nxge_status_t
switch (contig_alloc_type) {
case B_FALSE:
return (NXGE_ERROR);
return (NXGE_ERROR);
case B_TRUE:
case B_TRUE:
return (NXGE_OK);
return (EIO);
goto nxge_m_start_exit;
return (EINVAL);
if (add) {
return (EINVAL);
return (EINVAL);
return (EINVAL);
int err;
int cmd;
switch (cmd) {
case LB_GET_INFO_SIZE:
case LB_GET_INFO:
case LB_GET_MODE:
case LB_SET_MODE:
case ND_GET:
case ND_SET:
case NXGE_GET_MII:
case NXGE_PUT_MII:
case NXGE_GET64:
case NXGE_PUT64:
case NXGE_GET_TX_RING_SZ:
case NXGE_GET_TX_DESC:
case NXGE_TX_SIDE_RESET:
case NXGE_RX_SIDE_RESET:
case NXGE_GLOBAL_RESET:
case NXGE_RESET_MAC:
case NXGE_TX_REGS_DUMP:
case NXGE_RX_REGS_DUMP:
case NXGE_INT_REGS_DUMP:
case NXGE_VIR_INT_REGS_DUMP:
case NXGE_PUT_TCAM:
case NXGE_GET_TCAM:
case NXGE_RTRACE:
case NXGE_RDUMP:
case NXGE_INJECT_ERR:
if (need_privilege) {
if (err != 0) {
switch (cmd) {
case ND_GET:
case ND_SET:
case LB_GET_MODE:
case LB_SET_MODE:
case LB_GET_INFO_SIZE:
case LB_GET_INFO:
case NXGE_GET_MII:
case NXGE_PUT_MII:
case NXGE_PUT_TCAM:
case NXGE_GET_TCAM:
case NXGE_GET64:
case NXGE_PUT64:
case NXGE_GET_TX_RING_SZ:
case NXGE_GET_TX_DESC:
case NXGE_TX_SIDE_RESET:
case NXGE_RX_SIDE_RESET:
case NXGE_GLOBAL_RESET:
case NXGE_RESET_MAC:
case NXGE_TX_REGS_DUMP:
case NXGE_RX_REGS_DUMP:
case NXGE_INT_REGS_DUMP:
case NXGE_VIR_INT_REGS_DUMP:
goto nxge_m_resources_exit;
for (i = 0; i < ndmas; i++) {
rcr_p[i],
for (i = 0; i < ETHERADDRL; i++) {
if (factory) {
return (EIO);
return (EIO);
!= NPI_SUCCESS)
return (EIO);
int err;
return (ENXIO);
return (ENOSPC);
return (EINVAL);
slot++) {
& MMAC_SLOT_USED))
return (err);
int err;
return (ENXIO);
return (ENOSPC);
return (ENOSPC);
return (EINVAL);
return (EBUSY);
return (EINVAL);
return (err);
int err = 0;
return (ENXIO);
return (EINVAL);
== NPI_SUCCESS) {
|= MMAC_VENDOR_ADDR;
return (err);
int err = 0;
return (EINVAL);
return (ENXIO);
return (EINVAL);
return (err);
return (ENXIO);
return (EINVAL);
static boolean_t
switch (cap) {
case MAC_CAPAB_HCKSUM:
case MAC_CAPAB_POLL:
case MAC_CAPAB_MULTIADDRESS:
return (B_FALSE);
return (B_TRUE);
NULL,
_init(void)
int status;
if (status != 0) {
goto _init_exit;
if (status != 0) {
goto _init_exit;
return (status);
_fini(void)
int status;
if (nxge_mblks_pending)
return (EBUSY);
status));
goto _fini_exit;
return (status);
int status;
return (status);
static nxge_status_t
int intr_types;
int type = 0;
} else if (nxge_msi_enable) {
!= DDI_SUCCESS) {
ddi_status));
switch (nxge_msi_enable) {
type));
type));
type));
type));
type));
type));
type));
status));
return (status);
return (status);
return (status);
static nxge_status_t
ddi_status));
return (status);
static nxge_status_t
int intr_type;
intr_type));
switch (intr_type) {
return (NXGE_ERROR);
static nxge_status_t
int behavior;
int inum = 0;
ddi_status));
ddi_status));
for (y = 0; y < nactual; y++) {
nrequired = 0;
case N2_NIU:
for (y = 0; y < nactual; y++) {
return (status);
!= DDI_SUCCESS) {
(void) ddi_intr_remove_handler(
for (y = 0; y < nactual; y++) {
return (status);
static nxge_status_t
int behavior;
int inum = 0;
ddi_status));
ddi_status));
for (y = 0; y < nactual; y++) {
nrequired = 0;
case N2_NIU:
for (y = 0; y < nactual; y++) {
return (status);
!= DDI_SUCCESS) {
(void) ddi_intr_remove_handler(
for (y = 0; y < nactual; y++) {
return (status);
int i, inum;
inum,
int status;
static nxge_status_t
int status;
return (NXGE_ERROR);
if (status != 0) {
return (NXGE_ERROR);
return (NXGE_OK);
switch (blk_id) {
case MAC_BLK_ID:
case TXMAC_BLK_ID:
case RXMAC_BLK_ID:
case MIF_BLK_ID:
case IPP_BLK_ID:
case TXC_BLK_ID:
case TXDMA_BLK_ID:
case RXDMA_BLK_ID:
case ZCP_BLK_ID:
case ESPC_BLK_ID:
case FFLP_BLK_ID:
case PHY_BLK_ID:
case ETHER_SERDES_BLK_ID:
case PCIE_SERDES_BLK_ID:
case VIR_BLK_ID:
hw_p,
p_dip));
hw_p,
p_dip));
nxge_hw_list));
return (NXGE_OK);
hw_p,
hw_p,
hw_p,
hw_p,
nxge_hw_list));
int nports = 0;
case N2_NIU:
case NEPTUNE_2_10GF:
case NEPTUNE_4_1GC:
case NEPTUNE_2_10GF_2_1GC:
case NEPTUNE_1_10GF_3_1GC:
case P_NEPTUNE_NIU:
case P_NEPTUNE_ATLAS_2PORT:
case P_NEPTUNE_ATLAS_4PORT:
case P_NEPTUNE_MARAMBA_P0:
case P_NEPTUNE_MARAMBA_P1:
return (nports);