nxge_mac.c revision 4df55fde49134f9735f84011f23a767c75e393c7
/*
* CDDL HEADER START
*
* The contents of this file are subject to the terms of the
* Common Development and Distribution License (the "License").
* You may not use this file except in compliance with the License.
*
* You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
* See the License for the specific language governing permissions
* and limitations under the License.
*
* When distributing Covered Code, include this CDDL HEADER in each
* file and include the License file at usr/src/OPENSOLARIS.LICENSE.
* If applicable, add the following below this CDDL HEADER, with the
* fields enclosed by brackets "[]" replaced with your own identifying
* information: Portions Copyright [yyyy] [name of copyright owner]
*
* CDDL HEADER END
*/
/*
* Copyright 2009 Sun Microsystems, Inc. All rights reserved.
* Use is subject to license terms.
*/
#define LM_WAIT_MULTIPLIER 8
#define SERDES_RDY_WT_INTERVAL 50
#define MAX_SERDES_RDY_RETRIES 10
#define TN1010_SPEED_1G 1
#define TN1010_SPEED_10G 0
#define TN1010_AN_IN_PROG 0 /* Auto negotiation in progress */
#define TN1010_AN_COMPLETE 1
#define TN1010_AN_RSVD 2
#define TN1010_AN_FAILED 3
extern uint32_t nxge_no_link_notify;
extern boolean_t nxge_no_msg;
extern uint32_t nxge_lb_dbg;
extern uint32_t nxge_jumbo_mtu;
typedef enum {
/*
* Ethernet broadcast address definition.
*/
static ether_addr_st etherbroadcastaddr =
{{0xff, 0xff, 0xff, 0xff, 0xff, 0xff}};
/*
* Ethernet zero address definition.
*/
static ether_addr_st etherzeroaddr =
{{0x0, 0x0, 0x0, 0x0, 0x0, 0x0}};
/*
* Supported chip types
*/
static uint32_t nxge_supported_cl45_ids[] = {
};
static uint32_t nxge_supported_cl22_ids[] = {
};
#define NUM_CLAUSE_45_IDS (sizeof (nxge_supported_cl45_ids) / \
sizeof (uint32_t))
#define NUM_CLAUSE_22_IDS (sizeof (nxge_supported_cl22_ids) / \
sizeof (uint32_t))
/*
* static functions
*/
static void nxge_bcm5464_link_led_off(p_nxge_t);
#ifdef NXGE_DEBUG
static void nxge_mii_dump(p_nxge_t);
#endif
/*
* xcvr tables for supported transceivers
*/
/*
* nxge_n2_10G_table is for 10G fiber or serdes on N2-NIU systems.
* The Teranetics TN1010 based copper XAUI card can also be used
* on N2-NIU systems in 10G mode, but it uses its own table
* nxge_n2_10G_tn1010_table below.
*/
static nxge_xcvr_table_t nxge_n2_10G_table = {
};
/*
* For the Teranetics TN1010 based copper XAUI card
*/
static nxge_xcvr_table_t nxge_n2_10G_tn1010_table = {
nxge_n2_serdes_init, /* Handle both 1G and 10G */
nxge_tn1010_xcvr_init, /* Handle both 1G and 10G */
nxge_check_tn1010_link, /* Will figure out speed */
};
static nxge_xcvr_table_t nxge_n2_1G_table = {
};
static nxge_xcvr_table_t nxge_n2_1G_tn1010_table = {
nxge_1G_fiber_link_intr_stop, /* TN1010 is a Cu PHY, but it uses */
nxge_1G_fiber_link_intr_start, /* PCS for 1G, so call fiber func */
};
static nxge_xcvr_table_t nxge_10G_tn1010_table = {
};
static nxge_xcvr_table_t nxge_1G_tn1010_table = {
};
static nxge_xcvr_table_t nxge_10G_fiber_table = {
};
static nxge_xcvr_table_t nxge_1G_copper_table = {
NULL,
};
/* This table is for Neptune portmode == PORT_1G_SERDES cases */
static nxge_xcvr_table_t nxge_1G_fiber_table = {
};
static nxge_xcvr_table_t nxge_10G_copper_table = {
NULL,
NULL,
NULL,
NULL,
};
/*
* NXGE_PORT_TN1010 is defined as,
* NXGE_PORT_SPD_NONE | (NXGE_PHY_TN1010 << NXGE_PHY_SHIFT)
* = 0 | 5 << 16 = 0x50000
*
* So NEPTUNE_2_TN1010 =
* (NXGE_PORT_TN1010 |
* (NXGE_PORT_TN1010 << 4) |
* (NXGE_PORT_NONE << 8) |
* (NXGE_PORT_NONE << 12)),
* = 0x50000 | (0x50000 << 4)
* = 0x550000
*
* This function partitions nxgep->nxge_hw_p->niu_type (which may have
* value NEPTUNE_2_TN1010) and checks if a port has type = NXGE_PORT_TN1010
* = 0x50000
*/
{
& NXGE_PHY_MASK) == NXGE_PORT_TN1010) {
return (B_TRUE);
} else {
return (B_FALSE);
}
}
/*
* Figure out nxgep->mac.portmode from nxge.conf, OBP's device properties,
* serial EEPROM or VPD if possible. Note that not all systems could get
* the portmode information by calling this function. For example, the
* Maramba system figures out the portmode information by calling function
* nxge_setup_xcvr_table.
*/
{
char *phy_type;
char *prop_val;
/* For Opus NEM, skip xcvr checking if 10G Serdes link is up */
return (status);
}
/*
* First check for hot swappable phy property.
*/
"hot-swappable-phy") == 1) {
"hot-swappable-phy") == 1) {
}
/*
* MDIO polling support for Monza RTM card, Goa NEM card
*/
if (portn > 1) {
return (NXGE_ERROR);
}
/*
* If this is the 2nd NIU port, then check 2 addresses
* to take care of the Goa NEM card. Port 1 can have addr 17
* (in the eval board) or 20 (in the P0 board).
*/
if (portn == 1) {
if (nxge_is_phy_present(nxgep,
BCM_PHY_ID_MASK)) {
goto found_phy;
}
}
if (nxge_is_phy_present(nxgep,
goto found_phy;
}
/* Check Serdes link to detect Opus NEM */
XPCS_REG_STATUS, &val);
"HSP 10G Serdes FOUND!!"));
}
goto check_phy_done;
"found for hot swappable phy"));
return (status);
}
/* Get phy-type property (May have been set by nxge.conf) */
"found conf file: phy-type %s", prop_val));
"found: 10G Serdes"));
/*
* Before OBP supports new phy-type property
* value "xgc", the 10G copper XAUI may carry
* "xgf" instead of "xgc". If the OBP is
* upgraded to a newer version which supports
* "xgc", then the TN1010 related code in this
* "xgf" case will not be used anymore.
*/
if (nxge_is_tn1010_phy(nxgep)) {
!= NXGE_OK) {
return (status);
}
} else { /* For Fiber XAUI */
"10G Fiber Xcvr"));
}
return (status);
}
"phy-type", prop_val);
"Got phy type [0x%x] from conf file",
return (NXGE_OK);
}
/* Get phy-type property from OBP */
/*
* Before OBP supports new phy-type property
* value "xgc", the 10G copper XAUI may carry
* "xgf" instead of "xgc". If the OBP is
* upgraded to a newer version which supports
* "xgc", then the TN1010 related code in this
* "xgf" case will not be used anymore.
*/
if (nxge_is_tn1010_phy(nxgep)) {
if ((status =
!= NXGE_OK) {
return (status);
}
"TN1010 Xcvr"));
} else { /* For Fiber XAUI */
= XPCS_XCVR;
"10G Fiber Xcvr"));
}
"1G Copper Xcvr"));
"1G Fiber Xcvr"));
return (status);
"OBP: 10G Serdes"));
"OBP: 1G Serdes"));
} else {
"Unknown phy-type: %s", prop_val));
return (NXGE_ERROR);
}
(void) ddi_prop_update_string(DDI_DEV_T_NONE,
"Got phy type [0x%x] from OBP",
return (status);
} else {
"Exiting...phy-type property not found"));
return (NXGE_ERROR);
}
}
return (NXGE_OK);
}
goto read_seeprom;
}
"Reading phy type from expansion ROM"));
/*
* Try to read the phy type from the vpd data read off the
* expansion ROM.
*/
"nxge_get_xcvr_type: Failed to set TN1010 param"));
goto read_seeprom;
}
} else {
"nxge_get_xcvr_type: Unknown phy type [%c%c%c] in EEPROM",
goto read_seeprom;
}
return (status);
/*
* read the phy type from the SEEPROM - NCR registers
*/
"Failed to get phy type"));
}
return (status);
}
/* Set up the PHY specific values. */
{
uint32_t pma_pmd_id = 0;
portn));
case N2_NIU:
case PORT_1G_FIBER:
case PORT_1G_SERDES:
"Serdes"));
break;
case PORT_10G_FIBER:
case PORT_10G_SERDES:
}
"Serdes"));
break;
case PORT_1G_TN1010:
"TN1010 Copper Xcvr in 1G"));
break;
case PORT_10G_TN1010:
"TN1010 Copper Xcvr in 10G"));
break;
case PORT_HSP_MODE:
"Swappable Xcvr (not present)"));
break;
default:
"<== nxge_setup_xcvr_table: "
"Unable to determine NIU portmode"));
return (NXGE_ERROR);
}
break;
default:
/*
* Would be the case for platforms like Maramba
* in which the phy type could not be got from conf
* file, OBP, VPD or Serial PROM.
*/
if (!NXGE_IS_VALID_NEPTUNE_TYPE(nxgep)) {
"<== nxge_setup_xcvr_table:"
" Invalid Neptune type [0x%x]",
return (NXGE_ERROR);
}
switch (port_type) {
case NXGE_PORT_1G_COPPER:
break;
case NXGE_PORT_10G_COPPER:
break;
case NXGE_PORT_1G_FIBRE:
break;
case NXGE_PORT_10G_FIBRE:
break;
case NXGE_PORT_1G_SERDES:
break;
case NXGE_PORT_10G_SERDES:
break;
/* Ports 2 and 3 of Alonso or ARTM */
case NXGE_PORT_1G_RGMII_FIBER:
break;
case NXGE_PORT_TN1010:
/*
* If this port uses the TN1010 copper
* PHY, then its speed is not known yet
* because nxge_scan_ports_phy could only
* figure out the vendor of the PHY but
* not its speed. nxge_set_tn1010_param
* will read the PHY speed and set
* portmode accordingly.
*/
!= NXGE_OK) {
"nxge_set_tn1010_param failed"));
return (status);
}
break;
default:
"<== nxge_setup_xcvr_table: "
"Unknown port-type: 0x%x", port_type));
return (NXGE_ERROR);
}
}
/*
* Above switch has figured out nxge->mac.portmode, now set
* nxgep->xcvr (the table) and nxgep->xcvr_addr according
* to portmode.
*/
case PORT_1G_COPPER:
case PORT_1G_RGMII_FIBER:
/*
* For Altas 4-1G copper, Xcvr port numbers are
* swapped with ethernet port number. This is
* designed for better signal integrity in
* routing. This is also the case for the
* on-board Neptune copper ports on the Maramba
* platform.
*/
switch (nxgep->platform_type) {
case P_NEPTUNE_ATLAS_4PORT:
case P_NEPTUNE_MARAMBA_P0:
case P_NEPTUNE_MARAMBA_P1:
switch (portn) {
case 0:
break;
case 1:
break;
case 2:
break;
case 3:
break;
default:
return (NXGE_ERROR);
}
break;
default:
break;
}
"Copper" : "RGMII Fiber"));
break;
case PORT_10G_COPPER:
break;
case PORT_1G_TN1010:
"1G TN1010 copper Xcvr"));
break;
case PORT_10G_TN1010:
"10G TN1010 copper Xcvr"));
break;
case PORT_1G_FIBER:
case PORT_1G_SERDES:
"Fiber" : "Serdes"));
break;
case PORT_10G_FIBER:
case PORT_10G_SERDES:
"nxgep->nxge_hw_p->xcvr_addr[portn] = [%d] "
"nxgep->xcvr_addr = [%d]",
}
switch (nxgep->platform_type) {
case P_NEPTUNE_MARAMBA_P0:
case P_NEPTUNE_MARAMBA_P1:
/*
* Switch off LED for corresponding copper
* port
*/
break;
default:
break;
}
"Fiber" : "Serdes"));
break;
case PORT_HSP_MODE:
"Swappable Xcvr (not present)"));
break;
default:
"Unknown port-type: 0x%x", port_type));
return (NXGE_ERROR);
}
}
"nxge_setup_xcvr_table: "
"Chip ID MARVELL [0x%x] for 10G xcvr", chip_id));
switch (chip_id) {
case BCM8704_CHIP_ID:
"nxge_setup_xcvr_table: "
"Chip ID 8704 [0x%x] for 10G xcvr",
chip_id));
break;
case BCM8706_CHIP_ID:
"nxge_setup_xcvr_table: "
"Chip ID 8706 [0x%x] for 10G xcvr",
chip_id));
break;
default:
"nxge_setup_xcvr_table: "
"Unknown Chip ID [0x%x] for 10G xcvr",
chip_id));
break;
}
}
}
/*
* Get the actual device ID value returned by MDIO read.
*/
} else {
} else {
}
}
}
return (status);
}
/* Initialize the entire MAC and physical layer */
{
/* Initialize XIF to configure a network mode */
goto fail;
}
goto fail;
}
/* Initialize TX and RX MACs */
/*
* Always perform XIF init first, before TX and RX MAC init
*/
goto fail;
goto fail;
goto fail;
goto fail;
goto fail;
goto fail;
}
/* Initialize MAC control configuration */
goto fail;
}
/* The Neptune Serdes needs to be reinitialized again */
if ((NXGE_IS_VALID_NEPTUNE_TYPE(nxgep)) &&
"nxge_mac_init: reinit Neptune 1G Serdes "));
goto fail;
}
}
return (NXGE_OK);
fail:
"nxge_mac_init: failed to initialize MAC port<%d>", portn));
return (status);
}
/* Initialize the Ethernet Link */
{
#ifdef NXGE_DEBUG
#endif
/* For Opus NEM, Serdes always needs to be initialized */
/*
* Workaround to get link up in both NIU ports. Some portmodes require
* that the xcvr be initialized twice, the first time before calling
* nxge_serdes_init.
*/
(portmode != PORT_10G_TN1010) &&
(portmode != PORT_1G_TN1010) &&
(portmode != PORT_1G_SERDES)) {
goto fail;
}
}
NXGE_DELAY(200000);
/* Initialize internal serdes */
goto fail;
NXGE_DELAY(200000);
goto fail;
return (NXGE_OK);
fail:
"failed to initialize Ethernet link on port<%d>", portn));
return (status);
}
/* Initialize the XIF sub-block within the MAC */
{
if ((NXGE_IS_VALID_NEPTUNE_TYPE(nxgep)) &&
"nxge_xcvr_init: set ATCA mode"));
}
if (portt == PORT_TYPE_XMAC) {
/* Setup XIF Configuration for XMAC */
if ((portmode == PORT_10G_FIBER) ||
(portmode == PORT_10G_COPPER) ||
(portmode == PORT_10G_TN1010) ||
(portmode == PORT_HSP_MODE) ||
(portmode == PORT_10G_SERDES))
/* Bypass PCS so that RGMII will be used */
if (portmode == PORT_1G_COPPER) {
}
/* Set MAC Internal Loopback if necessary */
if ((portmode == PORT_10G_FIBER) ||
(portmode == PORT_10G_TN1010) ||
(portmode == PORT_1G_TN1010) ||
(portmode == PORT_HSP_MODE) ||
(portmode == PORT_10G_SERDES)) {
/* Assume LED same for 1G and 10G */
} else {
}
}
if (rs != NPI_SUCCESS)
goto fail;
/* Set Port Mode */
if ((portmode == PORT_10G_FIBER) ||
(portmode == PORT_10G_COPPER) ||
(portmode == PORT_10G_TN1010) ||
(portmode == PORT_HSP_MODE) ||
(portmode == PORT_10G_SERDES)) {
MAC_XGMII_MODE, rs);
if (rs != NPI_SUCCESS)
goto fail;
goto fail;
} else {
goto fail;
}
} else if ((portmode == PORT_1G_FIBER) ||
(portmode == PORT_1G_COPPER) ||
(portmode == PORT_1G_SERDES) ||
(portmode == PORT_1G_TN1010) ||
(portmode == PORT_1G_RGMII_FIBER)) {
"nxge_xif_init: Port[%d] Mode[%d] Speed[%d]",
MAC_GMII_MODE, rs);
} else {
MAC_MII_MODE, rs);
}
if (rs != NPI_SUCCESS)
goto fail;
} else {
"nxge_xif_init: Unknown port mode (%d)"
goto fail;
}
/* Enable ATCA mode */
} else if (portt == PORT_TYPE_BMAC) {
/* Setup XIF Configuration for BMAC */
if ((portmode == PORT_1G_COPPER) ||
(portmode == PORT_1G_RGMII_FIBER)) {
}
if (rs != NPI_SUCCESS)
goto fail;
}
return (NXGE_OK);
fail:
"nxge_xif_init: Failed to initialize XIF port<%d>", portn));
return (NXGE_ERROR | rs);
}
/*
* Initialize the PCS sub-block in the MAC. Note that PCS does not
* support loopback like XPCS.
*/
{
uint8_t i;
if (portmode == PORT_1G_FIBER ||
portmode == PORT_1G_TN1010 ||
portmode == PORT_1G_SERDES) {
if (portmode == PORT_1G_TN1010) {
/* Reset PCS multiple time in PORT_1G_TN1010 mode */
for (i = 0; i < 6; i ++) {
!= NPI_SUCCESS) {
goto fail;
}
}
} else {
!= NPI_SUCCESS)
goto fail;
}
/* Initialize port's PCS */
"==> nxge_pcs_init: (1G) port<%d> write config 0x%llx",
if (portmode == PORT_1G_TN1010) {
/*
* Must disable PCS auto-negotiation when the the driver
* is driving the TN1010 based XAUI card Otherwise the
* autonegotiation between the PCS and the TN1010 PCS
*/
}
} else if (portmode == PORT_10G_FIBER ||
portmode == PORT_10G_COPPER ||
portmode == PORT_10G_TN1010 ||
portmode == PORT_HSP_MODE ||
portmode == PORT_10G_SERDES) {
/* Use internal XPCS, bypass 1G PCS */
val &= ~XMAC_XIF_XPCS_BYPASS;
goto fail;
/* Set XPCS Internal Loopback if necessary */
goto fail;
val |= XPCS_CTRL1_LOOPBK;
else
val &= ~XPCS_CTRL1_LOOPBK;
goto fail;
/* Clear descw errors */
XPCS_REG_DESCWERR_COUNTER, 0)) != NPI_SUCCESS)
goto fail;
/* Clear symbol errors */
goto fail;
goto fail;
} else if ((portmode == PORT_1G_COPPER) ||
(portmode == PORT_1G_RGMII_FIBER)) {
"==> nxge_pcs_init: (1G) copper port<%d>", portn));
if (portn < 4) {
}
goto fail;
} else {
goto fail;
}
pass:
return (NXGE_OK);
fail:
"nxge_pcs_init: Failed to initialize PCS port<%d>", portn));
return (NXGE_ERROR | rs);
}
/*
* Initialize the MAC CTRL sub-block within the MAC
* Only the receive-pause-cap is supported.
*/
{
portn));
if (portt == PORT_TYPE_XMAC) {
/* Reading the current XMAC Config Register for XMAC */
/*
* Setup XMAC Configuration for XMAC
* XMAC only supports receive-pause
*/
/*
* If adv_cap_asmpause is 1 and adv_cap_pause
* is 0, enable receive pause.
*/
} else {
/*
* If adv_cap_asmpause is 1 and adv_cap_pause
* is 1, disable receive pause. Send pause is
* not supported.
*/
}
} else {
"==> nxge_mac_ctrl_init: port<%d>: pause",
portn));
"==> nxge_mac_ctrl_init: port<%d>: "
"enable pause", portn));
/*
* If adv_cap_asmpause is 0 and adv_cap_pause
* is 1, enable receive pause.
*/
} else {
/*
* If adv_cap_asmpause is 0 and adv_cap_pause
* is 0, disable receive pause. Send pause is
* not supported
*/
"==> nxge_mac_ctrl_init: port<%d>: "
"disable pause", portn));
}
}
} else if (portt == PORT_TYPE_BMAC) {
/* Reading the current MAC CTRL Config Register for BMAC */
/* Setup MAC CTRL Configuration for BMAC */
/*
* If adv_cap_asmpause is 1 and adv_cap_pause
* is 1, disable receive pause. Send pause
* is not supported
*/
} else {
/*
* If adv_cap_asmpause is 1 and adv_cap_pause
* is 0, enable receive pause and disable
* send pause.
*/
}
} else {
/*
* If adv_cap_asmpause is 0 and adv_cap_pause
* is 1, enable receive pause. Send pause is
* not supported.
*/
} else {
/*
* If adv_cap_asmpause is 0 and adv_cap_pause
* is 0, pause capability is not available in
* either direction.
*/
val &= (~MAC_CTRL_CFG_SEND_PAUSE_EN &
}
}
}
portn));
return (NXGE_OK);
}
/* Initialize the Internal Serdes */
{
#ifdef NXGE_DEBUG
#endif
#ifdef NXGE_DEBUG
"==> nxge_serdes_init port<%d>", portn));
#endif
goto fail;
}
portn));
return (NXGE_OK);
fail:
"nxge_serdes_init: Failed to initialize serdes for port<%d>",
portn));
return (status);
}
/* Initialize the TI Hedwig Internal Serdes (N2-NIU only) */
static nxge_status_t
{
int chan;
#ifdef NXGE_DEBUG
#endif
portn));
"==> nxge_n2_serdes_init port<%d>: KT-NIU", portn));
return (nxge_n2_kt_serdes_init(nxgep));
}
/*
* If the nxge driver has been plumbed without a link, then it will
* detect a link up when a cable connecting to an anto-negotiation
* partner is plugged into the port. Because the TN1010 PHY supports
* both 1G and 10G speeds, the driver must re-configure the
* is called at the post-link-up reconfiguration time. Here it calls
* nxge_set_tn1010_param to set portmode before re-initializing
* the serdes.
*/
goto fail;
}
}
/* 0x0E01 */
/* 0x9101 */
/* 0x0008 */
/* Set loopback mode if necessary */
goto fail;
}
/* Initialize PLL for 10G */
goto fail;
goto fail;
#ifdef NXGE_DEBUG
"==> nxge_n2_serdes_init port<%d>: PLL cfg.l 0x%x (0x%x)",
"==> nxge_n2_serdes_init port<%d>: PLL sts.l 0x%x (0x%x)",
#endif
/* 0x0E21 */
/* 0x9121 */
if (portn == 0) {
/* 0x8 */
}
/* Initialize PLL for 1G */
goto fail;
goto fail;
#ifdef NXGE_DEBUG
"==> nxge_n2_serdes_init port<%d>: PLL cfg.l 0x%x (0x%x)",
"==> nxge_n2_serdes_init port<%d>: PLL sts.l 0x%x (0x%x)",
#endif
/* Set loopback mode if necessary */
"==> nxge_n2_serdes_init port<%d>: loopback 0x%x",
goto fail;
}
}
} else {
goto fail;
}
/* MIF_REG_WR(handle, MIF_MASK_REG, ~mask); */
NXGE_DELAY(20);
/* init TX channels */
goto fail;
goto fail;
"==> nxge_n2_serdes_init port<%d>: chan %d tx_cfg_l 0x%x",
"==> nxge_n2_serdes_init port<%d>: chan %d tx_cfg_h 0x%x",
}
/* init RX channels */
goto fail;
goto fail;
"==> nxge_n2_serdes_init port<%d>: chan %d rx_cfg_l 0x%x",
"==> nxge_n2_serdes_init port<%d>: chan %d rx_cfg_h 0x%x",
}
portn));
return (NXGE_OK);
fail:
"nxge_n2_serdes_init: Failed to initialize N2 serdes for port<%d>",
portn));
return (status);
}
/* Initialize the TI Hedwig Internal Serdes (N2-KT-NIU only) */
static nxge_status_t
{
int chan;
#ifdef NXGE_DEBUG
#endif
"==> nxge_n2_kt_serdes_init port<%d>", portn));
/*
* The following setting assumes the reference clock frquency
* is 156.25 MHz.
*/
/*
* If the nxge driver has been plumbed without a link, then it will
* detect a link up when a cable connecting to an anto-negotiation
* partner is plugged into the port. Because the TN1010 PHY supports
* both 1G and 10G speeds, the driver must re-configure the
* is called at the post-link-up reconfiguration time. Here it calls
* nxge_set_tn1010_param to set portmode before re-initializing
* the serdes.
*/
goto fail;
}
}
/* 0x1e21 */
"==> nxge_n2_kt_serdes_init port<%d> tx_cfg_l 0x%x",
/* channel 0: enable syn. master */
/* 0x40 */
"==> nxge_n2_kt_serdes_init port<%d> tx_cfg_h 0x%x",
/* 0x4821 */
"==> nxge_n2_kt_serdes_init port<%d> rx_cfg_l 0x%x",
/* 0x0008 */
"==> nxge_n2_kt_serdes_init port<%d> rx_cfg_h 0x%x",
/* Set loopback mode if necessary */
"==> nxge_n2_kt_serdes_init port<%d>: "
}
/* 0xa1: Initialize PLL for 10G */
"==> nxge_n2_kt_serdes_init port<%d> pll_cfg_l 0x%x",
goto fail;
"==> nxge_n2_kt_serdes_init port<%d> pll_cfg_l 0x%x",
#ifdef NXGE_DEBUG
"==> nxge_n2_kt_serdes_init port<%d>: "
"PLL cfg.l 0x%x (0x%x)",
"==> nxge_n2_kt_serdes_init port<%d>: (0x%x)",
#endif
/* 0x1e41 */
"==> nxge_n2_kt_serdes_init port<%d> tx_cfg_l 0x%x",
/* channel 0: enable syn. master */
"==> nxge_n2_kt_serdes_init port<%d> tx_cfg_h 0x%x",
/* 0x4841 */
"==> nxge_n2_kt_serdes_init port<%d> rx_cfg_l 0x%x",
/* 0x0008 */
"==> nxge_n2_kt_serdes_init port<%d> tx_cfg_h 0x%x",
/* 0xa1: Initialize PLL for 1G */
"==> nxge_n2_kt_serdes_init port<%d> pll_cfg_l 0x%x",
!= NXGE_OK)
goto fail;
#ifdef NXGE_DEBUG
"==> nxge_n2_serdes_init port<%d>: PLL cfg.l 0x%x (0x%x)",
"==> nxge_n2_kt_serdes_init port<%d>: (0x%x)",
#endif
/* Set loopback mode if necessary */
"==> nxge_n2_kt_serdes_init port<%d>: "
goto fail;
}
}
} else {
"nxge_n2_kt_serdes_init:port<%d> - "
"unsupported port mode %d",
goto fail;
}
NXGE_DELAY(20);
/* Clear the test register (offset 0x8004) */
goto fail;
}
NXGE_DELAY(20);
/* init TX channels */
if (mode_1g)
goto fail;
goto fail;
"==> nxge_n2_kt_serdes_init port<%d>: "
"==> nxge_n2_kt_serdes_init port<%d>: "
}
/* init RX channels */
/* 1G mode only write to the first channel */
!= NXGE_OK)
goto fail;
!= NXGE_OK)
goto fail;
"==> nxge_n2_kt_serdes_init port<%d>: "
"==> nxge_n2_kt_serdes_init port<%d>: "
}
"<== nxge_n2_kt_serdes_init port<%d>", portn));
return (NXGE_OK);
fail:
"nxge_n2_serdes_init: Failed to initialize N2 serdes for port<%d>",
portn));
return (status);
}
/* Initialize the Neptune Internal Serdes for 10G (Neptune only) */
static nxge_status_t
{
int chan, i;
return (NXGE_OK);
"==> nxge_neptune_10G_serdes_init port<%d>", portn));
switch (portn) {
case 0:
/* Reset Serdes */
NXGE_DELAY(20);
NXGE_DELAY(2000);
/* Configure Serdes to 10G mode */
(0x5 << ESR_CTL_OUT_EMPH_0_SHIFT) |
(0x5 << ESR_CTL_OUT_EMPH_1_SHIFT) |
(0x5 << ESR_CTL_OUT_EMPH_2_SHIFT) |
(0x5 << ESR_CTL_OUT_EMPH_3_SHIFT) |
(0x5 << ESR_CTL_OUT_EMPH_3_SHIFT) |
(0x1 << ESR_CTL_LOSADJ_0_SHIFT) |
(0x1 << ESR_CTL_LOSADJ_1_SHIFT) |
(0x1 << ESR_CTL_LOSADJ_2_SHIFT) |
(0x1 << ESR_CTL_LOSADJ_3_SHIFT));
/* Set Serdes0 Internal Loopback if necessary */
} else {
}
break;
case 1:
/* Reset Serdes */
NXGE_DELAY(20);
NXGE_DELAY(2000);
/* Configure Serdes to 10G mode */
(0x5 << ESR_CTL_OUT_EMPH_0_SHIFT) |
(0x5 << ESR_CTL_OUT_EMPH_1_SHIFT) |
(0x5 << ESR_CTL_OUT_EMPH_2_SHIFT) |
(0x5 << ESR_CTL_OUT_EMPH_3_SHIFT) |
(0x5 << ESR_CTL_OUT_EMPH_3_SHIFT) |
(0x1 << ESR_CTL_LOSADJ_0_SHIFT) |
(0x1 << ESR_CTL_LOSADJ_1_SHIFT) |
(0x1 << ESR_CTL_LOSADJ_2_SHIFT) |
(0x1 << ESR_CTL_LOSADJ_3_SHIFT));
/* Set Serdes1 Internal Loopback if necessary */
} else {
}
break;
default:
/* Nothing to do here */
goto done;
}
/* init TX RX channels */
goto fail;
goto fail;
goto fail;
goto fail;
goto fail;
goto fail;
goto fail;
goto fail;
}
/* Apply Tx core reset */
goto fail;
goto fail;
NXGE_DELAY(200);
/* Apply Rx core reset */
goto fail;
NXGE_DELAY(200);
goto fail;
NXGE_DELAY(200);
goto fail;
goto fail;
"Failed to reset port<%d> XAUI Serdes "
"(val16l 0x%x val16h 0x%x)",
}
if (portn == 0) {
/* Wait for serdes to be ready */
for (i = 0; i < MAX_SERDES_RDY_RETRIES; i++) {
if ((val & ESR_SIG_P0_BITS_MASK) !=
else
break;
}
if (i == MAX_SERDES_RDY_RETRIES) {
/*
* RDY signal stays low may due to the absent of the
* external PHY, it is not an error condition. But still
* print the message for the debugging purpose when link
* stays down
*/
"nxge_neptune_10G_serdes_init: "
goto done;
}
} else if (portn == 1) {
/* Wait for serdes to be ready */
for (i = 0; i < MAX_SERDES_RDY_RETRIES; i++) {
if ((val & ESR_SIG_P1_BITS_MASK) !=
else
break;
}
if (i == MAX_SERDES_RDY_RETRIES) {
/*
* RDY signal stays low may due to the absent of the
* external PHY, it is not an error condition. But still
* print the message for the debugging purpose when link
* stays down
*/
"nxge_neptune_10G_serdes_init: "
goto done;
}
}
done:
"<== nxge_neptune_10G_serdes_init port<%d>", portn));
return (NXGE_OK);
fail:
"nxge_neptune_10G_serdes_init: "
"Failed to initialize Neptune serdes for port<%d>", portn));
return (status);
}
/* Initialize Neptune Internal Serdes for 1G (Neptune only) */
static nxge_status_t
{
int chan;
"==> nxge_1G_serdes_init port<%d>", portn));
switch (portn) {
case 0:
/* Assert the reset register */
val |= ESR_RESET_0;
/* Set the PLL register to 0x79 */
/* Set the control register to 0x249249f */
/* Set Serdes0 Internal Loopback if necessary */
/* Set pad loopback modes 0xaa */
} else {
}
/* Deassert the reset register */
val &= ~ESR_RESET_0;
break;
case 1:
/* Assert the reset register */
val |= ESR_RESET_1;
/* Set PLL register to 0x79 */
/* Set the control register to 0x249249f */
/* Set Serdes1 Internal Loopback if necessary */
/* Set pad loopback mode 0xaa */
} else {
}
/* Deassert the reset register */
val &= ~ESR_RESET_1;
break;
default:
/* Nothing to do here */
goto done;
}
/* init TX RX channels */
goto fail;
}
goto fail;
}
goto fail;
}
goto fail;
}
goto fail;
}
goto fail;
}
goto fail;
}
goto fail;
}
}
goto fail;
}
goto fail;
}
goto fail;
}
goto fail;
}
/* Apply Tx core reset */
goto fail;
}
NXGE_OK) {
goto fail;
}
NXGE_DELAY(200);
/* Apply Rx core reset */
NXGE_OK) {
goto fail;
}
NXGE_DELAY(200);
goto fail;
}
NXGE_DELAY(200);
goto fail;
}
goto fail;
}
"Failed to reset port<%d> XAUI Serdes "
status = NXGE_ERROR;
goto fail;
}
NXGE_DELAY(200);
"nxge_neptune_serdes_init: read internal signal reg port<%d> "
if (portn == 0) {
if ((val & ESR_SIG_P0_BITS_MASK_1G) !=
/*
* RDY signal stays low may due to the absent of the
* external PHY, it is not an error condition. But still
* print the message for the debugging purpose when link
* stays down
*/
"nxge_neptune_1G_serdes_init: "
goto done;
}
} else if (portn == 1) {
if ((val & ESR_SIG_P1_BITS_MASK_1G) !=
/*
* RDY signal stays low may due to the absent of the
* external PHY, it is not an error condition. But still
* print the message for the debugging purpose when link
* stays down
*/
"nxge_neptune_1G_serdes_init: "
goto done;
}
}
done:
"<== nxge_1G_serdes_init port<%d>", portn));
return (NXGE_OK);
fail:
"nxge_1G_serdes_init: "
"Failed to initialize Neptune serdes for port<%d>",
portn));
return (status);
}
/* Initialize the BCM 8704 xcvr */
static nxge_status_t
{
#ifdef NXGE_DEBUG
#endif
#ifdef NXGE_DEBUG
#endif
portn));
/* Reset the transceiver */
goto fail;
goto fail;
do {
drv_usecwait(500);
goto fail;
delay++;
if (delay == 100) {
"failed to reset Transceiver on port<%d>", portn));
status = NXGE_ERROR;
goto fail;
}
/* Set to 0x7FBF */
!= NXGE_OK)
goto fail;
/* Set to 0x164 */
goto fail;
/*
* According to Broadcom's instruction, SW needs to read
* back these registers twice after written.
*/
!= NXGE_OK)
goto fail;
!= NXGE_OK)
goto fail;
!= NXGE_OK)
goto fail;
!= NXGE_OK)
goto fail;
/* Enable Tx and Rx LEDs to be driven by traffic */
goto fail;
if (NXGE_IS_XAUI_PLATFORM(nxgep)) {
} else {
}
goto fail;
NXGE_DELAY(1000000);
/* Set BCM8704 Internal Loopback mode if necessary */
!= NXGE_OK)
goto fail;
else
!= NXGE_OK)
goto fail;
goto fail;
goto fail;
goto fail;
#ifdef NXGE_DEBUG
/* Diagnose link issue if link is not up */
&val);
goto fail;
goto fail;
goto fail;
goto fail;
if (val != 0x3FC) {
"Cable not connected to peer or bad"
" cable on port<%d>\n", portn));
} else if (val == 0x639C) {
"Optical module (XFP) is bad or absent"
" on port<%d>\n", portn));
}
}
#endif
portn));
return (NXGE_OK);
fail:
"nxge_BCM8704_xcvr_init: failed to initialize transceiver for "
return (NXGE_ERROR);
}
/* Initialize the BCM 8706 Transceiver */
static nxge_status_t
{
#ifdef NXGE_DEBUG
#endif
portn));
/* Reset the transceiver */
goto fail;
goto fail;
do {
drv_usecwait(500);
goto fail;
delay++;
if (delay == 100) {
"failed to reset Transceiver on port<%d>", portn));
status = NXGE_ERROR;
goto fail;
}
NXGE_DELAY(1000000);
/* Set BCM8706 Internal Loopback mode if necessary */
!= NXGE_OK)
goto fail;
else
!= NXGE_OK)
goto fail;
/* Enable Tx and Rx LEDs to be driven by traffic */
goto fail;
goto fail;
portn));
return (NXGE_OK);
fail:
"nxge_BCM8706_xcvr_init: failed to initialize transceiver for "
return (status);
}
static void
{
value);
}
}
static nxge_status_t
{
else
fail:
return (status);
}
static void
{
"nxge_mrvl88x2011_led: nxge_mdio_write failed!!"));
}
}
static nxge_status_t
{
"==> nxge_mrvl88x2011_xcvr_init: port<%d> addr<0x%x>",
/* Set LED functions */
/* PCS activity */
/* Set internal loopback mode if necessary */
/* Enable PMD */
fail:
return (status);
}
/* Initialize the 10G Transceiver */
static nxge_status_t
{
#ifdef NXGE_DEBUG
#endif
portn));
/* Disable Link LEDs, with or without PHY */
goto done;
/* Skip MDIO, if PHY absent */
goto done;
}
/* Set Clause 45 */
case BCM8704_CHIP_ID:
break;
case BCM8706_CHIP_ID:
break;
case MRVL88X201X_CHIP_ID:
break;
default:
"Unknown chip ID 0x%x for 10G xcvr addr[%d]",
goto fail;
}
goto fail;
}
done:
portn));
return (NXGE_OK);
fail:
"nxge_10G_xcvr_init: failed to initialize transceiver for "
return (NXGE_ERROR);
}
/* Initialize the 1G copper (BCM 5464) Transceiver */
static nxge_status_t
{
goto done;
}
/* Set Clause 22 */
/* Set capability flags */
}
done:
return (status);
}
/*
* Although the Teranetics copper transceiver (TN1010) does not need
* to be initialized by the driver for passing packets, this funtion
* initializes the members of nxgep->statsp->mac_stats struct for
* kstat based on the value of nxgep->statsp->ports_stats.lb_mode.
* It also configures the TN1010 for PHY loopback to support SunVTS.
*
* TN1010 only has the option to disable advertisement for the 10G
* mode. So we can set it to either Dual Mode or 1G Only mode but
* can't set it to 10G Only mode.
*
*
* ----------------------------------------------------------------
* ----------------------------------------------------------------
* adv_autoneg_cap kstat nxge:1 | grep adv_cap_autoneg
* adv_10gfdx_cap
* adv_1000fdx_cap kstat nxge:1 | grep adv_cap_1000fdx
* adv_100fdx_cap kstat nxge:1 | grep adv_cap_100fdx
* adv_10fdx_cap kstat nxge:1 | grep adv_cap_10fdx
* adv_pause_cap kstat nxge:1 | grep adv_cap_pause
* ----------------------------------------------------------------
*/
static nxge_status_t
{
/*
* Initialize the xcvr statistics which are NOT controlled by ndd
*/
/*
* Read the TN1010 link speed and initialize capabilities kstat. Note
* that function nxge_check_tn1010_link repeatedly invoked by the
* timer will update link_speed real time.
*/
goto fail;
}
if (speed == TN1010_SPEED_1G) {
} else {
}
/* Whether we are in 1G or 10G mode, we always have the 1G capability */
/* TN1010 is not able to operate in the following states */
/* param_anar_pause can be modified by ndd -set */
/*
* The following 4 lines actually overwrites what ever the ndd command
* has set. For example, by command
* we could set param_arr[param_autoneg].value to n. However, because
* here we assign constants to these parameters, whatever we set with
* the "ndd -set" command will be replaced. So command
* kstat nxge:X | grep param
* will always show those constant values. In other words, the
* "ndd -set" command can NOT change the values of these 4 parameters
* even though the command appears to be successful.
*
* Note: TN1010 auto negotiation is always enabled.
*/
/*
* The following 4 ndd params have type NXGE_PARAM_MAC_DONT_SHOW as
* defined in nxge_param_arr[], therefore they are not seen by the
* "ndd -get" command and can not be changed by ndd. We just set
* them (both ndd param and kstat values) to constant 0 because TN1010
* does not support those speeds.
*/
/*
* adv_cap_pause has type NXGE_PARAM_MAC_RW, so it can be modified
* by ndd
*/
/*
* nxge_param_arr[] defines the adv_cap_asmpause with type
* NXGE_PARAM_DONT_SHOW, therefore they are NOT seen by the
* "ndd -get" command and can not be changed by ndd. Here we do not
* assign a constant to it so the default value defined in
* nxge_param_arr[] will be used to set the parameter and
* will be shown by the kstat.
*/
/*
* Initialize the link statistics.
*/
if (speed == TN1010_SPEED_1G) {
} else {
}
/*
* Because TN1010 does not have a link partner register, to
* figure out the link partner's capabilities is tricky. Here we
* just set the kstat based on our knowledge about the partner
* (The partner must support auto-neg because auto-negotiation
* has completed, it must support 1G or 10G because that is the
* negotiated speed we are using.)
*
* Note: Current kstat does not show lp_cap_10gfdx and
* lp_cap_10ghdx.
*/
if (speed == TN1010_SPEED_1G) {
} else {
}
/* Handle PHY loopback for SunVTS loopback test */
goto fail;
}
} else {
}
goto fail;
}
"<== nxge_1G_tn1010_xcvr_init status 0x%x", status));
return (status);
fail:
"<== nxge_1G_tn1010_xcvr_init status 0x%x", status));
return (status);
}
/* Initialize transceiver */
{
#ifdef NXGE_DEBUG
#endif
#ifdef NXGE_DEBUG
#endif
/*
* Initialize the xcvr statistics. nxgep->xcvr.xcvr_init will
* modify mac_stats.
*/
/*
* Initialize the link statistics.
*/
goto fail;
}
portn));
return (NXGE_OK);
fail:
"nxge_xcvr_init: failed to initialize transceiver for port<%d>",
portn));
return (status);
}
/* Look for transceiver type */
{
return (NXGE_ERROR);
return (NXGE_ERROR);
return (NXGE_OK);
}
/* Initialize the TxMAC sub-block */
{
portn));
/* Set Max and Min Frame Size */
/*
* Use maxframesize to configure the hardware maxframe size
* and minframesize to configure the hardware minframe size.
*/
"==> nxge_tx_mac_init: port<%d> "
"min framesize %d max framesize %d ",
portn));
rs);
if (rs != NPI_SUCCESS)
goto fail;
if (portt == PORT_TYPE_XMAC) {
0)) != NPI_SUCCESS)
goto fail;
if ((portmode == PORT_10G_FIBER) ||
(portmode == PORT_10G_COPPER) ||
(portmode == PORT_10G_TN1010) ||
(portmode == PORT_HSP_MODE) ||
(portmode == PORT_10G_SERDES)) {
if (rs != NPI_SUCCESS)
goto fail;
} else {
if (rs != NPI_SUCCESS)
goto fail;
}
goto fail;
!= NPI_SUCCESS)
goto fail;
} else {
0)) != NPI_SUCCESS)
goto fail;
rs);
if (rs != NPI_SUCCESS)
goto fail;
if (rs != NPI_SUCCESS)
goto fail;
goto fail;
}
portn));
return (NXGE_OK);
fail:
"nxge_tx_mac_init: failed to initialize port<%d> TXMAC", portn));
return (NXGE_ERROR | rs);
}
/* Initialize the RxMAC sub-block */
{
uint32_t i;
portn));
rs);
if (rs != NPI_SUCCESS)
goto fail;
if (rs != NPI_SUCCESS)
goto fail;
if (rs != NPI_SUCCESS)
goto fail;
/*
* Load the multicast hash filter bits.
*/
for (i = 0; i < MAC_MAX_HASH_ENTRY; i++) {
if (hash_filter != NULL) {
(NMCFILTER_REGS - 1) - i];
} else {
hashtab_e = 0;
}
goto fail;
}
if (portt == PORT_TYPE_XMAC) {
0)) != NPI_SUCCESS)
goto fail;
(void) nxge_fflp_init_hostinfo(nxgep);
xconfig)) != NPI_SUCCESS)
goto fail;
/* Comparison of mac unique address is always enabled on XMAC */
!= NPI_SUCCESS)
goto fail;
} else {
(void) nxge_fflp_init_hostinfo(nxgep);
0) != NPI_SUCCESS)
goto fail;
bconfig)) != NPI_SUCCESS)
goto fail;
/* Always enable comparison of mac unique address */
!= NPI_SUCCESS)
goto fail;
}
portn));
return (NXGE_OK);
fail:
"nxge_rx_mac_init: Failed to Initialize port<%d> RxMAC", portn));
return (NXGE_ERROR | rs);
}
/* Enable TXMAC */
{
goto fail;
/* based on speed */
CFG_XMAC_TX)) != NPI_SUCCESS)
goto fail;
} else {
CFG_BMAC_TX)) != NPI_SUCCESS)
goto fail;
}
return (NXGE_OK);
fail:
"nxgep_tx_mac_enable: Failed to enable port<%d> TxMAC",
if (rs != NPI_SUCCESS)
return (NXGE_ERROR | rs);
else
return (status);
}
/* Disable TXMAC */
{
if (isLDOMguest(nxgep))
return (NXGE_OK);
goto fail;
} else {
goto fail;
}
return (NXGE_OK);
fail:
"nxge_tx_mac_disable: Failed to disable port<%d> TxMAC",
return (NXGE_ERROR | rs);
}
/* Enable RXMAC */
{
/* This is a service-domain-only activity. */
if (isLDOMguest(nxgep))
return (status);
portn));
goto fail;
CFG_XMAC_RX)) != NPI_SUCCESS)
goto fail;
} else {
CFG_BMAC_RX)) != NPI_SUCCESS)
goto fail;
}
"<== nxge_rx_mac_enable: port<%d>", portn));
return (NXGE_OK);
fail:
"nxgep_rx_mac_enable: Failed to enable port<%d> RxMAC", portn));
if (rs != NPI_SUCCESS)
return (NXGE_ERROR | rs);
else
return (status);
}
/* Disable RXMAC */
{
/* If we are a guest domain driver, don't bother. */
if (isLDOMguest(nxgep))
return (NXGE_OK);
portn));
CFG_XMAC_RX)) != NPI_SUCCESS)
goto fail;
} else {
CFG_BMAC_RX)) != NPI_SUCCESS)
goto fail;
}
portn));
return (NXGE_OK);
fail:
"nxgep_rx_mac_disable: Failed to disable port<%d> RxMAC", portn));
return (NXGE_ERROR | rs);
}
/* Reset TXMAC */
{
portn));
!= NPI_SUCCESS)
goto fail;
} else {
!= NPI_SUCCESS)
goto fail;
}
portn));
return (NXGE_OK);
fail:
"nxge_tx_mac_reset: Failed to Reset TxMAC port<%d>", portn));
return (NXGE_ERROR | rs);
}
/* Reset RXMAC */
{
portn));
!= NPI_SUCCESS)
goto fail;
} else {
!= NPI_SUCCESS)
goto fail;
}
portn));
return (NXGE_OK);
fail:
"nxge_rx_mac_reset: Failed to Reset RxMAC port<%d>", portn));
return (NXGE_ERROR | rs);
}
/* 10G fiber link interrupt start routine */
static nxge_status_t
{
if (rs != NPI_SUCCESS)
return (NXGE_ERROR | rs);
else
return (NXGE_OK);
}
/* 10G fiber link interrupt stop routine */
static nxge_status_t
{
if (rs != NPI_SUCCESS)
return (NXGE_ERROR | rs);
else
return (NXGE_OK);
}
/* 1G fiber link interrupt start routine */
static nxge_status_t
{
if (rs != NPI_SUCCESS)
return (NXGE_ERROR | rs);
else
return (NXGE_OK);
}
/* 1G fiber link interrupt stop routine */
static nxge_status_t
{
if (rs != NPI_SUCCESS)
return (NXGE_ERROR | rs);
else
return (NXGE_OK);
}
/* 1G copper link interrupt start routine */
static nxge_status_t
{
if (rs != NPI_SUCCESS)
return (NXGE_ERROR | rs);
else
return (NXGE_OK);
}
/* 1G copper link interrupt stop routine */
static nxge_status_t
{
if (rs != NPI_SUCCESS)
return (NXGE_ERROR | rs);
else
return (NXGE_OK);
}
{
return (NXGE_OK);
if (enable == LINK_INTR_START)
else if (enable == LINK_INTR_STOP)
goto fail;
return (NXGE_OK);
fail:
"nxge_link_intr: Failed to set port<%d> mif intr mode", portn));
return (status);
}
/* Initialize 1G Fiber / Copper transceiver using Clause 22 */
{
/*
* The mif phy mode may be connected to either a copper link
* or fiber link. Read the mode control register to get the fiber
* configuration if it is hard-wired to fiber link.
*/
(void) nxge_mii_get_link_mode(nxgep);
return (nxge_mii_xcvr_fiber_init(nxgep));
}
/*
* Reset the transceiver.
*/
delay = 0;
#if defined(__i386)
#else
#endif
goto fail;
do {
drv_usecwait(500);
#if defined(__i386)
#else
#endif
goto fail;
delay++;
if (delay == 1000) {
goto fail;
}
#if defined(__i386)
#else
#endif
goto fail;
/*
* Initialize the xcvr statistics.
*/
/*
* Initialize the xcvr advertised capability statistics.
*/
/*
* Check for extended status just in case we're
* running a Gigibit phy.
*/
#if defined(__i386)
#else
#endif
goto fail;
} else {
}
/*
* Initialize 1G Statistics once the capability is established.
*/
/*
* Initialize the link statistics.
*/
/*
* Switch off Auto-negotiation, 100M and full duplex.
*/
#if defined(__i386)
#else
#endif
goto fail;
} else {
}
bcm5464r_aux.value = 0;
goto fail;
}
/* If auto-negotiation is desired */
"Restarting Auto-negotiation."));
/*
* Setup our Auto-negotiation advertisement register.
*/
}
/* Write to the auto-negotiation advertisement register */
#if defined(__i386)
#else
#endif
goto fail;
#if defined(__i386)
#else
#endif
goto fail;
}
} else {
/* Force to 1G */
#if defined(__i386)
#else
#endif
goto fail;
} else
/* Force to 100M */
} else
/* Force to 10M */
} else {
} else
}
}
/* BCM5464R 1000mbps external loopback mode */
#if defined(__i386)
#else
#endif
goto fail;
== nxge_lb_ext100) {
/* BCM5464R 100mbps external loopback mode */
== nxge_lb_ext10) {
/* BCM5464R 10mbps external loopback mode */
}
}
}
#if defined(__i386)
#else
#endif
goto fail;
#if defined(__i386)
#else
#endif
goto fail;
/*
* Initialize the xcvr status kept in the context structure.
*/
#if defined(__i386)
#else
#endif
goto fail;
fail:
"<== nxge_mii_xcvr_init status 0x%x", status));
return (status);
}
{
"nxge_mii_xcvr_fiber_init: "
/*
* Reset the transceiver.
*/
delay = 0;
#if defined(__i386)
goto fail;
#else
goto fail;
#endif
do {
drv_usecwait(500);
#if defined(__i386)
!= NXGE_OK)
goto fail;
#else
!= NXGE_OK)
goto fail;
#endif
delay++;
if (delay == 1000) {
goto fail;
}
#if defined(__i386)
goto fail;
#else
goto fail;
#endif
/*
* Initialize the xcvr statistics.
*/
/*
* Initialize the xcvr advertised capability statistics.
*/
/*
* Check for extended status just in case we're
* running a Gigibit phy.
*/
#if defined(__i386)
goto fail;
#else
goto fail;
#endif
} else {
}
/*
* Initialize 1G Statistics once the capability is established.
*/
/*
* Initialize the link statistics.
*/
/*
* Switch off Auto-negotiation, 100M and full duplex.
*/
#if defined(__i386)
goto fail;
#else
goto fail;
#endif
} else {
}
bcm5464r_aux.value = 0;
goto fail;
}
/* BCM5464R 1000mbps external loopback mode */
#if defined(__i386)
goto fail;
#else
goto fail;
#endif
}
#if defined(__i386)
goto fail;
#else
goto fail;
#endif
"nxge_mii_xcvr_fiber_init: value wrote bmcr = 0x%x",
#if defined(__i386)
goto fail;
#else
goto fail;
#endif
/*
* Initialize the xcvr status kept in the context structure.
*/
#if defined(__i386)
goto fail;
#else
goto fail;
#endif
"<== nxge_mii_xcvr_fiber_init status 0x%x", status));
return (status);
fail:
"<== nxge_mii_xcvr_fiber_init status 0x%x", status));
return (status);
}
/* Read from a MII compliant register */
{
goto fail;
goto fail;
} else
goto fail;
return (NXGE_OK);
fail:
"nxge_mii_read: Failed to read mii on xcvr %d", xcvr_portn));
return (NXGE_ERROR | rs);
}
/* Write to a MII compliant Register */
{
goto fail;
goto fail;
} else
goto fail;
return (NXGE_OK);
fail:
"nxge_mii_write: Failed to write mii on xcvr %d", xcvr_portn));
return (NXGE_ERROR | rs);
}
/*
* Perform write to Clause45 serdes / transceiver device
* Arguments:
* xcvr_portn: The IEEE 802.3 Clause45 PHYAD, it is the same as port
* number if nxge_mdio_write is used for accessing the
* internal LSIL serdes. Otherwise PHYAD is different
* for different platforms.
* device: With each PHYAD, the driver can use MDIO to control
* multiple devices inside the PHY, here "device" is an
* MMD (MDIO managable device).
* xcvr_reg: Each device has multiple registers. xcvr_reg specifies
* the register which the driver will write value to.
* value: The register value will be filled in.
*/
{
xcvr_portn));
goto fail;
xcvr_portn));
return (NXGE_OK);
fail:
"nxge_mdio_read: Failed to read mdio on xcvr %d", xcvr_portn));
return (NXGE_ERROR | rs);
}
/* Perform write to Clause45 serdes / transceiver device */
{
xcvr_portn));
goto fail;
xcvr_portn));
return (NXGE_OK);
fail:
"nxge_mdio_write: Failed to write mdio on xcvr %d", xcvr_portn));
return (NXGE_ERROR | rs);
}
/* Check MII to see if there is any link status change */
{
"==> nxge_mii_check bmsr 0x%x bmsr_int 0x%x",
"==> nxge_mii_check (link up) bmsr 0x%x bmsr_int 0x%x",
"==> nxge_mii_check (link up) soft bmsr 0x%x bmsr_int "
} else {
"Link down cable problem"));
*link_up = LINK_IS_DOWN;
}
}
else
}
}
} else
"==> nxge_mii_check "
"(auto negotiation complete or link up) "
"soft bmsr 0x%x bmsr_int 0x%x",
#if defined(__i386)
#else
#endif
goto fail;
#if defined(__i386)
#else
#endif
goto fail;
#if defined(__i386)
#else
#endif
goto fail;
#if defined(__i386)
#else
#endif
goto fail;
} else if (
}
}
} else {
goto fail;
}
}
int link_pause;
link_pause = 0;
} else {
link_pause = 1;
}
} else {
}
}
}
*link_up = LINK_IS_UP;
}
if (nxgep->link_notify) {
}
return (NXGE_OK);
fail:
"nxge_mii_check: Unable to check MII"));
return (status);
}
/*
* Check PCS to see if there is any link status change.
* This function is called by PORT_1G_SERDES only.
*/
void
{
if (linkup) {
if (nxgep->link_notify ||
*link_up = LINK_IS_UP;
}
} else {
if (nxgep->link_notify ||
*link_up = LINK_IS_DOWN;
}
}
}
/* Add a multicast address entry into the HW hash table */
{
uint_t j;
"Allocating hash filter storage."));
KM_SLEEP);
}
j = mchash / HASH_REG_WIDTH;
}
if (rx_init) {
goto fail;
goto fail;
}
return (NXGE_OK);
fail:
"Unable to add multicast address"));
return (status);
}
/* Remove a multicast address entry from the HW hash table */
{
uint_t j;
"Hash filter already de_allocated."));
return (NXGE_OK);
}
j = mchash / HASH_REG_WIDTH;
}
if (hash_filter->hash_ref_cnt == 0) {
"De-allocating hash filter storage."));
}
if (rx_init) {
goto fail;
goto fail;
}
return (NXGE_OK);
fail:
"Unable to remove multicast address"));
return (status);
}
/* Set MAC address into MAC address HW registers */
{
/*
* Exit if the address is same as ouraddr or multicast or broadcast
*/
goto nxge_set_mac_addr_exit;
}
/*
* Set new interface local address and re-init device.
* This is destructive to any other streams attached
* to this device.
*/
goto fail;
goto fail;
goto nxge_set_mac_addr_end;
return (NXGE_OK);
fail:
"Unable to set mac address"));
return (status);
}
static
{
/* If the poll has been cancelled, return STOP. */
nxge->nxge_link_poll_timerid = 0;
"nxge_check_%s_link(port<%d>) stopped.",
return (CHECK_LINK_STOP);
}
return (CHECK_LINK_RESCHEDULE);
}
/*
* Check status of MII (MIF or PCS) link.
* This function is called once per second, that is because this function
* calls nxge_link_monitor with LINK_MONITOR_START, which starts a timer to
* call this function recursively.
*/
static nxge_status_t
{
return (NXGE_ERROR);
return (NXGE_OK);
portn));
goto nxge_check_mii_link_exit;
default:
#if defined(__i386)
#else
#endif
goto fail;
}
"==> nxge_check_mii_link port<0x%x> "
"RIGHT AFTER READ bmsr_data 0x%x (nxgep->bmsr 0x%x ",
#if defined(__i386)
#else
#endif
goto fail;
#if defined(__i386)
#else
#endif
goto fail;
}
}
}
/* Workaround for link down issue */
goto nxge_check_mii_link_exit;
}
"==> nxge_check_mii_link port<0x%x> :"
"BEFORE BMSR ^ nxgep->bmsr 0x%x bmsr_data 0x%x",
"==> nxge_check_mii_link port<0x%x> CALLING "
"bmsr_data 0x%x bmsr_ints.value 0x%x",
goto fail;
}
break;
case PORT_1G_SERDES:
/*
* Above default is for all cases except PORT_1G_SERDES.
* The default case gets information from the PHY, but a
* nxge whose portmode equals PORT_1G_SERDES does not
* have a PHY.
*/
"==> nxge_check_mii_link port<%d> (SERDES)", portn));
break;
}
if (link_up == LINK_IS_UP) {
} else if (link_up == LINK_IS_DOWN) {
}
portn));
return (NXGE_OK);
fail:
"nxge_check_mii_link: Failed to check link port<%d>", portn));
return (status);
}
/*ARGSUSED*/
static nxge_status_t
{
return (NXGE_ERROR);
return (NXGE_OK);
val = 0;
rs = NPI_SUCCESS;
portn));
default:
/*
* Check if the phy is present in case of hot swappable phy
*/
if (nxgep->hot_swappable_phy) {
/*
* If this is the 2nd Goa port, then check 2 addresses
* to take care of the Goa NEM card requirements.
*/
if (portn == 1) {
if (nxge_is_phy_present(nxgep,
goto phy_check_done;
}
}
if (nxge_is_phy_present(nxgep,
}
/* Check back-to-back XAUI connect to detect Opus NEM */
if (rs != 0)
goto fail;
if (val & XPCS_STATUS_LANE_ALIGN) {
}
if (nxgep->phy_absent) {
if (phy_present_now) {
/*
* Detect, Initialize phy and do link up
* set xcvr vals, link_init, nxge_init
*/
"Hot swappable phy DETECTED!!"));
(void) nxge_xcvr_find(nxgep);
(void) nxge_link_init(nxgep);
"Hot swappable "
"phy present, but"
" driver init"
" failed..."));
goto fail;
}
}
} else if (link_up) { /* XAUI linkup, no PHY */
/*
* This is the back-to-back XAUI
* connect case for Opus NEM.
*/
"HSP 10G Serdes DETECTED!!"));
break;
}
goto start_link_check;
} else if (!phy_present_now) {
/*
* Phy gone, bring link down reset xcvr vals
*/
"Hot swappable phy REMOVED!!"));
(void) nxge_xcvr_find(nxgep);
goto start_link_check;
}
}
} else {
}
goto fail;
break;
case PORT_10G_SERDES:
XPCS_REG_STATUS, &val);
if (rs != 0)
goto fail;
if (val & XPCS_STATUS_LANE_ALIGN) {
}
"==> nxge_check_10g_link port<%d> "
"XPCS_REG_STATUS2 0x%x link_up %d",
break;
}
if (link_up) {
if (nxgep->link_notify ||
goto fail;
}
} else {
if (nxgep->link_notify ||
goto fail;
"Link down cable problem"));
/*
* NEM was unplugged, set up xcvr table
* to find another xcvr in the future.
*/
(void) nxge_xcvr_find(nxgep);
}
}
}
portn));
return (NXGE_OK);
fail:
(void) nxge_check_link_stop(nxgep);
"nxge_check_10g_link: Failed to check link port<%d>",
portn));
return (status);
}
/* Declare link down */
void
{
char link_stat_msg[64];
if (nxge_no_msg == B_FALSE) {
}
}
/* Declare link up */
void
{
char link_stat_msg[64];
else
/* Clean up symbol errors incurred during link transition */
}
/*
* If the driver was plumbed without a link (therefore auto-negotiation
* could not complete), the driver will detect a link up when a cable
* conneting to a link partner is plugged into the port. By the time
* link-up is detected, auto-negotiation should have completed (The
* TN1010 tries to contact a link partner every 8~24ms). Here we re-
* This is necessary only for the TN1010 basad device because only the
* TN1010 supports dual speeds.
*/
(void) nxge_set_tn1010_param(nxgep);
/*
* nxge_xcvr_find calls nxge_get_xcvr_type (which sets
* nxgep->portmode) and nxge_setup_xcvr_table (which sets
* the nxgep->xcvr to the proper nxge_xcvr_table_t struct).
*/
"nxge_link_is_up: nxge_xcvr_find failed"));
}
/* nxge_link_init calls nxge_xcvr_init and nxge_serdes_init */
"nxge_link_is_up: nxge_link_init failed"));
}
/*
* nxge_mac_init calls many subroutines including
* nxge_xif_init which sets XGMII or GMII mode
*/
"nxge_link_is_up: nxge_mac_init failed"));
}
} else {
(void) nxge_xif_init(nxgep);
}
if (nxge_no_msg == B_FALSE) {
}
}
#ifdef NXGE_DEBUG
/* Dump all TN1010 Status registers */
static void
{
}
#endif
/*
* Calculate the bit in the multicast address filter
* that selects the given * address.
* Note: For GEM, the last 8-bits are used.
*/
{
uint32_t c;
int byte;
int bit;
else
c >>= 1;
}
}
}
/* Reset serdes */
{
drv_usecwait(500);
return (NXGE_OK);
}
/*
* This function monitors link status using interrupt or polling.
* It calls nxgep->xcvr.check_link, a member function of
* nxge_xcvr_table_t. But nxgep->xcvr.check_link calls this
* function back, that is why the check_link routine is
* executed periodically.
*/
{
/* If we are a guest domain driver, don't bother. */
if (isLDOMguest(nxgep))
return (status);
/*
* Return immediately if this is an imaginary XMAC port.
* (At least, we don't have 4-port XMAC cards yet.)
*/
return (NXGE_OK);
/* stats has not been allocated. */
return (NXGE_OK);
}
/* Don't check link if we're in internal loopback mode */
return (NXGE_OK);
"==> nxge_link_monitor port<%d> enable=%d",
if (enable == LINK_MONITOR_START) {
!= NXGE_OK)
goto fail;
} else {
/*
* check_link_stop means "Stop the link check", so
* we return without starting the timer.
*/
return (NXGE_OK);
/*
* Otherwise fire the timer for the nxge to check
* the link using the check_link function
* of the nxge_xcvr_table and pass "nxgep" as the
* argument to the check_link function.
*/
} else {
return (NXGE_ERROR);
}
}
} else {
!= NXGE_OK)
goto fail;
} else {
/* If <timerid> == 0, the link monitor has */
/* never been started, or just now stopped. */
if (nxgep->nxge_link_poll_timerid == 0) {
return (NXGE_OK);
}
if (rv == -1) {
"==> stopping port %d: "
"cv_timedwait(%d) timed out",
nxgep->nxge_link_poll_timerid = 0;
}
}
}
"<== nxge_link_monitor port<%d> enable=%d",
return (NXGE_OK);
fail:
return (status);
}
{
/* magic is 0 if driver is not attached */
return (NXGE_ERROR);
}
/* Link has been stopped, no need to continue */
return (NXGE_OK);
}
goto fail;
if (link_up == LINK_IS_UP)
else if (link_up == LINK_IS_DOWN)
/*
* nxge_link_monitor will call (nxgep->xcvr.check_link)
* which could be THIS function.
*/
return (NXGE_OK);
fail:
"nxge_check_tn1010_link: Failed to check link"));
return (status);
}
/*
* Fill variable "link_up" with either LINK_IS_UP or LINK_IS_DOWN.
*/
static nxge_status_t
{
/* Check if link is up */
!= NXGE_OK) {
goto fail;
}
/*
* nxge_link_is_up has called nxge_set_tn1010_param and set
* portmode and link_speed
*/
if (val & TN1010_AN_LINK_STAT_BIT) {
if (nxgep->link_notify ||
*link_up = LINK_IS_UP;
}
} else {
if (nxgep->link_notify ||
*link_up = LINK_IS_DOWN;
}
}
return (NXGE_OK);
fail:
"nxge_tn1010_check: Unable to check TN1010"));
return (status);
}
/* Set promiscous mode */
{
goto fail;
}
goto fail;
}
if (on)
else
return (NXGE_OK);
fail:
"Unable to set promisc (%d)", on));
return (status);
}
/*ARGSUSED*/
{
#ifdef NXGE_DEBUG
#endif
#if NXGE_MIF
#endif
#ifdef NXGE_MIF
}
#endif
return (DDI_INTR_CLAIMED);
return (DDI_INTR_UNCLAIMED);
}
/*ARGSUSED*/
{
}
/*
* This interrupt handler is for a specific
* mac port.
*/
"==> nxge_mac_intr: reading mac stats: port<%d>", portn));
(xmac_tx_iconfig_t *)&status);
if (rs != NPI_SUCCESS)
goto npi_fail;
if (status & ICFG_XMAC_TX_ALL) {
if (status & ICFG_XMAC_TX_UNDERRUN) {
}
if (status & ICFG_XMAC_TX_MAX_PACKET_ERR) {
/*
* Do not send FMA ereport because this
* error does not indicate HW failure.
*/
}
if (status & ICFG_XMAC_TX_OVERFLOW) {
}
if (status & ICFG_XMAC_TX_FIFO_XFR_ERR) {
}
if (status & ICFG_XMAC_TX_BYTE_CNT_EXP) {
}
if (status & ICFG_XMAC_TX_FRAME_CNT_EXP) {
}
}
(xmac_rx_iconfig_t *)&status);
if (rs != NPI_SUCCESS)
goto npi_fail;
if (status & ICFG_XMAC_RX_ALL) {
if (status & ICFG_XMAC_RX_OVERFLOW)
if (status & ICFG_XMAC_RX_UNDERFLOW) {
}
/*
* Do not send FMA ereport for the following 3 errors
* because they do not indicate HW failures.
*/
if (status & ICFG_XMAC_RX_CRC_ERR_CNT_EXP) {
}
if (status & ICFG_XMAC_RX_LEN_ERR_CNT_EXP) {
}
if (status & ICFG_XMAC_RX_VIOL_ERR_CNT_EXP) {
}
if (status & ICFG_XMAC_RX_OCT_CNT_EXP) {
}
if (status & ICFG_XMAC_RX_HST_CNT1_EXP) {
}
if (status & ICFG_XMAC_RX_HST_CNT2_EXP) {
}
if (status & ICFG_XMAC_RX_HST_CNT3_EXP) {
}
if (status & ICFG_XMAC_RX_HST_CNT4_EXP) {
}
if (status & ICFG_XMAC_RX_HST_CNT5_EXP) {
}
if (status & ICFG_XMAC_RX_HST_CNT6_EXP) {
}
if (status & ICFG_XMAC_RX_BCAST_CNT_EXP) {
}
if (status & ICFG_XMAC_RX_MCAST_CNT_EXP) {
}
/*
* Do not send FMA ereport for the following 3 errors
* because they do not indicate HW failures.
*/
if (status & ICFG_XMAC_RX_FRAG_CNT_EXP) {
}
if (status & ICFG_XMAC_RX_ALIGNERR_CNT_EXP) {
}
if (status & ICFG_XMAC_RX_LINK_FLT_CNT_EXP) {
}
if (status & ICFG_XMAC_RX_REMOTE_FLT_DET) {
}
if (status & ICFG_XMAC_RX_LOCAL_FLT_DET) {
}
}
(xmac_ctl_iconfig_t *)&status);
if (rs != NPI_SUCCESS)
goto npi_fail;
if (status & ICFG_XMAC_CTRL_ALL) {
if (status & ICFG_XMAC_CTRL_PAUSE_RCVD)
if (status & ICFG_XMAC_CTRL_PAUSE_STATE)
}
(bmac_tx_iconfig_t *)&status);
if (rs != NPI_SUCCESS)
goto npi_fail;
if (status & ICFG_BMAC_TX_ALL) {
if (status & ICFG_BMAC_TX_UNDERFLOW) {
}
if (status & ICFG_BMAC_TX_MAXPKTSZ_ERR) {
}
if (status & ICFG_BMAC_TX_BYTE_CNT_EXP) {
}
if (status & ICFG_BMAC_TX_FRAME_CNT_EXP) {
}
}
(bmac_rx_iconfig_t *)&status);
if (rs != NPI_SUCCESS)
goto npi_fail;
if (status & ICFG_BMAC_RX_ALL) {
if (status & ICFG_BMAC_RX_OVERFLOW) {
}
if (status & ICFG_BMAC_RX_FRAME_CNT_EXP) {
}
if (status & ICFG_BMAC_RX_CRC_ERR_CNT_EXP) {
}
if (status & ICFG_BMAC_RX_LEN_ERR_CNT_EXP) {
}
}
if (status & ICFG_BMAC_RX_BYTE_CNT_EXP) {
}
if (status & ICFG_BMAC_RX_ALIGNERR_CNT_EXP) {
}
(bmac_ctl_iconfig_t *)&status);
if (rs != NPI_SUCCESS)
goto npi_fail;
if (status & ICFG_BMAC_CTL_ALL) {
if (status & ICFG_BMAC_CTL_RCVPAUSE)
if (status & ICFG_BMAC_CTL_INPAUSE_ST)
}
}
}
return (DDI_INTR_CLAIMED);
return (DDI_INTR_UNCLAIMED);
}
{
#ifdef NXGE_DEBUG_SYMBOL_ERR
#endif
#ifdef NXGE_DEBUG_SYMBOL_ERR
/* Check Device 3 Register Device 3 0xC809 */
if ((val_debug & ~0x200) != 0) {
&val_debug);
}
if (val != 0)
if (val != 0)
if (val != 0)
#endif
/* Check from BCM8704 if 10G link is up or down */
/* Check Device 1 Register 0xA bit0 */
goto fail;
/* Check Device 3 Register 0x20 bit0 */
goto fail;
/* Check Device 4 Register 0x18 bit12 */
goto fail;
case BCM8704_CHIP_ID:
break;
case BCM8706_CHIP_ID:
break;
default:
goto fail;
}
#ifdef NXGE_DEBUG_ALIGN_ERR
/* Temp workaround for link down issue */
if (pcs_blk_lock == B_FALSE) {
if (val2 != 0x4) {
}
}
if (link_align == B_FALSE) {
if (val3 != 0x140f) {
link_align = B_TRUE;
}
}
"!LINK DEBUG: port %d Dev3 or Dev4 read zero\n",
}
}
#endif
return (NXGE_OK);
fail:
return (status);
}
static nxge_status_t
{
/* Check from Marvell 88X2011 if 10G link is up or down */
"nxge_check_mrvl88x2011_link: pmd=0x%x", val));
/* Check PMC Register : 3.0001.2 == 1: read twice */
"nxge_check_mrvl88x2011_link: pcs=0x%x", val));
/* Check XGXS Register : 4.0018.[0-3,12] */
"nxge_check_mrvl88x2011_link: xgxs=0x%x", val));
fail:
/* PCS OFF */
} else {
/* PCS Activity */
}
" <== nxge_check_mrvl88x2011_link: up=%d", *link_up));
return (status);
}
{
!= NPI_SUCCESS)
return (NXGE_ERROR);
else
return (NXGE_OK);
}
{
!= NPI_SUCCESS)
return (NXGE_ERROR);
else
return (NXGE_OK);
}
static boolean_t
{
uint32_t pma_pmd_id = 0;
"nxge_is_phy_present: pma_pmd_id[0x%x]", pma_pmd_id));
goto found_phy;
"nxge_is_phy_present: pcs_id[0x%x]", pcs_id));
goto found_phy;
"nxge_is_phy_present: phy_id[0x%x]", phy_id));
goto found_phy;
return (B_FALSE);
return (B_TRUE);
}
/* Check if the given id read using the given MDIO Clause is supported */
static boolean_t
{
int i;
switch (type) {
case CLAUSE_45_TYPE:
for (i = 0; i < NUM_CLAUSE_45_IDS; i++) {
if (((nxge_supported_cl45_ids[i] & BCM_PHY_ID_MASK) ==
(id & BCM_PHY_ID_MASK)) ||
break;
}
}
break;
case CLAUSE_22_TYPE:
for (i = 0; i < NUM_CLAUSE_22_IDS; i++) {
if ((nxge_supported_cl22_ids[i] & BCM_PHY_ID_MASK) ==
(id & BCM_PHY_ID_MASK)) {
break;
}
}
break;
default:
break;
}
return (found);
}
static uint32_t
{
uint32_t pma_pmd_dev_id = 0;
/* Concatenate the Device ID stored in two registers. */
pma_pmd_dev_id |= val2;
return (pma_pmd_dev_id);
}
static uint32_t
{
uint32_t pcs_dev_id = 0;
pcs_dev_id = val1;
pcs_dev_id |= val2;
return (pcs_dev_id);
}
static uint32_t
{
&val1);
if (npi_status != NPI_SUCCESS) {
"clause 22 read to reg 2 failed!!!"));
goto exit;
}
&val2);
if (npi_status != 0) {
"clause 22 read to reg 3 failed!!!"));
goto exit;
}
exit:
return (phy_id);
}
/*
* Scan the PHY ports 0 through 31 to get the PHY ID using Clause 22 MDIO
* read. Then use the values obtained to determine the phy type of each port
* and the Neptune type.
*
* This function sets hw_p->xcvr_addr[i] for future MDIO access and set
* hw_p->niu_type for each nxge instance to figure out nxgep->mac.portmode
* in case the portmode information is not available via OBP, nxge.conf,
* VPD or SEEPROM.
*/
{
int i, j, l;
uint32_t pma_pmd_dev_id = 0;
uint32_t pcs_dev_id = 0;
"==> nxge_scan_ports_phy: nxge niu_type[0x%x]",
if (isLDOMguest(nxgep)) {
return (NXGE_OK);
}
j = l = 0;
total_port_fd = total_phy_fd = 0;
/*
* for on chip serdes usages. "i" in the following for loop starts at 6.
*/
for (i = NXGE_EXT_PHY_PORT_ST; i < NXGE_MAX_PHY_PORTS; i++) {
pma_pmd_dev_fd[i] = 1;
"PMA/PMD dev %x found", i, pma_pmd_dev_id));
if (j < NXGE_PORTS_NEPTUNE) {
if ((pma_pmd_dev_id & TN1010_DEV_ID_MASK)
== TN1010_DEV_ID) {
} else {
port_pma_pmd_dev_id[j] =
}
port_fd_arr[j] = (uint8_t)i;
j++;
}
} else {
pma_pmd_dev_fd[i] = 0;
}
pcs_dev_fd[i] = 1;
"dev %x found", i, pcs_dev_id));
if (pma_pmd_dev_fd[i] == 1) {
if ((pcs_dev_id & TN1010_DEV_ID_MASK)
== TN1010_DEV_ID) {
port_pcs_dev_id[j - 1] =
} else {
port_pcs_dev_id[j - 1] =
}
} else {
if (j < NXGE_PORTS_NEPTUNE) {
if ((pcs_dev_id & TN1010_DEV_ID_MASK)
== TN1010_DEV_ID) {
port_pcs_dev_id[j] =
} else {
port_pcs_dev_id[j] =
}
port_fd_arr[j] = (uint8_t)i;
j++;
}
}
} else {
pcs_dev_fd[i] = 0;
}
if (pcs_dev_fd[i] || pma_pmd_dev_fd[i]) {
total_port_fd ++;
}
total_phy_fd ++;
"%x found", i, phy_id));
if (l < NXGE_PORTS_NEPTUNE) {
if ((phy_id & TN1010_DEV_ID_MASK)
== TN1010_DEV_ID) {
port_phy_id[l] = TN1010_DEV_ID;
} else {
port_phy_id[l]
= phy_id & BCM_PHY_ID_MASK;
}
phy_fd_arr[l] = (uint8_t)i;
l++;
}
}
}
switch (total_port_fd) {
case 2:
switch (total_phy_fd) {
case 2:
/* 2 10G, 2 1G RGMII Fiber / copper */
if ((((port_pcs_dev_id[0] == PHY_BCM8704_FAMILY) &&
((port_pma_pmd_dev_id[0] == PHY_BCM8704_FAMILY) &&
((port_phy_id[0] == PHY_BCM5482_FAMILY) &&
switch (hw_p->platform_type) {
case P_NEPTUNE_ROCK:
/*
* ROCK platform has assigned a lower
* addr to port 1. (port 0 = 0x9 and
* port 1 = 0x8).
*/
"Rock with 2 10G, 2 1GC"));
break;
case P_NEPTUNE_NONE:
default:
"ARTM card with 2 10G, 2 1GF"));
break;
}
} else {
"Unsupported neptune type 1"));
goto error_exit;
}
break;
case 1:
/* TODO - 2 10G, 1 1G */
"Unsupported neptune type 2 10G, 1 1G"));
goto error_exit;
case 0:
/*
* 2 10G: 2XGF NIC, Marvell, Goa, Huron with 2 XAUI
* cards, etc.
*/
if (((port_pcs_dev_id[0] == PHY_BCM8704_FAMILY) &&
((port_pma_pmd_dev_id[0] == PHY_BCM8704_FAMILY) &&
((port_pcs_dev_id[0] == MARVELL_88X201X_PHY_ID) &&
((port_pma_pmd_dev_id[0] ==
(port_pma_pmd_dev_id[1] ==
/*
* Check the first phy port address against
* the known phy start addresses to determine
* the platform type.
*/
switch (port_fd_arr[0]) {
/*
* The Marvell case also falls into
* this case as
* MRVL88X2011_NEPTUNE_PORT_ADDR_BASE
* == NEPTUNE_CLAUSE45_PORT_ADDR_BASE.
* This is OK for the 2 10G case.
*/
break;
if (hw_p->platform_type !=
}
break;
default:
"Unsupported neptune type 2 - 1"));
goto error_exit;
}
for (i = 0; i < 2; i++) {
}
/* Both XAUI slots have copper XAUI cards */
} else if ((((port_pcs_dev_id[0] & TN1010_DEV_ID_MASK)
== TN1010_DEV_ID) &&
== TN1010_DEV_ID)) ||
(((port_pma_pmd_dev_id[0] & TN1010_DEV_ID_MASK)
== TN1010_DEV_ID) &&
== TN1010_DEV_ID))) {
/* Slot0 has fiber XAUI, slot1 has copper XAUI */
} else if ((port_pcs_dev_id[0] == PHY_BCM8704_FAMILY &&
== TN1010_DEV_ID) ||
(port_pma_pmd_dev_id[0] == PHY_BCM8704_FAMILY &&
TN1010_DEV_ID)) {
/* Slot0 has copper XAUI, slot1 has fiber XAUI */
== TN1010_DEV_ID) ||
== TN1010_DEV_ID)) {
} else {
"Unsupported neptune type 2"));
goto error_exit;
}
break;
case 4:
if (nxge_get_num_of_xaui(
goto error_exit;
}
if (num_xaui != 2)
goto error_exit;
/*
* Maramba with 2 XAUIs (either fiber or copper)
*
* Check the first phy port address against
* the known phy start addresses to determine
* the platform type.
*/
switch (phy_fd_arr[0]) {
break;
break;
default:
"Unknown port %d...Cannot "
"determine platform type", i));
goto error_exit;
}
/* slot0 has fiber XAUI, slot1 has Cu XAUI */
if (port_pcs_dev_id[0] == PHY_BCM8704_FAMILY &&
== TN1010_DEV_ID) {
/* slot0 has Cu XAUI, slot1 has fiber XAUI */
} else if (((port_pcs_dev_id[0] & TN1010_DEV_ID_MASK)
== TN1010_DEV_ID) &&
/* Both slots have fiber XAUI */
} else if (port_pcs_dev_id[0] == PHY_BCM8704_FAMILY &&
/* Both slots have copper XAUI */
} else if (((port_pcs_dev_id[0] & TN1010_DEV_ID_MASK)
== TN1010_DEV_ID) &&
== TN1010_DEV_ID) {
} else {
"Unsupported neptune type 3"));
goto error_exit;
}
break;
default:
"Unsupported neptune type 5"));
goto error_exit;
}
break;
case 1: /* Only one clause45 port */
switch (total_phy_fd) { /* Number of clause22 ports */
case 3:
/*
* TODO 3 1G, 1 10G mode.
* Differentiate between 1_1G_1_10G_2_1G and
* 1_10G_3_1G
*/
"Unsupported neptune type 7"));
goto error_exit;
case 2:
/*
* TODO 2 1G, 1 10G mode.
* Differentiate between 1_1G_1_10G_1_1G and
* 1_10G_2_1G
*/
"Unsupported neptune type 8"));
goto error_exit;
case 1:
/*
* TODO 1 1G, 1 10G mode.
* Differentiate between 1_1G_1_10G and
* 1_10G_1_1G
*/
"Unsupported neptune type 9"));
goto error_exit;
case 0: /* N2 with 1 XAUI (fiber or copper) */
/* Fiber XAUI */
if (port_pcs_dev_id[0] == PHY_BCM8704_FAMILY ||
port_pma_pmd_dev_id[0] == PHY_BCM8704_FAMILY) {
/*
* Check the first phy port address against
* the known phy start addresses to determine
* the platform type.
*/
switch (port_fd_arr[0]) {
case (N2_CLAUSE45_PORT_ADDR_BASE + 1):
/*
* If hw_p->platform_type ==
* P_NEPTUNE_NIU, then portmode
* is already known, so there is
* no need to figure out hw_p->
* platform_type because
* platform_type is only for
* figuring out portmode.
*/
if (hw_p->platform_type !=
}
break;
default:
"Unsupported neptune type 10"));
goto error_exit;
}
/*
* For GOA, which is a hot swappable PHY, the
* phy address to function number mapping
* should be preserved, i.e., addr 16 is
* assigned to function 0 and 20 to function 1
* But for Huron XAUI, the assignment should
* be by function number, i.e., whichever
* function number attaches should be
* assigned the available PHY (this is required
* primarily to support pre-production Huron
* boards where function 0 is mapped to addr 17
*/
if (port_fd_arr[0] ==
} else {
port_fd_arr[0];
}
/* A 10G copper XAUI in either slot0 or slot1 */
} else if ((port_pcs_dev_id[0] & TN1010_DEV_ID_MASK)
== TN1010_DEV_ID ||
== TN1010_DEV_ID) {
switch (port_fd_arr[0]) {
/* The XAUI is in slot0 */
break;
/* The XAUI is in slot1 */
case (N2_CLAUSE45_PORT_ADDR_BASE + 1):
break;
default:
"Unsupported XAUI port address"));
goto error_exit;
}
= port_fd_arr[0];
} else {
"Unsupported PHY type"));
goto error_exit;
}
break;
case 4: /* Maramba always have 4 clause 45 ports */
/* Maramba with 1 XAUI */
if ((port_pcs_dev_id[0] != PHY_BCM8704_FAMILY) &&
(port_pma_pmd_dev_id[0] != PHY_BCM8704_FAMILY) &&
((port_pcs_dev_id[0] & TN1010_DEV_ID_MASK)
!= TN1010_DEV_ID) &&
!= TN1010_DEV_ID)) {
"Unsupported neptune type 12"));
goto error_exit;
}
/*
* Check the first phy port address against
* the known phy start addresses to determine
* the platform type.
*/
switch (phy_fd_arr[0]) {
break;
break;
default:
"Unknown port %d...Cannot "
"determine platform type 10 - 2",
i));
goto error_exit;
}
/*
* Check the clause45 address to determine
* if XAUI is in port 0 or port 1.
*/
switch (port_fd_arr[0]) {
if (port_pcs_dev_id[0]
== PHY_BCM8704_FAMILY ||
== PHY_BCM8704_FAMILY) {
} else {
}
for (i = 1; i < NXGE_MAX_PORTS; i++) {
phy_fd_arr[i];
}
break;
case (MARAMBA_CLAUSE45_PORT_ADDR_BASE + 1):
if (port_pcs_dev_id[0]
== PHY_BCM8704_FAMILY ||
== PHY_BCM8704_FAMILY) {
} else {
}
break;
default:
"Unsupported neptune type 11"));
goto error_exit;
}
"Maramba with 1 XAUI (fiber or copper)"));
break;
default:
"Unsupported neptune type 13"));
goto error_exit;
}
break;
case 0: /* 4 ports Neptune based NIC */
switch (total_phy_fd) {
case 4:
if ((port_phy_id[0] == PHY_BCM5464R_FAMILY) &&
/*
* Check the first phy port address against
* the known phy start addresses to determine
* the platform type.
*/
switch (phy_fd_arr[0]) {
break;
break;
default:
"Unknown port %d...Cannot "
"determine platform type", i));
goto error_exit;
}
for (i = 0; i < NXGE_MAX_PORTS; i++) {
}
} else {
"Unsupported neptune type 14"));
goto error_exit;
}
break;
case 3:
/* TODO 3 1G mode */
"Unsupported neptune type 15"));
goto error_exit;
case 2:
/* TODO 2 1G mode */
if ((port_phy_id[0] == PHY_BCM5482_FAMILY) &&
} else {
"Unsupported neptune type 16"));
goto error_exit;
}
"2 RGMII Fiber ports - RTM"));
break;
case 1:
/* TODO 1 1G mode */
"Unsupported neptune type 17"));
goto error_exit;
default:
"Unsupported neptune type 18, total phy fd %d",
total_phy_fd));
goto error_exit;
}
break;
default:
"Unsupported neptune type 19"));
goto error_exit;
}
return (status);
return (NXGE_ERROR);
}
{
return (B_FALSE);
else
return (B_TRUE);
}
static void
}
/*
* For Altas 4-1G copper, Xcvr port numbers are
* swapped with ethernet port number. This is
* designed for better signal integrity in routing.
*/
switch (portn) {
case 0:
xcvr_portn += 3;
break;
case 1:
xcvr_portn += 2;
break;
case 2:
xcvr_portn += 1;
break;
case 3:
default:
break;
}
if (rs != NPI_SUCCESS) {
"<== nxge_bcm5464_link_led_off: npi_mac_mif_mii_write "
"returned error 0x[%x]", rs));
return;
}
if (rs != NPI_SUCCESS) {
"<== nxge_bcm5464_link_led_off: npi_mac_mif_mii_write "
"returned error 0x[%x]", rs));
}
}
static nxge_status_t
{
#if defined(__i386)
goto fail;
#else
goto fail;
#endif
}
#if defined(__i386)
goto fail;
}
#else
goto fail;
}
#endif
"nxge_mii_get_link_mode: fiber mode"));
}
"nxge_mii_get_link_mode: "
"(address 0x%x) port 0x%x mode value 0x%x link mode 0x%x",
"<== nxge_mii_get_link_mode"));
return (status);
fail:
"<== nxge_mii_get_link_mode (failed)"));
return (NXGE_ERROR);
}
{
"==> nxge_mac_sec_framesize: port<%d> "
"min framesize %d max framesize %d ",
rs);
if (rs != NPI_SUCCESS) {
"<== nxge_mac_set_framesize: failed to configure "
return (NXGE_ERROR | rs);
}
"<== nxge_mac_set_framesize: port<%d>", portn));
return (NXGE_OK);
}
static nxge_status_t
{
uint8_t i;
for (i = 0; i < 4; i++) {
if (port_phy_id[i] != PHY_BCM5464R_FAMILY)
return (NXGE_ERROR);
}
*num_xaui = 0;
if ((port_pma_pmd_dev_id[0] == PHY_BCM8704_FAMILY &&
port_pcs_dev_id[0] == PHY_BCM8704_FAMILY) ||
(((port_pma_pmd_dev_id[0] & TN1010_DEV_ID_MASK)
== TN1010_DEV_ID) &&
((port_pcs_dev_id[0] & TN1010_DEV_ID_MASK)
== TN1010_DEV_ID))) {
(*num_xaui) ++;
}
== TN1010_DEV_ID) &&
== TN1010_DEV_ID))) {
(*num_xaui) ++;
}
return (NXGE_OK);
}
/*
* Instruction from Teranetics: Once you detect link is up, go
* read Reg 30.1.4 for link speed: '1' for 1G and '0' for 10G. You
* may want to qualify it by first checking Register 30.1.7:6 and
* making sure it reads "01" (Auto-Neg Complete).
*
* If this function is called when the link is down or before auto-
* negotiation has completed, then the speed of the PHY is not certain.
* In such cases, this function returns 1G as the default speed with
* NXGE_OK status instead of NXGE_ERROR. It is OK to initialize the
* driver based on a default speed because this function will be called
* again when the link comes up. Returning NXGE_ERROR, which may
* cause brutal chain reaction in caller functions, is not necessary.
*/
static nxge_status_t
{
/* Set default speed to 10G */
/* Set Clause 45 */
/* Check Device 1 Register 0xA bit0 for link up status */
goto fail;
"nxge_get_tn1010_speed: link is down"));
}
goto fail;
}
/*
* Return NXGE_OK even when we can not get a settled speed. In
* such case, the speed reported should not be trusted but that
* is OK, we will call this function periodically and will get
* the correct speed after the link is up.
*/
switch (autoneg_stat) {
case TN1010_AN_IN_PROG:
"nxge_get_tn1010_speed: Auto-negotiation in progress"));
break;
case TN1010_AN_COMPLETE:
goto fail;
}
break;
case TN1010_AN_RSVD:
"nxge_get_tn1010_speed: Autoneg status undefined"));
break;
case TN1010_AN_FAILED:
"nxge_get_tn1010_speed: Auto-negotiation failed"));
break;
default:
break;
}
return (NXGE_OK);
fail:
return (status);
}
/*
* Teranetics TN1010 PHY chip supports both 1G and 10G modes, this function
* figures out the speed of the PHY determined by the autonegotiation
* process and sets the following 3 parameters,
* nxgep->mac.portmode
* nxgep->statsp->mac_stats.link_speed
* nxgep->statsp->mac_stats.xcvr_inuse
*/
static nxge_status_t
{
"nxge_set_tn1010_param: "
"Failed to get TN1010 speed"));
return (NXGE_ERROR);
}
if (speed == TN1010_SPEED_1G) {
} else {
}
return (NXGE_OK);
}
#ifdef NXGE_DEBUG
static void
{
#if defined(__i386)
#else
#endif
"nxge_mii_dump: bmcr (0) xcvr 0x%x value 0x%x",
#if defined(__i386)
(void) nxge_mii_read(nxgep,
#else
(void) nxge_mii_read(nxgep,
#endif
"nxge_mii_dump: bmsr (1) xcvr 0x%x value 0x%x",
#if defined(__i386)
(void) nxge_mii_read(nxgep,
#else
(void) nxge_mii_read(nxgep,
#endif
#if defined(__i386)
(void) nxge_mii_read(nxgep,
#else
(void) nxge_mii_read(nxgep,
#endif
"nxge_mii_dump: idr1 (2) xcvr 0x%x value 0x%x",
"nxge_mii_dump: idr2 (3) xcvr 0x%x value 0x%x",
#if defined(__i386)
#else
#endif
"nxge_mii_dump: mode control xcvr 0x%x value 0x%x",
}
#endif