npi_zcp.c revision 6f45ec7b0b964c3be967c4880e8867ac1e7763a5
/*
* CDDL HEADER START
*
* The contents of this file are subject to the terms of the
* Common Development and Distribution License (the "License").
* You may not use this file except in compliance with the License.
*
* You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
* See the License for the specific language governing permissions
* and limitations under the License.
*
* When distributing Covered Code, include this CDDL HEADER in each
* file and include the License file at usr/src/OPENSOLARIS.LICENSE.
* If applicable, add the following below this CDDL HEADER, with the
* fields enclosed by brackets "[]" replaced with your own identifying
* information: Portions Copyright [yyyy] [name of copyright owner]
*
* CDDL HEADER END
*/
/*
* Copyright 2007 Sun Microsystems, Inc. All rights reserved.
* Use is subject to license terms.
*/
#pragma ident "%Z%%M% %I% %E% SMI"
#include <npi_zcp.h>
uint16_t, zcp_ram_unit_t *);
{
switch (op) {
case ENABLE:
case DISABLE:
" npi_zcp_config"
" Invalid Input: config <0x%x>",
config));
return (NPI_FAILURE | NPI_ZCP_CONFIG_INVALID);
}
if (config & CFG_ZCP_ECC_CHK)
val &= ~ECC_CHK_DIS;
if (config & CFG_ZCP_PAR_CHK)
val &= ~PAR_CHK_DIS;
if (config & CFG_ZCP_BUF_RESP)
val &= ~DIS_BUFF_RN;
if (config & CFG_ZCP_BUF_REQ)
val &= ~DIS_BUFF_RQ_IF;
} else {
if (config & CFG_ZCP_ECC_CHK)
val |= ECC_CHK_DIS;
if (config & CFG_ZCP_PAR_CHK)
val |= PAR_CHK_DIS;
if (config & CFG_ZCP_BUF_RESP)
val |= DIS_BUFF_RN;
if (config & CFG_ZCP_BUF_REQ)
val |= DIS_BUFF_RQ_IF;
}
break;
case INIT:
else
if (config & CFG_ZCP_ECC_CHK)
val &= ~ECC_CHK_DIS;
else
val |= ECC_CHK_DIS;
if (config & CFG_ZCP_PAR_CHK)
val &= ~PAR_CHK_DIS;
else
val |= PAR_CHK_DIS;
if (config & CFG_ZCP_BUF_RESP)
val &= ~DIS_BUFF_RN;
else
val |= DIS_BUFF_RN;
if (config & CFG_ZCP_BUF_REQ)
val &= DIS_BUFF_RQ_IF;
else
val |= DIS_BUFF_RQ_IF;
break;
default:
" npi_zcp_config"
" Invalid Input: config <0x%x>",
config));
return (NPI_FAILURE | NPI_ZCP_OPCODE_INVALID);
}
return (NPI_SUCCESS);
}
{
switch (op) {
case ENABLE:
case DISABLE:
" npi_zcp_iconfig"
" Invalid Input: iconfig <0x%x>",
iconfig));
return (NPI_FAILURE | NPI_ZCP_CONFIG_INVALID);
}
else
break;
case INIT:
if ((iconfig & ~ICFG_ZCP_ALL) != 0) {
" npi_zcp_iconfig"
" Invalid Input: iconfig <0x%x>",
iconfig));
return (NPI_FAILURE | NPI_ZCP_CONFIG_INVALID);
}
break;
default:
" npi_zcp_iconfig"
" Invalid Input: iconfig <0x%x>",
iconfig));
return (NPI_FAILURE | NPI_ZCP_OPCODE_INVALID);
}
return (NPI_SUCCESS);
}
{
return (NPI_SUCCESS);
}
{
return (NPI_SUCCESS);
}
{
if ((dma_thres & ~RDMA_TH_BITS) != 0) {
" npi_zcp_set_dma_thresh"
" Invalid Input: dma_thres <0x%x>",
dma_thres));
return (NPI_FAILURE | NPI_ZCP_DMA_THRES_INVALID);
}
val &= ~RDMA_TH_MASK;
return (NPI_SUCCESS);
}
{
if (!IS_VALID_BAM_REGION(region)) {
" npi_zcp_set_bam_region"
" Invalid Input: region <0x%x>",
region));
return (NPI_FAILURE | ZCP_BAM_REGION_INVALID);
}
switch (region) {
case BAM_4BUF:
break;
case BAM_8BUF:
break;
case BAM_16BUF:
break;
case BAM_32BUF:
break;
}
return (NPI_SUCCESS);
}
{
if (!IS_VALID_BAM_REGION(region)) {
" npi_zcp_set_dst_region"
" Invalid Input: region <0x%x>",
region));
return (NPI_FAILURE | NPI_ZCP_BAM_REGION_INVALID);
}
if ((row_idx & ~0x3FF) != 0) {
" npi_zcp_set_dst_region"
" Invalid Input: row_idx", row_idx));
return (NPI_FAILURE | NPI_ZCP_ROW_INDEX_INVALID);
}
switch (region) {
case BAM_4BUF:
break;
case BAM_8BUF:
break;
case BAM_16BUF:
break;
case BAM_32BUF:
break;
}
return (NPI_SUCCESS);
}
{
" npi_zcp_tt_static_entry"
" Invalid Input: op <0x%x>",
op));
return (NPI_FAILURE | NPI_ZCP_OPCODE_INVALID);
}
if ((mask & TTE_SFLOW_ATTR_ALL) == 0) {
" npi_zcp_tt_static_entry"
" Invalid Input: mask <0x%x>",
mask));
return (NPI_FAILURE | NPI_ZCP_SFLOW_ATTR_INVALID);
}
if ((flow_id & ~0x0FFF) != 0) {
" npi_zcp_tt_static_entry"
" Invalid Input: flow_id<0x%x>",
flow_id));
return (NPI_FAILURE | NPI_ZCP_FLOW_ID_INVALID);
}
(zcp_ram_unit_t *)&val) != 0) {
" npi_zcp_tt_static_entry"
" HW Error: ZCP_RAM_ACC <0x%x>",
NULL));
return (NPI_FAILURE | NPI_ZCP_MEM_READ_FAILED);
}
if (mask & TTE_RDC_TBL_OFF) {
}
if (mask & TTE_BUF_SIZE) {
}
if (mask & TTE_NUM_BUF) {
}
if (mask & TTE_ULP_END) {
}
if (mask & TTE_ULP_END) {
}
if (mask & TTE_ULP_END_EN) {
}
if (mask & TTE_UNMAP_ALL_EN) {
}
}
}
if (mask & TTE_HBM_RING_BASE_ADDR) {
}
if (mask & TTE_HBM_RING_BASE_ADDR) {
}
if (mask & TTE_HBM_RING_SIZE) {
}
if (mask & TTE_HBM_BUSY) {
}
if (mask & TTE_HBM_TOQ) {
}
(zcp_ram_unit_t *)&val) != 0) {
" npi_zcp_tt_static_entry"
" HW Error: ZCP_RAM_ACC <0x%x>",
NULL));
return (NPI_FAILURE | NPI_ZCP_MEM_WRITE_FAILED);
}
} else {
}
return (NPI_SUCCESS);
}
{
" npi_zcp_tt_dynamic_entry"
" Invalid Input: op <0x%x>", op));
return (NPI_FAILURE | NPI_ZCP_OPCODE_INVALID);
}
if ((mask & TTE_DFLOW_ATTR_ALL) == 0) {
" npi_zcp_tt_dynamic_entry"
" Invalid Input: mask <0x%x>",
mask));
return (NPI_FAILURE | NPI_ZCP_DFLOW_ATTR_INVALID);
}
if ((flow_id & ~0x0FFF) != 0) {
" npi_zcp_tt_dynamic_entry"
" Invalid Input: flow_id <0x%x>",
flow_id));
return (NPI_FAILURE | NPI_ZCP_FLOW_ID_INVALID);
}
(zcp_ram_unit_t *)&val) != 0) {
" npi_zcp_tt_dynamic_entry"
" HW Error: ZCP_RAM_ACC <0x%x>",
NULL));
return (NPI_FAILURE | NPI_ZCP_MEM_READ_FAILED);
}
/* Get data read */
if (mask & TTE_MAPPED_IN) {
}
if (mask & TTE_ANCHOR_SEQ) {
}
if (mask & TTE_ANCHOR_OFFSET) {
}
if (mask & TTE_ANCHOR_BUFFER) {
}
if (mask & TTE_ANCHOR_BUF_FLAG) {
}
if (mask & TTE_UNMAP_ON_LEFT) {
}
if (mask & TTE_ULP_END_REACHED) {
}
if (mask & TTE_ERR_STAT) {
}
if (mask & TTE_HBM_WR_PTR) {
}
if (mask & TTE_HBM_HOQ) {
}
if (mask & TTE_HBM_PREFETCH_ON) {
}
(zcp_ram_unit_t *)&val) != 0) {
" npi_zcp_tt_dynamic_entry"
" HW Error: ZCP_RAM_ACC <0x%x>",
NULL));
return (NPI_FAILURE | NPI_ZCP_MEM_WRITE_FAILED);
}
} else {
}
return (NPI_SUCCESS);
}
{
" npi_zcp_tt_bam_entry"
" Invalid Input: op <0x%x>", op));
return (NPI_FAILURE | NPI_ZCP_OPCODE_INVALID);
}
if ((flow_id & ~0x0FFF) != 0) {
" npi_zcp_tt_dynamic_entry"
" Invalid Input: flow_id <0x%x>",
flow_id));
return (NPI_FAILURE | NPI_ZCP_FLOW_ID_INVALID);
}
if (bankn >= MAX_BAM_BANKS) {
" npi_zcp_tt_bam_entry"
" Invalid Input: bankn <0x%x>",
bankn));
return (NPI_FAILURE | NPI_ZCP_BAM_BANK_INVALID);
}
if ((word_en & ~0xF) != 0) {
" npi_zcp_tt_bam_entry"
" Invalid Input: word_en <0x%x>",
word_en));
return (NPI_FAILURE | NPI_ZCP_BAM_WORD_EN_INVALID);
}
(zcp_ram_unit_t *)&val) != 0) {
" npi_zcp_tt_bam_entry"
" HW Error: ZCP_RAM_ACC <0x%x>",
NULL));
return (NPI_FAILURE | NPI_ZCP_MEM_READ_FAILED);
}
(zcp_ram_unit_t *)&val) != 0) {
" npi_zcp_tt_bam_entry"
" HW Error: ZCP_RAM_ACC <0x%x>",
NULL));
return (NPI_FAILURE | NPI_ZCP_MEM_WRITE_FAILED);
}
} else {
}
return (NPI_SUCCESS);
}
{
" npi_zcp_tt_cfifo_entry"
" Invalid Input: op <0x%x>", op));
return (NPI_FAILURE | NPI_ZCP_OPCODE_INVALID);
}
if (portn > 3) {
" npi_zcp_tt_cfifo_entry"
" Invalid Input: portn <%d>", portn));
}
" npi_zcp_tt_cfifo_entry"
" HW Error: ZCP_RAM_ACC <0x%x>",
NULL));
return (NPI_FAILURE | NPI_ZCP_MEM_WRITE_FAILED);
}
} else {
" npi_zcp_tt_cfifo_entry"
" HW Error: ZCP_RAM_ACC <0x%x>",
NULL));
return (NPI_FAILURE | NPI_ZCP_MEM_READ_FAILED);
}
}
return (NPI_SUCCESS);
}
{
switch (port) {
case 0:
break;
case 1:
break;
case 2:
break;
case 3:
break;
default:
break;
}
return (NPI_SUCCESS);
}
{
return (NPI_SUCCESS);
}
static int
{
/* Wait for RAM ready to be read */
" npi_zcp_tt_static_entry"
" HW Error: ZCP_RAM_ACC <0x%x>",
return (-1);
}
/* Read from RAM */
/* Wait for RAM read done */
return (-1);
/* Get data */
return (0);
}
static int
{
/* Setup data */
/* Set byte mask */
/* Write to RAM */
/* Wait for RAM write complete */
return (-1);
return (0);
}