npi_rxdma.h revision 4df55fde49134f9735f84011f23a767c75e393c7
fa9e4066f08beec538e775443c5be79dd423fcabahrens * CDDL HEADER START
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f48205be61a214698b763ff550ab9e657525104ccasper * Common Development and Distribution License (the "License").
f48205be61a214698b763ff550ab9e657525104ccasper * You may not use this file except in compliance with the License.
fa9e4066f08beec538e775443c5be79dd423fcabahrens * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
fa9e4066f08beec538e775443c5be79dd423fcabahrens * See the License for the specific language governing permissions
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fa9e4066f08beec538e775443c5be79dd423fcabahrens * information: Portions Copyright [yyyy] [name of copyright owner]
fa9e4066f08beec538e775443c5be79dd423fcabahrens * CDDL HEADER END
27dd1e87cd3d939264769dd4af7e6a529cde001fMark Shellenbaum * Copyright 2009 Sun Microsystems, Inc. All rights reserved.
1eb4e906ec75b9bde421954ace46ef137b0fc9ebKevin Crowe * Use is subject to license terms.
fa9e4066f08beec538e775443c5be79dd423fcabahrens * Register offset (0x200 bytes for each channel) for receive ring registers.
fa9e4066f08beec538e775443c5be79dd423fcabahrens#define REG_FZC_RDC_OFFSET(reg, rdc) (reg + RX_LOG_DMA_OFFSET(rdc))
da6c28aaf62fa55f0fdb8004aa40f88f23bf53f0amw * RX NPI error codes
da6c28aaf62fa55f0fdb8004aa40f88f23bf53f0amw#define NPI_RXDMA_SW_PARAM_ERROR (NPI_RXDMA_ERROR | 0x40)
da6c28aaf62fa55f0fdb8004aa40f88f23bf53f0amw#define NPI_RXDMA_RDC_INVALID (NPI_RXDMA_ERROR | CHANNEL_INVALID)
da6c28aaf62fa55f0fdb8004aa40f88f23bf53f0amw#define NPI_RXDMA_PAGE_INVALID (NPI_RXDMA_ERROR | LOGICAL_PAGE_INVALID)
da6c28aaf62fa55f0fdb8004aa40f88f23bf53f0amw#define NPI_RXDMA_RESET_ERR (NPI_RXDMA_HW_ERROR | RESET_FAILED)
da6c28aaf62fa55f0fdb8004aa40f88f23bf53f0amw#define NPI_RXDMA_DISABLE_ERR (NPI_RXDMA_HW_ERROR | 0x0000a)
da6c28aaf62fa55f0fdb8004aa40f88f23bf53f0amw#define NPI_RXDMA_ENABLE_ERR (NPI_RXDMA_HW_ERROR | 0x0000b)
da6c28aaf62fa55f0fdb8004aa40f88f23bf53f0amw#define NPI_RXDMA_FUNC_INVALID (NPI_RXDMA_SW_PARAM_ERROR | 0x0000a)
da6c28aaf62fa55f0fdb8004aa40f88f23bf53f0amw#define NPI_RXDMA_BUFSIZE_INVALID (NPI_RXDMA_SW_PARAM_ERROR | 0x0000b)
da6c28aaf62fa55f0fdb8004aa40f88f23bf53f0amw#define NPI_RXDMA_RBRSIZE_INVALID (NPI_RXDMA_SW_PARAM_ERROR | 0x0000c)
da6c28aaf62fa55f0fdb8004aa40f88f23bf53f0amw#define NPI_RXDMA_RCRSIZE_INVALID (NPI_RXDMA_SW_PARAM_ERROR | 0x0000d)
da6c28aaf62fa55f0fdb8004aa40f88f23bf53f0amw#define NPI_RXDMA_PORT_INVALID (NPI_RXDMA_ERROR | PORT_INVALID)
da6c28aaf62fa55f0fdb8004aa40f88f23bf53f0amw#define NPI_RXDMA_TABLE_INVALID (NPI_RXDMA_ERROR | RDC_TAB_INVALID)
da6c28aaf62fa55f0fdb8004aa40f88f23bf53f0amw#define NPI_RXDMA_CHANNEL_INVALID(n) (RXDMA_ID_SHIFT(n) | \
da6c28aaf62fa55f0fdb8004aa40f88f23bf53f0amw#define NPI_RXDMA_OPCODE_INVALID(n) (RXDMA_ID_SHIFT(n) | \
da6c28aaf62fa55f0fdb8004aa40f88f23bf53f0amw#define RXDMA_RCR_THRESH_VALID(thresh) ((thresh) && (thresh < 512))
da6c28aaf62fa55f0fdb8004aa40f88f23bf53f0amw * RXDMA NPI defined control types.
da6c28aaf62fa55f0fdb8004aa40f88f23bf53f0amwtypedef enum _rxdma_cs_cntl_e {
da6c28aaf62fa55f0fdb8004aa40f88f23bf53f0amw * RXDMA NPI defined event masks (mapped to the hardware defined masks).
da6c28aaf62fa55f0fdb8004aa40f88f23bf53f0amw CFG_RXDMA_ENT_MSK_CFIGLOGPGE_MASK = RX_DMA_ENT_MSK_CFIGLOGPGE_MASK,
da6c28aaf62fa55f0fdb8004aa40f88f23bf53f0amw CFG_RXDMA_ENT_MSK_RBRLOGPGE_MASK = RX_DMA_ENT_MSK_RBRLOGPGE_MASK,
da6c28aaf62fa55f0fdb8004aa40f88f23bf53f0amw CFG_RXDMA_ENT_MSK_RBRFULL_MASK = RX_DMA_ENT_MSK_RBRFULL_MASK,
da6c28aaf62fa55f0fdb8004aa40f88f23bf53f0amw CFG_RXDMA_ENT_MSK_RBREMPTY_MASK = RX_DMA_ENT_MSK_RBREMPTY_MASK,
da6c28aaf62fa55f0fdb8004aa40f88f23bf53f0amw CFG_RXDMA_ENT_MSK_RCRFULL_MASK = RX_DMA_ENT_MSK_RCRFULL_MASK,
da6c28aaf62fa55f0fdb8004aa40f88f23bf53f0amw CFG_RXDMA_ENT_MSK_RCRINCON_MASK = RX_DMA_ENT_MSK_RCRINCON_MASK,
da6c28aaf62fa55f0fdb8004aa40f88f23bf53f0amw CFG_RXDMA_ENT_MSK_CONFIG_ERR = RX_DMA_ENT_MSK_CONFIG_ERR_MASK,
da6c28aaf62fa55f0fdb8004aa40f88f23bf53f0amw CFG_RXDMA_ENT_MSK_RCR_SH_FULL_MASK = RX_DMA_ENT_MSK_RCRSH_FULL_MASK,
da6c28aaf62fa55f0fdb8004aa40f88f23bf53f0amw CFG_RXDMA_ENT_MSK_RBR_PRE_EMTY_MASK = RX_DMA_ENT_MSK_RBR_PRE_EMPTY_MASK,
da6c28aaf62fa55f0fdb8004aa40f88f23bf53f0amw CFG_RXDMA_ENT_MSK_WRED_DROP_MASK = RX_DMA_ENT_MSK_WRED_DROP_MASK,
da6c28aaf62fa55f0fdb8004aa40f88f23bf53f0amw CFG_RXDMA_ENT_MSK_PT_DROP_PKT_MASK = RX_DMA_ENT_MSK_PTDROP_PKT_MASK,
da6c28aaf62fa55f0fdb8004aa40f88f23bf53f0amw CFG_RXDMA_ENT_MSK_RBR_PRE_PAR_MASK = RX_DMA_ENT_MSK_RBR_PRE_PAR_MASK,
da6c28aaf62fa55f0fdb8004aa40f88f23bf53f0amw CFG_RXDMA_ENT_MSK_RCR_SHA_PAR_MASK = RX_DMA_ENT_MSK_RCR_SHA_PAR_MASK,
da6c28aaf62fa55f0fdb8004aa40f88f23bf53f0amw CFG_RXDMA_ENT_MSK_RCRTO_MASK = RX_DMA_ENT_MSK_RCRTO_MASK,
da6c28aaf62fa55f0fdb8004aa40f88f23bf53f0amw CFG_RXDMA_ENT_MSK_THRES_MASK = RX_DMA_ENT_MSK_THRES_MASK,
fa9e4066f08beec538e775443c5be79dd423fcabahrens CFG_RXDMA_ENT_MSK_DC_FIFO_ERR_MASK = RX_DMA_ENT_MSK_DC_FIFO_ERR_MASK,
fa9e4066f08beec538e775443c5be79dd423fcabahrens CFG_RXDMA_ENT_MSK_RCR_ACK_ERR_MASK = RX_DMA_ENT_MSK_RCR_ACK_ERR_MASK,
fa9e4066f08beec538e775443c5be79dd423fcabahrens CFG_RXDMA_ENT_MSK_RSP_DAT_ERR_MASK = RX_DMA_ENT_MSK_RSP_DAT_ERR_MASK,
fa9e4066f08beec538e775443c5be79dd423fcabahrens CFG_RXDMA_ENT_MSK_BYTE_EN_BUS_MASK = RX_DMA_ENT_MSK_BYTE_EN_BUS_MASK,
fa9e4066f08beec538e775443c5be79dd423fcabahrens CFG_RXDMA_ENT_MSK_RSP_CNT_ERR_MASK = RX_DMA_ENT_MSK_RSP_CNT_ERR_MASK,
fa9e4066f08beec538e775443c5be79dd423fcabahrens CFG_RXDMA_ENT_MSK_RBR_TMOUT_MASK = RX_DMA_ENT_MSK_RBR_TMOUT_MASK,
fa9e4066f08beec538e775443c5be79dd423fcabahrens CFG_RXDMA_MASK_ALL = (RX_DMA_ENT_MSK_CFIGLOGPGE_MASK |
fa9e4066f08beec538e775443c5be79dd423fcabahrenstypedef union _addr44 {
fa9e4066f08beec538e775443c5be79dd423fcabahrens * npi_rxdma_cfg_default_port_rdc()
fa9e4066f08beec538e775443c5be79dd423fcabahrens * Set the default rdc for the port
fa9e4066f08beec538e775443c5be79dd423fcabahrens * handle: register handle interpreted by the underlying OS
fa9e4066f08beec538e775443c5be79dd423fcabahrens * portnm: Physical Port Number
fa9e4066f08beec538e775443c5be79dd423fcabahrens * rdc: RX DMA Channel number
fa9e4066f08beec538e775443c5be79dd423fcabahrens * NPI_SUCCESS
fa9e4066f08beec538e775443c5be79dd423fcabahrens * NPI_RXDMA_RDC_INVALID
fa9e4066f08beec538e775443c5be79dd423fcabahrens * NPI_RXDMA_PORT_INVALID
fa9e4066f08beec538e775443c5be79dd423fcabahrensnpi_status_t npi_rxdma_cfg_default_port_rdc(npi_handle_t,
fa9e4066f08beec538e775443c5be79dd423fcabahrens * npi_rxdma_rdc_table_config
fa9e4066f08beec538e775443c5be79dd423fcabahrens * Configure/populate the RDC table
da6c28aaf62fa55f0fdb8004aa40f88f23bf53f0amw * handle: register handle interpreted by the underlying OS
da6c28aaf62fa55f0fdb8004aa40f88f23bf53f0amw * table: RDC Group Number
da6c28aaf62fa55f0fdb8004aa40f88f23bf53f0amw * map: Bitmap of RDCs to be written to <table>.
b819cea2f73f98c5662230cc9affc8cc84f77fcfGordon Ross * count: A count of the number of bits in <map>.
da6c28aaf62fa55f0fdb8004aa40f88f23bf53f0amw * NPI_SUCCESS
da6c28aaf62fa55f0fdb8004aa40f88f23bf53f0amw * NPI_RXDMA_TABLE_INVALID
da6c28aaf62fa55f0fdb8004aa40f88f23bf53f0amwnpi_status_t npi_rxdma_rdc_table_config(npi_handle_t, uint8_t, dc_map_t,
da6c28aaf62fa55f0fdb8004aa40f88f23bf53f0amwnpi_status_t npi_rxdma_cfg_rdc_table_default_rdc(npi_handle_t,
da6c28aaf62fa55f0fdb8004aa40f88f23bf53f0amwnpi_status_t npi_rxdma_cfg_rdc_rcr_timeout_disable(npi_handle_t,
da6c28aaf62fa55f0fdb8004aa40f88f23bf53f0amw * npi_rxdma_32bitmode_enable()
da6c28aaf62fa55f0fdb8004aa40f88f23bf53f0amw * Enable 32 bit mode
da6c28aaf62fa55f0fdb8004aa40f88f23bf53f0amw * handle: register handle interpreted by the underlying OS
da6c28aaf62fa55f0fdb8004aa40f88f23bf53f0amw * NPI_SUCCESS
da6c28aaf62fa55f0fdb8004aa40f88f23bf53f0amw * NPI_FAILURE
da6c28aaf62fa55f0fdb8004aa40f88f23bf53f0amw * NPI_HW_ERR
b819cea2f73f98c5662230cc9affc8cc84f77fcfGordon Rossnpi_status_t npi_rxdma_cfg_32bitmode_enable(npi_handle_t);
da6c28aaf62fa55f0fdb8004aa40f88f23bf53f0amw * npi_rxdma_32bitmode_disable()
da6c28aaf62fa55f0fdb8004aa40f88f23bf53f0amw * disable 32 bit mode
da6c28aaf62fa55f0fdb8004aa40f88f23bf53f0amw * handle: register handle interpreted by the underlying OS
da6c28aaf62fa55f0fdb8004aa40f88f23bf53f0amw * NPI_SUCCESS
da6c28aaf62fa55f0fdb8004aa40f88f23bf53f0amw * NPI_FAILURE
da6c28aaf62fa55f0fdb8004aa40f88f23bf53f0amw * NPI_HW_ERR
da6c28aaf62fa55f0fdb8004aa40f88f23bf53f0amwnpi_status_t npi_rxdma_cfg_32bitmode_disable(npi_handle_t);
da6c28aaf62fa55f0fdb8004aa40f88f23bf53f0amw * npi_rxdma_cfg_ram_access_enable()
da6c28aaf62fa55f0fdb8004aa40f88f23bf53f0amw * Enable PIO access to shadow and prefetch memory.
da6c28aaf62fa55f0fdb8004aa40f88f23bf53f0amw * In the case of DMA errors, software may need to
da6c28aaf62fa55f0fdb8004aa40f88f23bf53f0amw * initialize the shadow and prefetch memories to
da6c28aaf62fa55f0fdb8004aa40f88f23bf53f0amw * sane value (may be clear it) before re-enabling
da6c28aaf62fa55f0fdb8004aa40f88f23bf53f0amw * the DMA channel.
da6c28aaf62fa55f0fdb8004aa40f88f23bf53f0amw * handle: register handle interpreted by the underlying OS
da6c28aaf62fa55f0fdb8004aa40f88f23bf53f0amw * NPI_SUCCESS
da6c28aaf62fa55f0fdb8004aa40f88f23bf53f0amw * NPI_FAILURE
da6c28aaf62fa55f0fdb8004aa40f88f23bf53f0amw * NPI_HW_ERR
da6c28aaf62fa55f0fdb8004aa40f88f23bf53f0amwnpi_status_t npi_rxdma_cfg_ram_access_enable(npi_handle_t);
da6c28aaf62fa55f0fdb8004aa40f88f23bf53f0amw * npi_rxdma_cfg_ram_access_disable()
da6c28aaf62fa55f0fdb8004aa40f88f23bf53f0amw * Disable PIO access to shadow and prefetch memory.
da6c28aaf62fa55f0fdb8004aa40f88f23bf53f0amw * This is the normal operation mode.
da6c28aaf62fa55f0fdb8004aa40f88f23bf53f0amw * handle: register handle interpreted by the underlying OS
da6c28aaf62fa55f0fdb8004aa40f88f23bf53f0amw * NPI_SUCCESS
da6c28aaf62fa55f0fdb8004aa40f88f23bf53f0amw * NPI_FAILURE
da6c28aaf62fa55f0fdb8004aa40f88f23bf53f0amw * NPI_HW_ERR
da6c28aaf62fa55f0fdb8004aa40f88f23bf53f0amwnpi_status_t npi_rxdma_cfg_ram_access_disable(npi_handle_t);
da6c28aaf62fa55f0fdb8004aa40f88f23bf53f0amw * npi_rxdma_cfg_clock_div_set()
da6c28aaf62fa55f0fdb8004aa40f88f23bf53f0amw * init the clock division, used for RX timers
da6c28aaf62fa55f0fdb8004aa40f88f23bf53f0amw * This determines the granularity of RX DMA countdown timers
da6c28aaf62fa55f0fdb8004aa40f88f23bf53f0amw * It depends on the system clock. For example if the system
da6c28aaf62fa55f0fdb8004aa40f88f23bf53f0amw * clock is 300 MHz, a value of 30000 will yield a granularity
da6c28aaf62fa55f0fdb8004aa40f88f23bf53f0amw * of 100usec.
da6c28aaf62fa55f0fdb8004aa40f88f23bf53f0amw * handle: register handle interpreted by the underlying OS
da6c28aaf62fa55f0fdb8004aa40f88f23bf53f0amw * count: System clock divider
da6c28aaf62fa55f0fdb8004aa40f88f23bf53f0amw * NPI_SUCCESS
da6c28aaf62fa55f0fdb8004aa40f88f23bf53f0amw * NPI_FAILURE
da6c28aaf62fa55f0fdb8004aa40f88f23bf53f0amw * NPI_SW_ERR
da6c28aaf62fa55f0fdb8004aa40f88f23bf53f0amw * NPI_HW_ERR
da6c28aaf62fa55f0fdb8004aa40f88f23bf53f0amwnpi_status_t npi_rxdma_cfg_clock_div_set(npi_handle_t, uint16_t);
da6c28aaf62fa55f0fdb8004aa40f88f23bf53f0amw * npi_rxdma_cfg_red_rand_init()
da6c28aaf62fa55f0fdb8004aa40f88f23bf53f0amw * init the WRED Discard
da6c28aaf62fa55f0fdb8004aa40f88f23bf53f0amw * By default, it is enabled
da6c28aaf62fa55f0fdb8004aa40f88f23bf53f0amw * handle: register handle interpreted by the underlying OS
da6c28aaf62fa55f0fdb8004aa40f88f23bf53f0amw * init_value: WRED init value
da6c28aaf62fa55f0fdb8004aa40f88f23bf53f0amw * NPI_SUCCESS
da6c28aaf62fa55f0fdb8004aa40f88f23bf53f0amw * NPI_FAILURE
da6c28aaf62fa55f0fdb8004aa40f88f23bf53f0amw * NPI_SW_ERR
da6c28aaf62fa55f0fdb8004aa40f88f23bf53f0amw * NPI_HW_ERR
da6c28aaf62fa55f0fdb8004aa40f88f23bf53f0amwnpi_status_t npi_rxdma_cfg_red_rand_init(npi_handle_t, uint16_t);
da6c28aaf62fa55f0fdb8004aa40f88f23bf53f0amw * npi_rxdma_cfg_wred_disable()
da6c28aaf62fa55f0fdb8004aa40f88f23bf53f0amw * init the WRED Discard
da6c28aaf62fa55f0fdb8004aa40f88f23bf53f0amw * By default, it is enabled
da6c28aaf62fa55f0fdb8004aa40f88f23bf53f0amw * handle: register handle interpreted by the underlying OS
da6c28aaf62fa55f0fdb8004aa40f88f23bf53f0amw * NPI_SUCCESS
da6c28aaf62fa55f0fdb8004aa40f88f23bf53f0amw * NPI_FAILURE
da6c28aaf62fa55f0fdb8004aa40f88f23bf53f0amw * NPI_SW_ERR
da6c28aaf62fa55f0fdb8004aa40f88f23bf53f0amw * NPI_HW_ERR
da6c28aaf62fa55f0fdb8004aa40f88f23bf53f0amw * npi_rxdma_cfg_wred_param()
a3c49ce110f325a563c245bedc4d533adddb7211Albert Lee * COnfigure per rxdma channel WRED parameters
da6c28aaf62fa55f0fdb8004aa40f88f23bf53f0amw * By default, it is enabled
da6c28aaf62fa55f0fdb8004aa40f88f23bf53f0amw * handle: register handle interpreted by the underlying OS
da6c28aaf62fa55f0fdb8004aa40f88f23bf53f0amw * rdc: RX DMA Channel number
da6c28aaf62fa55f0fdb8004aa40f88f23bf53f0amw * wred_params: WRED configuration parameters
da6c28aaf62fa55f0fdb8004aa40f88f23bf53f0amw * NPI_SUCCESS
da6c28aaf62fa55f0fdb8004aa40f88f23bf53f0amw * NPI_FAILURE
da6c28aaf62fa55f0fdb8004aa40f88f23bf53f0amw * NPI_SW_ERR
da6c28aaf62fa55f0fdb8004aa40f88f23bf53f0amw * NPI_HW_ERR
da6c28aaf62fa55f0fdb8004aa40f88f23bf53f0amwnpi_status_t npi_rxdma_cfg_wred_param(npi_handle_t, uint8_t,
da6c28aaf62fa55f0fdb8004aa40f88f23bf53f0amw * npi_rxdma_port_ddr_weight
da6c28aaf62fa55f0fdb8004aa40f88f23bf53f0amw * Set the DDR weight for a port.
da6c28aaf62fa55f0fdb8004aa40f88f23bf53f0amw * handle: register handle interpreted by the underlying OS
da6c28aaf62fa55f0fdb8004aa40f88f23bf53f0amw * portnm: Physical Port Number
da6c28aaf62fa55f0fdb8004aa40f88f23bf53f0amw * weight: Port relative weight (in approx. bytes)
da6c28aaf62fa55f0fdb8004aa40f88f23bf53f0amw * Default values are:
da6c28aaf62fa55f0fdb8004aa40f88f23bf53f0amw * 0x400 (port 0 and 1) corresponding to 10 standard
da6c28aaf62fa55f0fdb8004aa40f88f23bf53f0amw * size (1500 bytes) Frames
da6c28aaf62fa55f0fdb8004aa40f88f23bf53f0amw * 0x66 (port 2 and 3) corresponding to 10% 10Gig ports
da6c28aaf62fa55f0fdb8004aa40f88f23bf53f0amw * NPI_SUCCESS
da6c28aaf62fa55f0fdb8004aa40f88f23bf53f0amw * NPI_FAILURE
da6c28aaf62fa55f0fdb8004aa40f88f23bf53f0amw * NPI_HW_ERR
da6c28aaf62fa55f0fdb8004aa40f88f23bf53f0amw * NPI_SW_ERR
a3c49ce110f325a563c245bedc4d533adddb7211Albert Leenpi_status_t npi_rxdma_cfg_port_ddr_weight(npi_handle_t,
da6c28aaf62fa55f0fdb8004aa40f88f23bf53f0amw * npi_rxdma_port_usage_get()
da6c28aaf62fa55f0fdb8004aa40f88f23bf53f0amw * Gets the port usage, in terms of 16 byte blocks
da6c28aaf62fa55f0fdb8004aa40f88f23bf53f0amw * NOTE: The register count is cleared upon reading.
da6c28aaf62fa55f0fdb8004aa40f88f23bf53f0amw * handle: register handle interpreted by the underlying OS
da6c28aaf62fa55f0fdb8004aa40f88f23bf53f0amw * portnm: Physical Port Number
da6c28aaf62fa55f0fdb8004aa40f88f23bf53f0amw * blocks: ptr to save current count.
da6c28aaf62fa55f0fdb8004aa40f88f23bf53f0amw * NPI_SUCCESS
da6c28aaf62fa55f0fdb8004aa40f88f23bf53f0amw * NPI_FAILURE
da6c28aaf62fa55f0fdb8004aa40f88f23bf53f0amw * NPI_HW_ERR
da6c28aaf62fa55f0fdb8004aa40f88f23bf53f0amw * NPI_SW_ERR
da6c28aaf62fa55f0fdb8004aa40f88f23bf53f0amw * npi_rxdma_cfg_logical_page()
da6c28aaf62fa55f0fdb8004aa40f88f23bf53f0amw * Configure per rxdma channel Logical page
da6c28aaf62fa55f0fdb8004aa40f88f23bf53f0amw * To disable the logical page, set valid = 0;
da6c28aaf62fa55f0fdb8004aa40f88f23bf53f0amw * handle: register handle interpreted by the underlying OS
da6c28aaf62fa55f0fdb8004aa40f88f23bf53f0amw * rdc: RX DMA Channel number
da6c28aaf62fa55f0fdb8004aa40f88f23bf53f0amw * page_params: Logical Page configuration parameters
da6c28aaf62fa55f0fdb8004aa40f88f23bf53f0amw * NPI_SUCCESS
da6c28aaf62fa55f0fdb8004aa40f88f23bf53f0amw * NPI_FAILURE
da6c28aaf62fa55f0fdb8004aa40f88f23bf53f0amw * NPI_SW_ERR
da6c28aaf62fa55f0fdb8004aa40f88f23bf53f0amw * NPI_HW_ERR
da6c28aaf62fa55f0fdb8004aa40f88f23bf53f0amwnpi_status_t npi_rxdma_cfg_logical_page(npi_handle_t, uint8_t,
da6c28aaf62fa55f0fdb8004aa40f88f23bf53f0amw * npi_rxdma_cfg_logical_page_handle()
da6c28aaf62fa55f0fdb8004aa40f88f23bf53f0amw * Configure per rxdma channel Logical page handle
da6c28aaf62fa55f0fdb8004aa40f88f23bf53f0amw * handle: register handle interpreted by the underlying OS
da6c28aaf62fa55f0fdb8004aa40f88f23bf53f0amw * rdc: RX DMA Channel number
da6c28aaf62fa55f0fdb8004aa40f88f23bf53f0amw * pg_handle: Logical Page handle
da6c28aaf62fa55f0fdb8004aa40f88f23bf53f0amw * NPI_SUCCESS
da6c28aaf62fa55f0fdb8004aa40f88f23bf53f0amw * NPI_FAILURE
da6c28aaf62fa55f0fdb8004aa40f88f23bf53f0amw * NPI_SW_ERR
da6c28aaf62fa55f0fdb8004aa40f88f23bf53f0amw * NPI_HW_ERR
da6c28aaf62fa55f0fdb8004aa40f88f23bf53f0amwnpi_status_t npi_rxdma_cfg_logical_page_handle(npi_handle_t, uint8_t,
da6c28aaf62fa55f0fdb8004aa40f88f23bf53f0amwnpi_status_t npi_rxdma_cfg_logical_page_disable(npi_handle_t,
da6c28aaf62fa55f0fdb8004aa40f88f23bf53f0amwtypedef enum _bsize {
da6c28aaf62fa55f0fdb8004aa40f88f23bf53f0amw * npi_rxdma_cfg_rdc_ring()
da6c28aaf62fa55f0fdb8004aa40f88f23bf53f0amw * Configure The RDC channel Rcv Buffer Ring
da6c28aaf62fa55f0fdb8004aa40f88f23bf53f0amw * rdc: RX DMA Channel number
da6c28aaf62fa55f0fdb8004aa40f88f23bf53f0amw * rdc_params: RDC configuration parameters
da6c28aaf62fa55f0fdb8004aa40f88f23bf53f0amw * NPI_SUCCESS
da6c28aaf62fa55f0fdb8004aa40f88f23bf53f0amw * NPI_FAILURE
da6c28aaf62fa55f0fdb8004aa40f88f23bf53f0amw * NPI_SW_ERR
da6c28aaf62fa55f0fdb8004aa40f88f23bf53f0amw * NPI_HW_ERR
da6c28aaf62fa55f0fdb8004aa40f88f23bf53f0amwtypedef struct _rdc_desc_cfg_t {
da6c28aaf62fa55f0fdb8004aa40f88f23bf53f0amwnpi_status_t npi_rxdma_cfg_rdc_ring(npi_handle_t, uint8_t,
da6c28aaf62fa55f0fdb8004aa40f88f23bf53f0amw * npi_rxdma_rdc_rcr_flush
da6c28aaf62fa55f0fdb8004aa40f88f23bf53f0amw * Forces RX completion ring update
da6c28aaf62fa55f0fdb8004aa40f88f23bf53f0amw * rdc: RX DMA Channel number
da6c28aaf62fa55f0fdb8004aa40f88f23bf53f0amw * npi_rxdma_rdc_rcr_read_update
da6c28aaf62fa55f0fdb8004aa40f88f23bf53f0amw * Update the number of rcr packets and buffers processed
da6c28aaf62fa55f0fdb8004aa40f88f23bf53f0amw * channel: RX DMA Channel number
da6c28aaf62fa55f0fdb8004aa40f88f23bf53f0amw * num_pkts: Number of pkts processed by SW.
da6c28aaf62fa55f0fdb8004aa40f88f23bf53f0amw * A packet could constitute multiple
da6c28aaf62fa55f0fdb8004aa40f88f23bf53f0amw * buffers, in case jumbo packets.
da6c28aaf62fa55f0fdb8004aa40f88f23bf53f0amw * num_bufs: Number of buffer processed by SW.
da6c28aaf62fa55f0fdb8004aa40f88f23bf53f0amw * NPI_FAILURE -
da6c28aaf62fa55f0fdb8004aa40f88f23bf53f0amw * NPI_RXDMA_OPCODE_INVALID -
da6c28aaf62fa55f0fdb8004aa40f88f23bf53f0amw * NPI_RXDMA_CHANNEL_INVALID -
da6c28aaf62fa55f0fdb8004aa40f88f23bf53f0amwnpi_status_t npi_rxdma_rdc_rcr_read_update(npi_handle_t, uint8_t,
da6c28aaf62fa55f0fdb8004aa40f88f23bf53f0amw * npi_rxdma_rdc_rcr_pktread_update
da6c28aaf62fa55f0fdb8004aa40f88f23bf53f0amw * Update the number of packets processed
da6c28aaf62fa55f0fdb8004aa40f88f23bf53f0amw * channel: RX DMA Channel number
da6c28aaf62fa55f0fdb8004aa40f88f23bf53f0amw * num_pkts: Number ofpkts processed by SW.
da6c28aaf62fa55f0fdb8004aa40f88f23bf53f0amw * A packet could constitute multiple
da6c28aaf62fa55f0fdb8004aa40f88f23bf53f0amw * buffers, in case jumbo packets.
da6c28aaf62fa55f0fdb8004aa40f88f23bf53f0amw * NPI_FAILURE -
da6c28aaf62fa55f0fdb8004aa40f88f23bf53f0amw * NPI_RXDMA_OPCODE_INVALID -
da6c28aaf62fa55f0fdb8004aa40f88f23bf53f0amw * NPI_RXDMA_CHANNEL_INVALID -
da6c28aaf62fa55f0fdb8004aa40f88f23bf53f0amwnpi_status_t npi_rxdma_rdc_rcr_pktread_update(npi_handle_t,
da6c28aaf62fa55f0fdb8004aa40f88f23bf53f0amw * npi_rxdma_rdc_rcr_bufread_update
da6c28aaf62fa55f0fdb8004aa40f88f23bf53f0amw * Update the number of buffers processed
da6c28aaf62fa55f0fdb8004aa40f88f23bf53f0amw * channel: RX DMA Channel number
da6c28aaf62fa55f0fdb8004aa40f88f23bf53f0amw * num_bufs: Number of buffer processed by SW. Multiple buffers
da6c28aaf62fa55f0fdb8004aa40f88f23bf53f0amw * could be part of a single packet.
da6c28aaf62fa55f0fdb8004aa40f88f23bf53f0amw * NPI_FAILURE -
da6c28aaf62fa55f0fdb8004aa40f88f23bf53f0amw * NPI_RXDMA_OPCODE_INVALID -
da6c28aaf62fa55f0fdb8004aa40f88f23bf53f0amw * NPI_RXDMA_CHANNEL_INVALID -
da6c28aaf62fa55f0fdb8004aa40f88f23bf53f0amwnpi_status_t npi_rxdma_rdc_rcr_bufread_update(npi_handle_t,
da6c28aaf62fa55f0fdb8004aa40f88f23bf53f0amw * npi_rxdma_rdc_rbr_kick
da6c28aaf62fa55f0fdb8004aa40f88f23bf53f0amw * Kick RDC RBR
da6c28aaf62fa55f0fdb8004aa40f88f23bf53f0amw * rdc: RX DMA Channel number
da6c28aaf62fa55f0fdb8004aa40f88f23bf53f0amw * num_buffers: Number of Buffers posted to the RBR
da6c28aaf62fa55f0fdb8004aa40f88f23bf53f0amw#define npi_rxdma_rdc_rbr_kick(handle, rdc, num_buffers) \
da6c28aaf62fa55f0fdb8004aa40f88f23bf53f0amw RXDMA_REG_WRITE64(handle, RBR_KICK_REG, rdc, num_buffers)
da6c28aaf62fa55f0fdb8004aa40f88f23bf53f0amw * npi_rxdma_rdc_rbr_head_get
da6c28aaf62fa55f0fdb8004aa40f88f23bf53f0amw * Gets the current rbr head pointer.
da6c28aaf62fa55f0fdb8004aa40f88f23bf53f0amw * rdc: RX DMA Channel number
da6c28aaf62fa55f0fdb8004aa40f88f23bf53f0amw * hdptr ptr to write the rbr head value
da6c28aaf62fa55f0fdb8004aa40f88f23bf53f0amw * npi_rxdma_rdc_rbr_stat_get
da6c28aaf62fa55f0fdb8004aa40f88f23bf53f0amw * Returns the RBR stat. The stat consists of the
da6c28aaf62fa55f0fdb8004aa40f88f23bf53f0amw * RX buffers in the ring. It also indicates if there
da6c28aaf62fa55f0fdb8004aa40f88f23bf53f0amw * has been an overflow.
da6c28aaf62fa55f0fdb8004aa40f88f23bf53f0amw * rdc: RX DMA Channel number
da6c28aaf62fa55f0fdb8004aa40f88f23bf53f0amw * rbr_stat_t: Structure to update stat
da6c28aaf62fa55f0fdb8004aa40f88f23bf53f0amwnpi_status_t npi_rxdma_rdc_rbr_stat_get(npi_handle_t, uint8_t,
da6c28aaf62fa55f0fdb8004aa40f88f23bf53f0amw * npi_rxdma_cfg_rdc_reset
da6c28aaf62fa55f0fdb8004aa40f88f23bf53f0amw * Resets the RDC channel
da6c28aaf62fa55f0fdb8004aa40f88f23bf53f0amw * rdc: RX DMA Channel number
da6c28aaf62fa55f0fdb8004aa40f88f23bf53f0amwnpi_status_t npi_rxdma_cfg_rdc_reset(npi_handle_t, uint8_t);
da6c28aaf62fa55f0fdb8004aa40f88f23bf53f0amw * npi_rxdma_rdc_enable
da6c28aaf62fa55f0fdb8004aa40f88f23bf53f0amw * Enables the RDC channel
da6c28aaf62fa55f0fdb8004aa40f88f23bf53f0amw * rdc: RX DMA Channel number
da6c28aaf62fa55f0fdb8004aa40f88f23bf53f0amwnpi_status_t npi_rxdma_cfg_rdc_enable(npi_handle_t, uint8_t);
da6c28aaf62fa55f0fdb8004aa40f88f23bf53f0amw * npi_rxdma_rdc_disable
da6c28aaf62fa55f0fdb8004aa40f88f23bf53f0amw * Disables the RDC channel
da6c28aaf62fa55f0fdb8004aa40f88f23bf53f0amw * rdc: RX DMA Channel number
da6c28aaf62fa55f0fdb8004aa40f88f23bf53f0amwnpi_status_t npi_rxdma_cfg_rdc_disable(npi_handle_t, uint8_t);
da6c28aaf62fa55f0fdb8004aa40f88f23bf53f0amw * npi_rxdma_cfg_rdc_rcr_timeout()
da6c28aaf62fa55f0fdb8004aa40f88f23bf53f0amw * Configure The RDC channel completion ring timeout.
da6c28aaf62fa55f0fdb8004aa40f88f23bf53f0amw * If a frame has been received, an event would be
da6c28aaf62fa55f0fdb8004aa40f88f23bf53f0amw * generated atleast at the expiration of the timeout.
da6c28aaf62fa55f0fdb8004aa40f88f23bf53f0amw * Enables timeout by default.
da6c28aaf62fa55f0fdb8004aa40f88f23bf53f0amw * rdc: RX DMA Channel number
da6c28aaf62fa55f0fdb8004aa40f88f23bf53f0amw * rcr_timeout: Completion Ring timeout value
da6c28aaf62fa55f0fdb8004aa40f88f23bf53f0amw * NPI_SUCCESS
da6c28aaf62fa55f0fdb8004aa40f88f23bf53f0amw * NPI_FAILURE
da6c28aaf62fa55f0fdb8004aa40f88f23bf53f0amw * NPI_SW_ERR
da6c28aaf62fa55f0fdb8004aa40f88f23bf53f0amw * NPI_HW_ERR
da6c28aaf62fa55f0fdb8004aa40f88f23bf53f0amwnpi_status_t npi_rxdma_cfg_rdc_rcr_timeout(npi_handle_t, uint8_t,
da6c28aaf62fa55f0fdb8004aa40f88f23bf53f0amw * npi_rxdma_cfg_rdc_rcr_threshold()
da6c28aaf62fa55f0fdb8004aa40f88f23bf53f0amw * Configure The RDC channel completion ring threshold.
da6c28aaf62fa55f0fdb8004aa40f88f23bf53f0amw * An event would be If the number of frame received,
da6c28aaf62fa55f0fdb8004aa40f88f23bf53f0amw * surpasses the threshold value
da6c28aaf62fa55f0fdb8004aa40f88f23bf53f0amw * rdc: RX DMA Channel number
da6c28aaf62fa55f0fdb8004aa40f88f23bf53f0amw * rcr_threshold: Completion Ring Threshold count
da6c28aaf62fa55f0fdb8004aa40f88f23bf53f0amw * NPI_SUCCESS
da6c28aaf62fa55f0fdb8004aa40f88f23bf53f0amw * NPI_FAILURE
da6c28aaf62fa55f0fdb8004aa40f88f23bf53f0amw * NPI_SW_ERR
da6c28aaf62fa55f0fdb8004aa40f88f23bf53f0amw * NPI_HW_ERR
da6c28aaf62fa55f0fdb8004aa40f88f23bf53f0amwnpi_status_t npi_rxdma_cfg_rdc_rcr_threshold(npi_handle_t, uint8_t,
da6c28aaf62fa55f0fdb8004aa40f88f23bf53f0amwnpi_status_t npi_rxdma_cfg_rdc_rcr_timeout_disable(npi_handle_t, uint8_t);
da6c28aaf62fa55f0fdb8004aa40f88f23bf53f0amwtypedef struct _rdc_error_stat_t {
da6c28aaf62fa55f0fdb8004aa40f88f23bf53f0amw * npi_rxdma_rdc_error_stat_get
da6c28aaf62fa55f0fdb8004aa40f88f23bf53f0amw * Gets the current Error stat for the RDC.
da6c28aaf62fa55f0fdb8004aa40f88f23bf53f0amw * rdc: RX DMA Channel number
da6c28aaf62fa55f0fdb8004aa40f88f23bf53f0amw * error_stat Structure to write current RDC Error stat
da6c28aaf62fa55f0fdb8004aa40f88f23bf53f0amw * npi_rxdma_rdc_rcr_tail_get
da6c28aaf62fa55f0fdb8004aa40f88f23bf53f0amw * Gets the current RCR tail address for the RDC.
da6c28aaf62fa55f0fdb8004aa40f88f23bf53f0amw * rdc: RX DMA Channel number
da6c28aaf62fa55f0fdb8004aa40f88f23bf53f0amw * tail_addr Structure to write current RDC RCR tail address
da6c28aaf62fa55f0fdb8004aa40f88f23bf53f0amwtypedef struct _rdc_discard_stat_t {
da6c28aaf62fa55f0fdb8004aa40f88f23bf53f0amw * npi_rxdma_rdc_discard_stat_get
da6c28aaf62fa55f0fdb8004aa40f88f23bf53f0amw * Gets the current discrad stats for the RDC.
da6c28aaf62fa55f0fdb8004aa40f88f23bf53f0amw * rdc: RX DMA Channel number
da6c28aaf62fa55f0fdb8004aa40f88f23bf53f0amw * rcr_stat Structure to write current RDC discard stat
da6c28aaf62fa55f0fdb8004aa40f88f23bf53f0amwnpi_status_t npi_rxdma_rdc_discard_stat_get(npi_handle_t,
da6c28aaf62fa55f0fdb8004aa40f88f23bf53f0amw * npi_rx_port_discard_stat_get
da6c28aaf62fa55f0fdb8004aa40f88f23bf53f0amw * Gets the current input (IPP) discrad stats for the rx port.
da6c28aaf62fa55f0fdb8004aa40f88f23bf53f0amw * rdc: RX DMA Channel number
da6c28aaf62fa55f0fdb8004aa40f88f23bf53f0amw * rx_disc_cnt_t Structure to write current RDC discard stat
da6c28aaf62fa55f0fdb8004aa40f88f23bf53f0amw * npi_rxdma_red_discard_stat_get
da6c28aaf62fa55f0fdb8004aa40f88f23bf53f0amw * Gets the current discrad count due RED
da6c28aaf62fa55f0fdb8004aa40f88f23bf53f0amw * The counter overflow bit is cleared, if it has been set.
da6c28aaf62fa55f0fdb8004aa40f88f23bf53f0amw * rdc: RX DMA Channel number
da6c28aaf62fa55f0fdb8004aa40f88f23bf53f0amw * rx_disc_cnt_t Structure to write current RDC discard stat
da6c28aaf62fa55f0fdb8004aa40f88f23bf53f0amw * NPI_SUCCESS
da6c28aaf62fa55f0fdb8004aa40f88f23bf53f0amw * NPI_RXDMA_RDC_INVALID
da6c28aaf62fa55f0fdb8004aa40f88f23bf53f0amwnpi_status_t npi_rxdma_red_discard_stat_get(npi_handle_t, uint8_t,
da6c28aaf62fa55f0fdb8004aa40f88f23bf53f0amw * npi_rxdma_red_discard_oflow_clear
da6c28aaf62fa55f0fdb8004aa40f88f23bf53f0amw * Clear RED discard counter overflow bit
da6c28aaf62fa55f0fdb8004aa40f88f23bf53f0amw * rdc: RX DMA Channel number
da6c28aaf62fa55f0fdb8004aa40f88f23bf53f0amw * NPI_SUCCESS
da6c28aaf62fa55f0fdb8004aa40f88f23bf53f0amw * NPI_RXDMA_RDC_INVALID
da6c28aaf62fa55f0fdb8004aa40f88f23bf53f0amwnpi_status_t npi_rxdma_red_discard_oflow_clear(npi_handle_t,
da6c28aaf62fa55f0fdb8004aa40f88f23bf53f0amw * npi_rxdma_misc_discard_stat_get
da6c28aaf62fa55f0fdb8004aa40f88f23bf53f0amw * Gets the current discrad count for the rdc due to
da6c28aaf62fa55f0fdb8004aa40f88f23bf53f0amw * buffer pool empty
da6c28aaf62fa55f0fdb8004aa40f88f23bf53f0amw * The counter overflow bit is cleared, if it has been set.
da6c28aaf62fa55f0fdb8004aa40f88f23bf53f0amw * rdc: RX DMA Channel number
da6c28aaf62fa55f0fdb8004aa40f88f23bf53f0amw * rx_disc_cnt_t Structure to write current RDC discard stat
da6c28aaf62fa55f0fdb8004aa40f88f23bf53f0amw * NPI_SUCCESS
da6c28aaf62fa55f0fdb8004aa40f88f23bf53f0amw * NPI_RXDMA_RDC_INVALID
da6c28aaf62fa55f0fdb8004aa40f88f23bf53f0amwnpi_status_t npi_rxdma_misc_discard_stat_get(npi_handle_t, uint8_t,
da6c28aaf62fa55f0fdb8004aa40f88f23bf53f0amw * npi_rxdma_red_discard_oflow_clear
da6c28aaf62fa55f0fdb8004aa40f88f23bf53f0amw * Clear RED discard counter overflow bit
da6c28aaf62fa55f0fdb8004aa40f88f23bf53f0amw * clear the overflow bit for buffer pool empty discrad counter
da6c28aaf62fa55f0fdb8004aa40f88f23bf53f0amw * for the rdc
da6c28aaf62fa55f0fdb8004aa40f88f23bf53f0amw * rdc: RX DMA Channel number
da6c28aaf62fa55f0fdb8004aa40f88f23bf53f0amw * NPI_SUCCESS
da6c28aaf62fa55f0fdb8004aa40f88f23bf53f0amw * NPI_RXDMA_RDC_INVALID
da6c28aaf62fa55f0fdb8004aa40f88f23bf53f0amwnpi_status_t npi_rxdma_misc_discard_oflow_clear(npi_handle_t,
da6c28aaf62fa55f0fdb8004aa40f88f23bf53f0amw * npi_rxdma_ring_perr_stat_get
da6c28aaf62fa55f0fdb8004aa40f88f23bf53f0amw * Gets the current RDC Memory parity error
da6c28aaf62fa55f0fdb8004aa40f88f23bf53f0amw * The counter overflow bit is cleared, if it has been set.
da6c28aaf62fa55f0fdb8004aa40f88f23bf53f0amw * pre_cnt: Structure to write current RDC Prefetch memory
da6c28aaf62fa55f0fdb8004aa40f88f23bf53f0amw * Parity Error stat
da6c28aaf62fa55f0fdb8004aa40f88f23bf53f0amw * sha_cnt: Structure to write current RDC Shadow memory
da6c28aaf62fa55f0fdb8004aa40f88f23bf53f0amw * Parity Error stat
da6c28aaf62fa55f0fdb8004aa40f88f23bf53f0amw * NPI_SUCCESS
da6c28aaf62fa55f0fdb8004aa40f88f23bf53f0amw * NPI_RXDMA_RDC_INVALID
da6c28aaf62fa55f0fdb8004aa40f88f23bf53f0amw * npi_rxdma_ring_perr_stat_get
da6c28aaf62fa55f0fdb8004aa40f88f23bf53f0amw * Clear RDC Memory Parity Error counter overflow bits
da6c28aaf62fa55f0fdb8004aa40f88f23bf53f0amw * NPI_SUCCESS
da6c28aaf62fa55f0fdb8004aa40f88f23bf53f0amwnpi_status_t npi_rxdma_ring_perr_stat_clear(npi_handle_t);
da6c28aaf62fa55f0fdb8004aa40f88f23bf53f0amw/* Access the RDMC Memory: used for debugging */
da6c28aaf62fa55f0fdb8004aa40f88f23bf53f0amw * npi_rxdma_rxctl_fifo_error_intr_set
da6c28aaf62fa55f0fdb8004aa40f88f23bf53f0amw * Configure The RX ctrl fifo error interrupt generation
da6c28aaf62fa55f0fdb8004aa40f88f23bf53f0amw * mask: rx_ctl_dat_fifo_mask_t specifying the errors
da6c28aaf62fa55f0fdb8004aa40f88f23bf53f0amw * NPI_SUCCESS
da6c28aaf62fa55f0fdb8004aa40f88f23bf53f0amw * NPI_FAILURE
da6c28aaf62fa55f0fdb8004aa40f88f23bf53f0amwnpi_status_t npi_rxdma_rxctl_fifo_error_intr_set(npi_handle_t,
da6c28aaf62fa55f0fdb8004aa40f88f23bf53f0amw * npi_rxdma_rxctl_fifo_error_status_get
da6c28aaf62fa55f0fdb8004aa40f88f23bf53f0amw * Read The RX ctrl fifo error Status
da6c28aaf62fa55f0fdb8004aa40f88f23bf53f0amw * stat: rx_ctl_dat_fifo_stat_t to read the errors to
da6c28aaf62fa55f0fdb8004aa40f88f23bf53f0amw * valid fields in rx_ctl_dat_fifo_stat_t structure are:
da6c28aaf62fa55f0fdb8004aa40f88f23bf53f0amw * zcp_eop_err, ipp_eop_err, id_mismatch.
da6c28aaf62fa55f0fdb8004aa40f88f23bf53f0amw * NPI_SUCCESS
da6c28aaf62fa55f0fdb8004aa40f88f23bf53f0amw * NPI_FAILURE
da6c28aaf62fa55f0fdb8004aa40f88f23bf53f0amwnpi_status_t npi_rxdma_rxctl_fifo_error_status_get(npi_handle_t,
da6c28aaf62fa55f0fdb8004aa40f88f23bf53f0amw * npi_rxdma_channel_mex_set():
da6c28aaf62fa55f0fdb8004aa40f88f23bf53f0amw * This function is called to arm the DMA channel with
a3c49ce110f325a563c245bedc4d533adddb7211Albert Lee * mailbox updating capability. Software needs to rearm
da6c28aaf62fa55f0fdb8004aa40f88f23bf53f0amw * for each update by writing to the control and status register.
da6c28aaf62fa55f0fdb8004aa40f88f23bf53f0amw * Parameters:
da6c28aaf62fa55f0fdb8004aa40f88f23bf53f0amw * handle - NPI handle (virtualization flag must be defined).
da6c28aaf62fa55f0fdb8004aa40f88f23bf53f0amw * channel - logical RXDMA channel from 0 to 23.
da6c28aaf62fa55f0fdb8004aa40f88f23bf53f0amw * (If virtualization flag is not set, then
da6c28aaf62fa55f0fdb8004aa40f88f23bf53f0amw * logical channel is the same as the hardware
da6c28aaf62fa55f0fdb8004aa40f88f23bf53f0amw * channel number).
da6c28aaf62fa55f0fdb8004aa40f88f23bf53f0amw * NPI_SUCCESS - If enable channel with mailbox update
da6c28aaf62fa55f0fdb8004aa40f88f23bf53f0amw * is complete successfully.
da6c28aaf62fa55f0fdb8004aa40f88f23bf53f0amw * NPI_FAILURE -
da6c28aaf62fa55f0fdb8004aa40f88f23bf53f0amw * NPI_RXDMA_CHANNEL_INVALID -
da6c28aaf62fa55f0fdb8004aa40f88f23bf53f0amwnpi_status_t npi_rxdma_channel_mex_set(npi_handle_t, uint8_t);
da6c28aaf62fa55f0fdb8004aa40f88f23bf53f0amw * npi_rxdma_channel_rcrto_clear():
da6c28aaf62fa55f0fdb8004aa40f88f23bf53f0amw * This function is called to reset RCRTO bit to 0.
da6c28aaf62fa55f0fdb8004aa40f88f23bf53f0amw * Parameters:
da6c28aaf62fa55f0fdb8004aa40f88f23bf53f0amw * handle - NPI handle (virtualization flag must be defined).
da6c28aaf62fa55f0fdb8004aa40f88f23bf53f0amw * channel - logical RXDMA channel from 0 to 23.
da6c28aaf62fa55f0fdb8004aa40f88f23bf53f0amw * (If virtualization flag is not set, then
da6c28aaf62fa55f0fdb8004aa40f88f23bf53f0amw * logical channel is the same as the hardware
da6c28aaf62fa55f0fdb8004aa40f88f23bf53f0amw * channel number).
da6c28aaf62fa55f0fdb8004aa40f88f23bf53f0amw * NPI_SUCCESS
da6c28aaf62fa55f0fdb8004aa40f88f23bf53f0amw * NPI_FAILURE -
da6c28aaf62fa55f0fdb8004aa40f88f23bf53f0amw * NPI_RXDMA_CHANNEL_INVALID -
da6c28aaf62fa55f0fdb8004aa40f88f23bf53f0amwnpi_status_t npi_rxdma_channel_rcrto_clear(npi_handle_t, uint8_t);
da6c28aaf62fa55f0fdb8004aa40f88f23bf53f0amw * npi_rxdma_channel_pt_drop_pkt_clear():
da6c28aaf62fa55f0fdb8004aa40f88f23bf53f0amw * This function is called to clear the port drop packet bit (debug).
da6c28aaf62fa55f0fdb8004aa40f88f23bf53f0amw * Parameters:
da6c28aaf62fa55f0fdb8004aa40f88f23bf53f0amw * handle - NPI handle (virtualization flag must be defined).
da6c28aaf62fa55f0fdb8004aa40f88f23bf53f0amw * channel - logical RXDMA channel from 0 to 23.
da6c28aaf62fa55f0fdb8004aa40f88f23bf53f0amw * (If virtualization flag is not set, then
da6c28aaf62fa55f0fdb8004aa40f88f23bf53f0amw * logical channel is the same as the hardware
da6c28aaf62fa55f0fdb8004aa40f88f23bf53f0amw * channel number).
da6c28aaf62fa55f0fdb8004aa40f88f23bf53f0amw * NPI_SUCCESS
a3c49ce110f325a563c245bedc4d533adddb7211Albert Lee * NPI_FAILURE -
da6c28aaf62fa55f0fdb8004aa40f88f23bf53f0amw * NPI_RXDMA_CHANNEL_INVALID -
da6c28aaf62fa55f0fdb8004aa40f88f23bf53f0amwnpi_status_t npi_rxdma_channel_pt_drop_pkt_clear(npi_handle_t, uint8_t);
da6c28aaf62fa55f0fdb8004aa40f88f23bf53f0amw * npi_rxdma_channel_wred_drop_clear():
da6c28aaf62fa55f0fdb8004aa40f88f23bf53f0amw * This function is called to wred drop bit (debug only).
da6c28aaf62fa55f0fdb8004aa40f88f23bf53f0amw * Parameters:
da6c28aaf62fa55f0fdb8004aa40f88f23bf53f0amw * handle - NPI handle (virtualization flag must be defined).
da6c28aaf62fa55f0fdb8004aa40f88f23bf53f0amw * channel - logical RXDMA channel from 0 to 23.
da6c28aaf62fa55f0fdb8004aa40f88f23bf53f0amw * (If virtualization flag is not set, then
da6c28aaf62fa55f0fdb8004aa40f88f23bf53f0amw * logical channel is the same as the hardware
da6c28aaf62fa55f0fdb8004aa40f88f23bf53f0amw * channel number).
da6c28aaf62fa55f0fdb8004aa40f88f23bf53f0amw * NPI_SUCCESS
da6c28aaf62fa55f0fdb8004aa40f88f23bf53f0amw * NPI_FAILURE -
da6c28aaf62fa55f0fdb8004aa40f88f23bf53f0amw * NPI_RXDMA_CHANNEL_INVALID -
da6c28aaf62fa55f0fdb8004aa40f88f23bf53f0amwnpi_status_t npi_rxdma_channel_wred_drop_clear(npi_handle_t, uint8_t);
da6c28aaf62fa55f0fdb8004aa40f88f23bf53f0amw * npi_rxdma_channel_rcr_shfull_clear():
da6c28aaf62fa55f0fdb8004aa40f88f23bf53f0amw * This function is called to clear RCR shadow full bit.
da6c28aaf62fa55f0fdb8004aa40f88f23bf53f0amw * Parameters:
da6c28aaf62fa55f0fdb8004aa40f88f23bf53f0amw * handle - NPI handle (virtualization flag must be defined).
da6c28aaf62fa55f0fdb8004aa40f88f23bf53f0amw * channel - logical RXDMA channel from 0 to 23.
da6c28aaf62fa55f0fdb8004aa40f88f23bf53f0amw * (If virtualization flag is not set, then
da6c28aaf62fa55f0fdb8004aa40f88f23bf53f0amw * logical channel is the same as the hardware
da6c28aaf62fa55f0fdb8004aa40f88f23bf53f0amw * channel number).
da6c28aaf62fa55f0fdb8004aa40f88f23bf53f0amw * NPI_SUCCESS
da6c28aaf62fa55f0fdb8004aa40f88f23bf53f0amw * NPI_FAILURE -
da6c28aaf62fa55f0fdb8004aa40f88f23bf53f0amw * NPI_RXDMA_CHANNEL_INVALID -
da6c28aaf62fa55f0fdb8004aa40f88f23bf53f0amwnpi_status_t npi_rxdma_channel_rcr_shfull_clear(npi_handle_t, uint8_t);
da6c28aaf62fa55f0fdb8004aa40f88f23bf53f0amw * npi_rxdma_channel_rcrfull_clear():
da6c28aaf62fa55f0fdb8004aa40f88f23bf53f0amw * This function is called to clear RCR full bit.
da6c28aaf62fa55f0fdb8004aa40f88f23bf53f0amw * Parameters:
da6c28aaf62fa55f0fdb8004aa40f88f23bf53f0amw * handle - NPI handle (virtualization flag must be defined).
da6c28aaf62fa55f0fdb8004aa40f88f23bf53f0amw * channel - logical RXDMA channel from 0 to 23.
da6c28aaf62fa55f0fdb8004aa40f88f23bf53f0amw * (If virtualization flag is not set, then
da6c28aaf62fa55f0fdb8004aa40f88f23bf53f0amw * logical channel is the same as the hardware
da6c28aaf62fa55f0fdb8004aa40f88f23bf53f0amw * channel number).
da6c28aaf62fa55f0fdb8004aa40f88f23bf53f0amw * NPI_SUCCESS
da6c28aaf62fa55f0fdb8004aa40f88f23bf53f0amw * NPI_FAILURE -
da6c28aaf62fa55f0fdb8004aa40f88f23bf53f0amw * NPI_RXDMA_CHANNEL_INVALID -
da6c28aaf62fa55f0fdb8004aa40f88f23bf53f0amwnpi_status_t npi_rxdma_channel_rcrfull_clear(npi_handle_t, uint8_t);
da6c28aaf62fa55f0fdb8004aa40f88f23bf53f0amw * npi_rxdma_rbr_pre_empty_clear():
da6c28aaf62fa55f0fdb8004aa40f88f23bf53f0amw * This function is called to control a receive DMA channel
da6c28aaf62fa55f0fdb8004aa40f88f23bf53f0amw * for arming the channel with mailbox updates, resetting
da6c28aaf62fa55f0fdb8004aa40f88f23bf53f0amw * various event status bits (control and status register).
da6c28aaf62fa55f0fdb8004aa40f88f23bf53f0amw * Parameters:
da6c28aaf62fa55f0fdb8004aa40f88f23bf53f0amw * handle - NPI handle (virtualization flag must be defined).
da6c28aaf62fa55f0fdb8004aa40f88f23bf53f0amw * control - NPI defined control type supported:
da6c28aaf62fa55f0fdb8004aa40f88f23bf53f0amw * - RXDMA_MEX_SET
da6c28aaf62fa55f0fdb8004aa40f88f23bf53f0amw * - RXDMA_RCRTO_CLEAR
da6c28aaf62fa55f0fdb8004aa40f88f23bf53f0amw * - RXDMA_PT_DROP_PKT_CLEAR
da6c28aaf62fa55f0fdb8004aa40f88f23bf53f0amw * - RXDMA_WRED_DROP_CLEAR
da6c28aaf62fa55f0fdb8004aa40f88f23bf53f0amw * - RXDMA_RCR_SFULL_CLEAR
da6c28aaf62fa55f0fdb8004aa40f88f23bf53f0amw * - RXDMA_RCR_FULL_CLEAR
da6c28aaf62fa55f0fdb8004aa40f88f23bf53f0amw * - RXDMA_RBR_PRE_EMPTY_CLEAR
da6c28aaf62fa55f0fdb8004aa40f88f23bf53f0amw * channel - logical RXDMA channel from 0 to 23.
da6c28aaf62fa55f0fdb8004aa40f88f23bf53f0amw * (If virtualization flag is not set, then
da6c28aaf62fa55f0fdb8004aa40f88f23bf53f0amw * logical channel is the same as the hardware.
da6c28aaf62fa55f0fdb8004aa40f88f23bf53f0amw * NPI_SUCCESS
da6c28aaf62fa55f0fdb8004aa40f88f23bf53f0amw * NPI_FAILURE -
da6c28aaf62fa55f0fdb8004aa40f88f23bf53f0amw * NPI_RXDMA_CHANNEL_INVALID -
da6c28aaf62fa55f0fdb8004aa40f88f23bf53f0amwnpi_status_t npi_rxdma_channel_rbr_pre_empty_clear(npi_handle_t, uint8_t);
da6c28aaf62fa55f0fdb8004aa40f88f23bf53f0amw * npi_rxdma_channel_control():
da6c28aaf62fa55f0fdb8004aa40f88f23bf53f0amw * This function is called to control a receive DMA channel
da6c28aaf62fa55f0fdb8004aa40f88f23bf53f0amw * for arming the channel with mailbox updates, resetting
da6c28aaf62fa55f0fdb8004aa40f88f23bf53f0amw * various event status bits (control and status register).
da6c28aaf62fa55f0fdb8004aa40f88f23bf53f0amw * Parameters:
da6c28aaf62fa55f0fdb8004aa40f88f23bf53f0amw * handle - NPI handle (virtualization flag must be defined).
da6c28aaf62fa55f0fdb8004aa40f88f23bf53f0amw * control - NPI defined control type supported:
da6c28aaf62fa55f0fdb8004aa40f88f23bf53f0amw * - RXDMA_MEX_SET
da6c28aaf62fa55f0fdb8004aa40f88f23bf53f0amw * - RXDMA_RCRTO_CLEAR
da6c28aaf62fa55f0fdb8004aa40f88f23bf53f0amw * - RXDMA_PT_DROP_PKT_CLEAR
da6c28aaf62fa55f0fdb8004aa40f88f23bf53f0amw * - RXDMA_WRED_DROP_CLEAR
da6c28aaf62fa55f0fdb8004aa40f88f23bf53f0amw * - RXDMA_RCR_SFULL_CLEAR
da6c28aaf62fa55f0fdb8004aa40f88f23bf53f0amw * - RXDMA_RCR_FULL_CLEAR
da6c28aaf62fa55f0fdb8004aa40f88f23bf53f0amw * - RXDMA_RBR_PRE_EMPTY_CLEAR
da6c28aaf62fa55f0fdb8004aa40f88f23bf53f0amw * channel - logical RXDMA channel from 0 to 23.
da6c28aaf62fa55f0fdb8004aa40f88f23bf53f0amw * (If virtualization flag is not set, then
da6c28aaf62fa55f0fdb8004aa40f88f23bf53f0amw * logical channel is the same as the hardware.
da6c28aaf62fa55f0fdb8004aa40f88f23bf53f0amw * NPI_SUCCESS
da6c28aaf62fa55f0fdb8004aa40f88f23bf53f0amw * NPI_FAILURE -
da6c28aaf62fa55f0fdb8004aa40f88f23bf53f0amw * NPI_TXDMA_OPCODE_INVALID -
da6c28aaf62fa55f0fdb8004aa40f88f23bf53f0amw * NPI_TXDMA_CHANNEL_INVALID -
da6c28aaf62fa55f0fdb8004aa40f88f23bf53f0amw * npi_rxdma_control_status():
da6c28aaf62fa55f0fdb8004aa40f88f23bf53f0amw * This function is called to operate on the control
da6c28aaf62fa55f0fdb8004aa40f88f23bf53f0amw * and status register.
da6c28aaf62fa55f0fdb8004aa40f88f23bf53f0amw * Parameters:
da6c28aaf62fa55f0fdb8004aa40f88f23bf53f0amw * handle - NPI handle
da6c28aaf62fa55f0fdb8004aa40f88f23bf53f0amw * op_mode - OP_GET: get hardware control and status
da6c28aaf62fa55f0fdb8004aa40f88f23bf53f0amw * OP_SET: set hardware control and status
da6c28aaf62fa55f0fdb8004aa40f88f23bf53f0amw * OP_UPDATE: update hardware control and status.
da6c28aaf62fa55f0fdb8004aa40f88f23bf53f0amw * OP_CLEAR: clear control and status register to 0s.
da6c28aaf62fa55f0fdb8004aa40f88f23bf53f0amw * channel - hardware RXDMA channel from 0 to 23.
da6c28aaf62fa55f0fdb8004aa40f88f23bf53f0amw * cs_p - pointer to hardware defined control and status
da6c28aaf62fa55f0fdb8004aa40f88f23bf53f0amw * structure.
da6c28aaf62fa55f0fdb8004aa40f88f23bf53f0amw * NPI_SUCCESS
da6c28aaf62fa55f0fdb8004aa40f88f23bf53f0amw * NPI_FAILURE -
da6c28aaf62fa55f0fdb8004aa40f88f23bf53f0amw * NPI_RXDMA_OPCODE_INVALID -
da6c28aaf62fa55f0fdb8004aa40f88f23bf53f0amw * NPI_RXDMA_CHANNEL_INVALID -
da6c28aaf62fa55f0fdb8004aa40f88f23bf53f0amwnpi_status_t npi_rxdma_control_status(npi_handle_t, io_op_t,
da6c28aaf62fa55f0fdb8004aa40f88f23bf53f0amw * npi_rxdma_event_mask():
da6c28aaf62fa55f0fdb8004aa40f88f23bf53f0amw * This function is called to operate on the event mask
da6c28aaf62fa55f0fdb8004aa40f88f23bf53f0amw * register which is used for generating interrupts.
da6c28aaf62fa55f0fdb8004aa40f88f23bf53f0amw * Parameters:
da6c28aaf62fa55f0fdb8004aa40f88f23bf53f0amw * handle - NPI handle
da6c28aaf62fa55f0fdb8004aa40f88f23bf53f0amw * op_mode - OP_GET: get hardware event mask
da6c28aaf62fa55f0fdb8004aa40f88f23bf53f0amw * OP_SET: set hardware interrupt event masks
da6c28aaf62fa55f0fdb8004aa40f88f23bf53f0amw * OP_CLEAR: clear control and status register to 0s.
da6c28aaf62fa55f0fdb8004aa40f88f23bf53f0amw * channel - hardware RXDMA channel from 0 to 23.
da6c28aaf62fa55f0fdb8004aa40f88f23bf53f0amw * mask_p - pointer to hardware defined event mask
da6c28aaf62fa55f0fdb8004aa40f88f23bf53f0amw * structure.
da6c28aaf62fa55f0fdb8004aa40f88f23bf53f0amw * NPI_SUCCESS - If set is complete successfully.
da6c28aaf62fa55f0fdb8004aa40f88f23bf53f0amw * NPI_FAILURE -
da6c28aaf62fa55f0fdb8004aa40f88f23bf53f0amw * NPI_RXDMA_OPCODE_INVALID -
da6c28aaf62fa55f0fdb8004aa40f88f23bf53f0amw * NPI_RXDMA_CHANNEL_INVALID -
da6c28aaf62fa55f0fdb8004aa40f88f23bf53f0amw * npi_rxdma_event_mask_config():
da6c28aaf62fa55f0fdb8004aa40f88f23bf53f0amw * This function is called to operate on the event mask
da6c28aaf62fa55f0fdb8004aa40f88f23bf53f0amw * register which is used for generating interrupts
da6c28aaf62fa55f0fdb8004aa40f88f23bf53f0amw * and status register.
da6c28aaf62fa55f0fdb8004aa40f88f23bf53f0amw * Parameters:
da6c28aaf62fa55f0fdb8004aa40f88f23bf53f0amw * handle - NPI handle
da6c28aaf62fa55f0fdb8004aa40f88f23bf53f0amw * op_mode - OP_GET: get hardware event mask
da6c28aaf62fa55f0fdb8004aa40f88f23bf53f0amw * OP_SET: set hardware interrupt event masks
da6c28aaf62fa55f0fdb8004aa40f88f23bf53f0amw * OP_CLEAR: clear control and status register to 0s.
a3c49ce110f325a563c245bedc4d533adddb7211Albert Lee * channel - hardware RXDMA channel from 0 to 23.
da6c28aaf62fa55f0fdb8004aa40f88f23bf53f0amw * cfgp - pointer to NPI defined event mask
da6c28aaf62fa55f0fdb8004aa40f88f23bf53f0amw * enum data type.
da6c28aaf62fa55f0fdb8004aa40f88f23bf53f0amw * NPI_SUCCESS - If set is complete successfully.
da6c28aaf62fa55f0fdb8004aa40f88f23bf53f0amw * NPI_FAILURE -
da6c28aaf62fa55f0fdb8004aa40f88f23bf53f0amw * NPI_RXDMA_OPCODE_INVALID -
da6c28aaf62fa55f0fdb8004aa40f88f23bf53f0amw * NPI_RXDMA_CHANNEL_INVALID -
da6c28aaf62fa55f0fdb8004aa40f88f23bf53f0amwnpi_status_t npi_rxdma_event_mask_config(npi_handle_t, io_op_t,
da6c28aaf62fa55f0fdb8004aa40f88f23bf53f0amw * npi_rxdma_dump_rdc_regs
da6c28aaf62fa55f0fdb8004aa40f88f23bf53f0amw * Dumps the contents of rdc csrs and fzc registers
da6c28aaf62fa55f0fdb8004aa40f88f23bf53f0amw * rdc: RX DMA number
da6c28aaf62fa55f0fdb8004aa40f88f23bf53f0amw * NPI_SUCCESS
da6c28aaf62fa55f0fdb8004aa40f88f23bf53f0amw * NPI_FAILURE
da6c28aaf62fa55f0fdb8004aa40f88f23bf53f0amw * NPI_RXDMA_RDC_INVALID
da6c28aaf62fa55f0fdb8004aa40f88f23bf53f0amwnpi_status_t npi_rxdma_dump_rdc_regs(npi_handle_t, uint8_t);
da6c28aaf62fa55f0fdb8004aa40f88f23bf53f0amw * npi_rxdma_dump_fzc_regs
da6c28aaf62fa55f0fdb8004aa40f88f23bf53f0amw * Dumps the contents of rdc csrs and fzc registers
da6c28aaf62fa55f0fdb8004aa40f88f23bf53f0amw * rdc: RX DMA number
da6c28aaf62fa55f0fdb8004aa40f88f23bf53f0amw * NPI_SUCCESS
da6c28aaf62fa55f0fdb8004aa40f88f23bf53f0amw * NPI_FAILURE
da6c28aaf62fa55f0fdb8004aa40f88f23bf53f0amw * NPI_RXDMA_RDC_INVALID
da6c28aaf62fa55f0fdb8004aa40f88f23bf53f0amwnpi_status_t npi_rxdma_channel_rbr_empty_clear(npi_handle_t,
da6c28aaf62fa55f0fdb8004aa40f88f23bf53f0amwnpi_status_t npi_rxdma_rxctl_fifo_error_intr_get(npi_handle_t,
da6c28aaf62fa55f0fdb8004aa40f88f23bf53f0amwnpi_status_t npi_rxdma_rxctl_fifo_error_intr_set(npi_handle_t,
da6c28aaf62fa55f0fdb8004aa40f88f23bf53f0amwnpi_status_t npi_rxdma_dump_rdc_table(npi_handle_t, uint8_t);
da6c28aaf62fa55f0fdb8004aa40f88f23bf53f0amw#endif /* _NPI_RXDMA_H */