npi_rxdma.c revision 678453a8ed49104d8adad58f3ba591bdc39883e8
/*
* CDDL HEADER START
*
* The contents of this file are subject to the terms of the
* Common Development and Distribution License (the "License").
* You may not use this file except in compliance with the License.
*
* You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
* See the License for the specific language governing permissions
* and limitations under the License.
*
* When distributing Covered Code, include this CDDL HEADER in each
* file and include the License file at usr/src/OPENSOLARIS.LICENSE.
* If applicable, add the following below this CDDL HEADER, with the
* fields enclosed by brackets "[]" replaced with your own identifying
* information: Portions Copyright [yyyy] [name of copyright owner]
*
* CDDL HEADER END
*/
/*
* Copyright 2008 Sun Microsystems, Inc. All rights reserved.
* Use is subject to license terms.
*/
#pragma ident "%Z%%M% %I% %E% SMI"
#include <npi_rxdma.h>
#include <npi_rx_rd64.h>
#include <npi_rx_wr64.h>
#include <nxge_common.h>
#define RXDMA_RESET_TRY_COUNT 4
#define RXDMA_RESET_DELAY 5
#define RXDMA_OP_DISABLE 0
#define RXDMA_OP_ENABLE 1
#define RXDMA_OP_RESET 2
#define RCR_TIMEOUT_ENABLE 1
#define RCR_TIMEOUT_DISABLE 2
#define RCR_THRESHOLD 4
/* assume weight is in byte frames unit */
uint64_t rdc_dmc_offset[] = {
};
const char *rdc_dmc_name[] = {
"RXDMA_CFIG1", "RXDMA_CFIG2", "RBR_CFIG_A", "RBR_CFIG_B",
"RBR_KICK", "RBR_STAT", "RBR_HDH", "RBR_HDL",
"RCRCFIG_A", "RCRCFIG_B", "RCRSTAT_A", "RCRSTAT_B",
"RCRSTAT_C", "RX_DMA_ENT_MSK", "RX_DMA_CTL_STAT", "RCR_FLSH",
"RXMISC_DISCARD"
};
uint64_t rdc_fzc_offset [] = {
};
const char *rdc_fzc_name [] = {
"RX_LOG_PAGE_VLD", "RX_LOG_PAGE_MASK1", "RX_LOG_PAGE_VAL1",
"RX_LOG_PAGE_MASK2", "RX_LOG_PAGE_VAL2", "RX_LOG_PAGE_RELO1",
"RX_LOG_PAGE_RELO2", "RX_LOG_PAGE_HDL", "RDC_RED_PARA", "RED_DIS_CNT"
};
/*
* Dump the MEM_ADD register first so all the data registers
* will have valid data buffer pointers.
*/
uint64_t rx_fzc_offset[] = {
};
const char *rx_fzc_name[] = {
"RX_DMA_CK_DIV", "DEF_PT0_RDC", "DEF_PT1_RDC", "DEF_PT2_RDC",
"DEF_PT3_RDC", "RX_ADDR_MD", "PT_DRR_WT0", "PT_DRR_WT1",
"PT_DRR_WT2", "PT_DRR_WT3", "PT_USE0", "PT_USE1",
"PT_USE2", "PT_USE3", "RED_RAN_INIT", "RX_ADDR_MD",
"RDMC_PRE_PAR_ERR", "RDMC_SHA_PAR_ERR",
"RDMC_MEM_DATA4", "RDMC_MEM_DATA3", "RDMC_MEM_DATA2",
"RDMC_MEM_DATA1", "RDMC_MEM_DATA0",
"RDMC_MEM_ADDR",
"RX_CTL_DAT_FIFO_STAT", "RX_CTL_DAT_FIFO_MASK",
"RDMC_TRAINING_VECTOR_REG",
"RX_CTL_DAT_FIFO_STAT_DBG_REG"
};
/*
* npi_rxdma_dump_rdc_regs
* Dumps the contents of rdc csrs and fzc registers
*
* Input:
* handle: opaque handle interpreted by the underlying OS
* rdc: RX DMA number
*
* return:
* NPI_SUCCESS
* NPI_RXDMA_RDC_INVALID
*
*/
{
int num_regs, i;
#ifdef NPI_DEBUG
extern uint64_t npi_debug_level;
#endif
if (!RXDMA_CHANNEL_VALID(rdc)) {
"npi_rxdma_dump_rdc_regs"
" Illegal RDC number %d \n",
rdc));
return (NPI_RXDMA_RDC_INVALID);
}
#ifdef NPI_DEBUG
#endif
"\nDMC Register Dump for Channel %d\n",
rdc));
for (i = 0; i < num_regs; i++) {
rdc);
"%08llx %s\t %08llx \n",
}
"\n Register Dump for Channel %d done\n",
rdc));
#ifdef NPI_DEBUG
#endif
return (NPI_SUCCESS);
}
/*
* npi_rxdma_dump_fzc_regs
* Dumps the contents of rdc csrs and fzc registers
*
* Input:
* handle: opaque handle interpreted by the underlying OS
*
* return:
* NPI_SUCCESS
*/
{
int num_regs, i;
"\nFZC_DMC Common Register Dump\n"));
for (i = 0; i < num_regs; i++) {
"0x%08llx %s\t 0x%08llx \n",
rx_fzc_offset[i],
rx_fzc_name[i], value));
}
"\n FZC_DMC Register Dump Done \n"));
return (NPI_SUCCESS);
}
/*
* per rdc config functions
*/
{
if (!RXDMA_CHANNEL_VALID(rdc)) {
"rxdma_cfg_logical_page_disable"
" Illegal RDC number %d \n",
rdc));
return (NPI_RXDMA_RDC_INVALID);
}
if (!RXDMA_PAGE_VALID(page_num)) {
"rxdma_cfg_logical_page_disable"
" Illegal page number %d \n",
page_num));
return (NPI_RXDMA_PAGE_INVALID);
}
if (page_num == 0)
if (page_num == 1)
return (NPI_SUCCESS);
}
{
if (!RXDMA_CHANNEL_VALID(rdc)) {
" rxdma_cfg_logical_page"
" Illegal RDC number %d \n",
rdc));
return (NPI_RXDMA_RDC_INVALID);
}
" rxdma_cfg_logical_page"
" Illegal page number %d \n",
return (NPI_RXDMA_PAGE_INVALID);
}
return (NPI_SUCCESS);
}
}
}
page_value.value = 0;
page_reloc.value = 0;
/* enable the logical page */
return (NPI_SUCCESS);
}
{
if (!RXDMA_CHANNEL_VALID(rdc)) {
"rxdma_cfg_logical_page_handle"
" Illegal RDC number %d \n", rdc));
return (NPI_RXDMA_RDC_INVALID);
}
return (NPI_SUCCESS);
}
/*
* RX DMA functions
*/
{
if (!RXDMA_CHANNEL_VALID(rdc)) {
"npi_rxdma_cfg_rdc_ctl"
" Illegal RDC number %d \n", rdc));
return (NPI_RXDMA_RDC_INVALID);
}
switch (op) {
case RXDMA_OP_ENABLE:
}
" npi_rxdma_cfg_rdc_ctl"
" RXDMA_OP_ENABLE Failed for RDC %d \n",
rdc));
return (error);
}
break;
case RXDMA_OP_DISABLE:
}
" npi_rxdma_cfg_rdc_ctl"
" RXDMA_OP_DISABLE Failed for RDC %d \n",
rdc));
return (error);
}
break;
case RXDMA_OP_RESET:
}
if (count == 0) {
" npi_rxdma_cfg_rdc_ctl"
" Reset Failed for RDC %d \n",
rdc));
return (error);
}
break;
default:
return (NPI_RXDMA_SW_PARAM_ERROR);
}
return (NPI_SUCCESS);
}
{
}
{
}
{
}
/*
* npi_rxdma_cfg_defualt_port_rdc()
* Set the default rdc for the port
*
* Inputs:
* handle: register handle interpreted by the underlying OS
* portnm: Physical Port Number
* rdc: RX DMA Channel number
*
* Return:
* NPI_SUCCESS
* NPI_RXDMA_RDC_INVALID
* NPI_RXDMA_PORT_INVALID
*
*/
{
if (!RXDMA_CHANNEL_VALID(rdc)) {
"rxdma_cfg_default_port_rdc"
" Illegal RDC number %d \n",
rdc));
return (NPI_RXDMA_RDC_INVALID);
}
if (!RXDMA_PORT_VALID(portnm)) {
"rxdma_cfg_default_port_rdc"
" Illegal Port number %d \n",
portnm));
return (NPI_RXDMA_PORT_INVALID);
}
return (NPI_SUCCESS);
}
{
if (!RXDMA_CHANNEL_VALID(rdc)) {
"rxdma_cfg_rdc_rcr_ctl"
" Illegal RDC number %d \n",
rdc));
return (NPI_RXDMA_RDC_INVALID);
}
switch (op) {
case RCR_TIMEOUT_ENABLE:
break;
case RCR_THRESHOLD:
break;
case RCR_TIMEOUT_DISABLE:
break;
default:
"rxdma_cfg_rdc_rcr_ctl"
" Illegal opcode %x \n",
op));
return (NPI_RXDMA_OPCODE_INVALID(rdc));
}
return (NPI_SUCCESS);
}
{
RCR_TIMEOUT_DISABLE, 0));
}
{
}
{
}
/*
* npi_rxdma_cfg_rdc_ring()
* Configure The RDC channel Rcv Buffer Ring
*/
{
if (!RXDMA_CHANNEL_VALID(rdc)) {
"rxdma_cfg_rdc_ring"
" Illegal RDC number %d \n",
rdc));
return (NPI_RXDMA_RDC_INVALID);
}
((rdc_desc_cfg->mbox_addr &
/*
* Only after all the configurations are set, then
* enable the RDC or else configuration fatal error
* will be returned (especially if the Hypervisor
* set up the logical pages with non-zero values.
* This NPI function only sets up the configuration.
*/
}
} else {
}
/* rbr config */
"npi_rxdma_cfg_rdc_ring"
" Illegal RBR Queue Length %d \n",
rdc_desc_cfg->rbr_len));
}
"npi_rxdma_cfg_rdc_ring"
" CFGA 0x%llx hdw.len %d (RBR LEN %d)\n",
rdc_desc_cfg->rbr_len));
else {
"rxdma_cfg_rdc_ring"
" blksize: Illegal buffer size %d \n",
return (NPI_RXDMA_BUFSIZE_INVALID);
}
if (rdc_desc_cfg->valid0) {
else {
" rxdma_cfg_rdc_ring"
" blksize0: Illegal buffer size %x \n",
rdc_desc_cfg->size0));
return (NPI_RXDMA_BUFSIZE_INVALID);
}
} else {
}
if (rdc_desc_cfg->valid1) {
else {
" rxdma_cfg_rdc_ring"
" blksize1: Illegal buffer size %x \n",
rdc_desc_cfg->size1));
return (NPI_RXDMA_BUFSIZE_INVALID);
}
} else {
}
if (rdc_desc_cfg->valid2) {
else {
" rxdma_cfg_rdc_ring"
" blksize2: Illegal buffer size %x \n",
rdc_desc_cfg->size2));
return (NPI_RXDMA_BUFSIZE_INVALID);
}
} else {
}
" rxdma_cfg_rdc_ring"
" Illegal RCR Queue Length %d \n",
rdc_desc_cfg->rcr_len));
}
/* check if the rcr timeout value is valid */
} else {
" rxdma_cfg_rdc_ring"
" Illegal RCR Timeout value %d \n",
}
} else {
}
/* check if the rcr threshold value is valid */
} else {
" rxdma_cfg_rdc_ring"
" Illegal RCR Threshold value %d \n",
}
/* now do the actual HW configuration */
return (NPI_SUCCESS);
}
/*
* npi_rxdma_red_discard_stat_get
* Gets the current discrad count due RED
* The counter overflow bit is cleared, if it has been set.
*
* Inputs:
* handle: opaque handle interpreted by the underlying OS
* rdc: RX DMA Channel number
* cnt: Ptr to structure to write current RDC discard stat
*
* Return:
* NPI_SUCCESS
* NPI_RXDMA_RDC_INVALID
*
*/
{
if (!RXDMA_CHANNEL_VALID(rdc)) {
" npi_rxdma_red_discard_stat_get"
" Illegal RDC Number %d \n",
rdc));
return (NPI_RXDMA_RDC_INVALID);
}
" npi_rxdma_red_discard_stat_get"
" Counter overflow for channel %d ",
" ..... clearing \n",
rdc));
}
return (NPI_SUCCESS);
}
/*
* npi_rxdma_red_discard_oflow_clear
* Clear RED discard counter overflow bit
*
* Inputs:
* handle: opaque handle interpreted by the underlying OS
* rdc: RX DMA Channel number
*
* Return:
* NPI_SUCCESS
* NPI_RXDMA_RDC_INVALID
*
*/
{
if (!RXDMA_CHANNEL_VALID(rdc)) {
" npi_rxdma_red_discard_oflow_clear"
" Illegal RDC Number %d \n",
rdc));
return (NPI_RXDMA_RDC_INVALID);
}
" npi_rxdma_red_discard_oflow_clear"
" Counter overflow for channel %d ",
" ..... clearing \n",
rdc));
}
return (NPI_SUCCESS);
}
/*
* npi_rxdma_misc_discard_stat_get
* Gets the current discrad count for the rdc due to
* buffer pool empty
* The counter overflow bit is cleared, if it has been set.
*
* Inputs:
* handle: opaque handle interpreted by the underlying OS
* rdc: RX DMA Channel number
* cnt: Ptr to structure to write current RDC discard stat
*
* Return:
* NPI_SUCCESS
* NPI_RXDMA_RDC_INVALID
*
*/
{
if (!RXDMA_CHANNEL_VALID(rdc)) {
" npi_rxdma_misc_discard_stat_get"
" Illegal RDC Number %d \n",
rdc));
return (NPI_RXDMA_RDC_INVALID);
}
" npi_rxdma_misc_discard_stat_get"
" Counter overflow for channel %d ",
" ..... clearing \n",
rdc));
}
return (NPI_SUCCESS);
}
/*
* npi_rxdma_red_discard_oflow_clear
* Clear RED discard counter overflow bit
* clear the overflow bit for buffer pool empty discrad counter
* for the rdc
*
* Inputs:
* handle: opaque handle interpreted by the underlying OS
* rdc: RX DMA Channel number
*
* Return:
* NPI_SUCCESS
* NPI_RXDMA_RDC_INVALID
*
*/
{
if (!RXDMA_CHANNEL_VALID(rdc)) {
" npi_rxdma_misc_discard_oflow_clear"
" Illegal RDC Number %d \n",
rdc));
return (NPI_RXDMA_RDC_INVALID);
}
" npi_rxdma_misc_discard_oflow_clear"
" Counter overflow for channel %d ",
" ..... clearing \n",
rdc));
}
return (NPI_SUCCESS);
}
/*
* npi_rxdma_ring_perr_stat_get
* Gets the current RDC Memory parity error
* The counter overflow bit is cleared, if it has been set.
*
* Inputs:
* handle: opaque handle interpreted by the underlying OS
* pre_log: Structure to write current RDC Prefetch memory
* Parity Error stat
* sha_log: Structure to write current RDC Shadow memory
* Parity Error stat
*
* Return:
* NPI_SUCCESS
*
*/
{
int clr_bits = 0;
" npi_rxdma_ring_perr_stat_get"
" PRE ERR Bit set ..... clearing \n"));
clr_bits++;
}
" npi_rxdma_ring_perr_stat_get"
" PRE MERR Bit set ..... clearing \n"));
clr_bits++;
}
if (clr_bits) {
}
clr_bits = 0;
" npi_rxdma_ring_perr_stat_get"
" SHA ERR Bit set ..... clearing \n"));
clr_bits++;
}
" npi_rxdma_ring_perr_stat_get"
" SHA MERR Bit set ..... clearing \n"));
clr_bits++;
}
if (clr_bits) {
}
return (NPI_SUCCESS);
}
/*
* npi_rxdma_ring_perr_stat_clear
* Clear RDC Memory Parity Error counter overflow bits
*
* Inputs:
* handle: opaque handle interpreted by the underlying OS
* Return:
* NPI_SUCCESS
*
*/
{
int clr_bits = 0;
" npi_rxdma_ring_perr_stat_get"
" PRE ERR Bit set ..... clearing \n"));
clr_bits++;
}
" npi_rxdma_ring_perr_stat_get"
" PRE MERR Bit set ..... clearing \n"));
clr_bits++;
}
if (clr_bits) {
}
clr_bits = 0;
" npi_rxdma_ring_perr_stat_get"
" SHA ERR Bit set ..... clearing \n"));
clr_bits++;
}
" npi_rxdma_ring_perr_stat_get"
" SHA MERR Bit set ..... clearing \n"));
clr_bits++;
}
if (clr_bits) {
}
return (NPI_SUCCESS);
}
/*
* Access the RDMC Memory: used for debugging
*/
{
" npi_rxdma_rdmc_memory_io"
" Illegal memory Type %x \n",
return (NPI_RXDMA_OPCODE_INVALID(0));
}
if (op == RDMC_MEM_WRITE) {
}
if (op == RDMC_MEM_READ) {
} else {
" npi_rxdma_rdmc_memory_io"
" Illegal opcode %x \n",
op));
return (NPI_RXDMA_OPCODE_INVALID(0));
}
return (NPI_SUCCESS);
}
/*
* system wide conf functions
*/
{
" npi_rxdma_cfg_clock_div_set: add 0x%llx "
"handle 0x%llx value 0x%llx",
return (NPI_SUCCESS);
}
{
return (NPI_SUCCESS);
}
{
return (NPI_SUCCESS);
}
{
return (NPI_SUCCESS);
}
{
return (NPI_SUCCESS);
}
{
return (NPI_SUCCESS);
}
{
return (NPI_SUCCESS);
}
{
if (!RXDMA_PORT_VALID(portnm)) {
" rxdma_cfg_port_ddr_weight"
" Illegal Port Number %d \n",
portnm));
return (NPI_RXDMA_PORT_INVALID);
}
return (NPI_SUCCESS);
}
{
if (!RXDMA_PORT_VALID(portnm)) {
" rxdma_port_usage_get"
" Illegal Port Number %d \n",
portnm));
return (NPI_RXDMA_PORT_INVALID);
}
return (NPI_SUCCESS);
}
{
if (!RXDMA_CHANNEL_VALID(rdc)) {
" rxdma_cfg_wred_param"
" Illegal RDC Number %d \n",
rdc));
return (NPI_RXDMA_RDC_INVALID);
}
/*
* need to update RDC_RED_PARA_REG as well as bit defs in
* the hw header file
*/
" npi_rxdma_cfg_wred_param: "
"set RED_PARA: passed value 0x%llx "
"win 0x%x thre 0x%x sync 0x%x thre_sync 0x%x",
"set RED_PARA: value 0x%llx "
"win 0x%x thre 0x%x sync 0x%x thre_sync 0x%x",
return (NPI_SUCCESS);
}
/*
* npi_rxdma_rdc_table_config()
*
* Inputs:
* handle: register handle interpreted by the underlying OS
* table: RDC Group Number
* map: A bitmap of the RDCs to populate with.
* count: A count of the RDCs expressed in <map>.
*
* Notes:
* This function assumes that we are not using the TCAM, but are
* hashing all fields of the incoming ethernet packet!
*
* Return:
* NPI_SUCCESS
* NPI_RXDMA_TABLE_INVALID
*
*/
int count)
{
int i, cursor;
if (!RXDMA_TABLE_VALID(table)) {
" npi_rxdma_cfg_rdc_table"
" Illegal RDC Table Number %d \n",
table));
return (NPI_RXDMA_TABLE_INVALID);
}
if (count == 0) /* This shouldn't happen */
return (NPI_SUCCESS);
for (i = 0, cursor = 0; i < NXGE_MAX_RDCS; i++) {
if ((1 << i) & rdc_map) {
break;
}
}
/* Now write ( NXGE_MAX_RDCS / count ) sets of RDC numbers. */
for (i = 0, cursor = 0; i < NXGE_MAX_RDCS; i++) {
cursor = 0;
}
/*
* Here is what the resulting table looks like with:
*
* 0 1 2 3 4 5 6 7 8 9 a b c d e f
* +--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+
* |v |w |x |y |z |v |w |x |y |z |v |w |x |y |z |v | 5 RDCs
* +--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+
* |w |x |y |z |w |x |y |z |w |x |y |z |w |x |y |z | 4 RDCs
* +--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+
* |x |y |z |x |y |z |x |y |z |x |y |z |x |y |z |x | 3 RDCs
* +--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+
* |x |y |x |y |x |y |x |y |x |y |x |y |x |y |x |y | 2 RDCs
* +--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+
* |x |x |x |x |x |x |x |x |x |x |x |x |x |x |x |x | 1 RDC
* +--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+
*/
return (NPI_SUCCESS);
}
{
if (!RXDMA_TABLE_VALID(table)) {
" npi_rxdma_cfg_rdc_table"
" Illegal RDC table Number %d \n",
rdc));
return (NPI_RXDMA_TABLE_INVALID);
}
return (NPI_SUCCESS);
}
{
int tbl_offset;
if (!RXDMA_TABLE_VALID(table)) {
" npi_rxdma_dump_rdc_table"
" Illegal RDC Rable Number %d \n",
table));
return (NPI_RXDMA_TABLE_INVALID);
}
"\n Register Dump for RDC Table %d \n",
table));
" 0x%08llx 0x%08llx \n",
offset += 8;
}
"\n Register Dump for RDC Table %d done\n",
table));
return (NPI_SUCCESS);
}
{
if (!RXDMA_CHANNEL_VALID(rdc)) {
" rxdma_rdc_rbr_stat_get"
" Illegal RDC Number %d \n",
rdc));
return (NPI_RXDMA_RDC_INVALID);
}
return (NPI_SUCCESS);
}
/*
* npi_rxdma_rdc_rbr_head_get
* Gets the current rbr head pointer.
*
* Inputs:
* handle: opaque handle interpreted by the underlying OS
* rdc: RX DMA Channel number
* hdptr ptr to write the rbr head value
*
* Return:
* NPI_SUCCESS
* NPI_RXDMA_RDC_INVALID
*/
{
if (!RXDMA_CHANNEL_VALID(rdc)) {
" rxdma_rdc_rbr_head_get"
" Illegal RDC Number %d \n",
rdc));
return (NPI_RXDMA_RDC_INVALID);
}
return (NPI_SUCCESS);
}
{
if (!RXDMA_CHANNEL_VALID(rdc)) {
" rxdma_rdc_rcr_qlen_get"
" Illegal RDC Number %d \n",
rdc));
return (NPI_RXDMA_RDC_INVALID);
}
" rxdma_rdc_rcr_qlen_get"
" RDC %d qlen %x qlen %x\n",
return (NPI_SUCCESS);
}
{
if (!RXDMA_CHANNEL_VALID(rdc)) {
" rxdma_rdc_rcr_tail_get"
" Illegal RDC Number %d \n",
rdc));
return (NPI_RXDMA_RDC_INVALID);
}
" rxdma_rdc_rcr_tail_get"
" RDC %d rcr_tail %llx tl %x\n",
return (NPI_SUCCESS);
}
/*
* npi_rxdma_rxctl_fifo_error_intr_set
* Configure The RX ctrl fifo error interrupt generation
*
* Inputs:
* handle: opaque handle interpreted by the underlying OS
* mask: rx_ctl_dat_fifo_mask_t specifying the errors
* valid fields in rx_ctl_dat_fifo_mask_t structure are:
* zcp_eop_err, ipp_eop_err, id_mismatch. If a field is set
* to 1, we will enable interrupt generation for the
* corresponding error condition. In the hardware, the bit(s)
* have to be cleared to enable interrupt.
*
* Return:
* NPI_SUCCESS
*
*/
{
}
}
}
return (NPI_SUCCESS);
}
/*
* npi_rxdma_rxctl_fifo_error_stat_get
* Read The RX ctrl fifo error Status
*
* Inputs:
* handle: opaque handle interpreted by the underlying OS
* stat: rx_ctl_dat_fifo_stat_t to read the errors to
* valid fields in rx_ctl_dat_fifo_stat_t structure are:
* zcp_eop_err, ipp_eop_err, id_mismatch.
* Return:
* NPI_SUCCESS
*
*/
{
return (NPI_SUCCESS);
}
{
if (!RXDMA_CHANNEL_VALID(channel)) {
" npi_rxdma_rdc_rcr_pktread_update ",
" channel %d", channel));
}
" npi_rxdma_rdc_rcr_pktread_update ",
" pkts %d out of bound", pkts_read));
return (NPI_RXDMA_OPCODE_INVALID(pkts_read));
}
return (NPI_SUCCESS);
}
{
if (!RXDMA_CHANNEL_VALID(channel)) {
" npi_rxdma_rdc_rcr_bufread_update ",
" channel %d", channel));
}
" npi_rxdma_rdc_rcr_bufread_update ",
" bufs read %d out of bound", bufs_read));
return (NPI_RXDMA_OPCODE_INVALID(bufs_read));
}
return (NPI_SUCCESS);
}
{
if (!RXDMA_CHANNEL_VALID(channel)) {
" npi_rxdma_rdc_rcr_read_update ",
" channel %d", channel));
}
" npi_rxdma_rdc_rcr_read_update "
" bufs read %d pkt read %d",
" npi_rxdma_rdc_rcr_read_update: "
" value: 0x%llx bufs read %d pkt read %d",
" npi_rxdma_rdc_rcr_read_update: read back after update "
" value: 0x%llx bufs read %d pkt read %d",
return (NPI_SUCCESS);
}
/*
* npi_rxdma_channel_mex_set():
* This function is called to arm the DMA channel with
* mailbox updating capability. Software needs to rearm
* for each update by writing to the control and status register.
*
* Parameters:
* handle - NPI handle (virtualization flag must be defined).
* channel - logical RXDMA channel from 0 to 23.
* (If virtualization flag is not set, then
* logical channel is the same as the hardware
* channel number).
*
* Return:
* NPI_SUCCESS - If enable channel with mailbox update
* is completed successfully.
*
* Error:
* NPI error status code
*/
{
}
/*
* npi_rxdma_channel_rcrto_clear():
* This function is called to reset RCRTO bit to 0.
*
* Parameters:
* handle - NPI handle (virtualization flag must be defined).
* channel - logical RXDMA channel from 0 to 23.
* (If virtualization flag is not set, then
* logical channel is the same as the hardware
* channel number).
* Return:
* NPI_SUCCESS
*
* Error:
* NPI error status code
*/
{
}
/*
* npi_rxdma_channel_pt_drop_pkt_clear():
* This function is called to clear the port drop packet bit (debug).
*
* Parameters:
* handle - NPI handle (virtualization flag must be defined).
* channel - logical RXDMA channel from 0 to 23.
* (If virtualization flag is not set, then
* logical channel is the same as the hardware
* channel number).
* Return:
* NPI_SUCCESS
*
* Error:
* NPI error status code
*/
{
channel));
}
/*
* npi_rxdma_channel_wred_drop_clear():
* This function is called to wred drop bit (debug only).
*
* Parameters:
* handle - NPI handle (virtualization flag must be defined).
* channel - logical RXDMA channel from 0 to 23.
* (If virtualization flag is not set, then
* logical channel is the same as the hardware
* channel number).
* Return:
* NPI_SUCCESS
*
* Error:
* NPI error status code
*/
{
channel));
}
/*
* npi_rxdma_channel_rcr_shfull_clear():
* This function is called to clear RCR shadow full bit.
*
* Parameters:
* handle - NPI handle (virtualization flag must be defined).
* channel - logical RXDMA channel from 0 to 23.
* (If virtualization flag is not set, then
* logical channel is the same as the hardware
* channel number).
* Return:
* NPI_SUCCESS
*
* Error:
* NPI error status code
*/
{
channel));
}
/*
* npi_rxdma_channel_rcrfull_clear():
* This function is called to clear RCR full bit.
*
* Parameters:
* handle - NPI handle (virtualization flag must be defined).
* channel - logical RXDMA channel from 0 to 23.
* (If virtualization flag is not set, then
* logical channel is the same as the hardware
* channel number).
* Return:
* NPI_SUCCESS
*
* Error:
* NPI error status code
*/
{
channel));
}
{
return (npi_rxdma_channel_control(handle,
}
{
}
/*
* npi_rxdma_channel_control():
* This function is called to control a receive DMA channel
* for arming the channel with mailbox updates, resetting
* various event status bits (control and status register).
*
* Parameters:
* handle - NPI handle (virtualization flag must be defined).
* control - NPI defined control type supported:
* - RXDMA_MEX_SET
* - RXDMA_RCRTO_CLEAR
* - RXDMA_PT_DROP_PKT_CLEAR
* - RXDMA_WRED_DROP_CLEAR
* - RXDMA_RCR_SFULL_CLEAR
* - RXDMA_RCR_FULL_CLEAR
* - RXDMA_RBR_PRE_EMPTY_CLEAR
* - RXDMA_RBR_EMPTY_CLEAR
* channel - logical RXDMA channel from 0 to 23.
* (If virtualization flag is not set, then
* logical channel is the same as the hardware.
* Return:
* NPI_SUCCESS
*
* Error:
* NPI error status code
*/
{
if (!RXDMA_CHANNEL_VALID(channel)) {
" npi_rxdma_channel_control",
" channel", channel));
}
switch (control) {
case RXDMA_MEX_SET:
break;
case RXDMA_RCRTO_CLEAR:
break;
case RXDMA_PT_DROP_PKT_CLEAR:
break;
case RXDMA_WRED_DROP_CLEAR:
break;
case RXDMA_RCR_SFULL_CLEAR:
break;
case RXDMA_RCR_FULL_CLEAR:
break;
break;
case RXDMA_RBR_EMPTY_CLEAR:
break;
case RXDMA_CS_CLEAR_ALL:
break;
default:
"npi_rxdma_channel_control",
"control", control));
}
return (NPI_SUCCESS);
}
/*
* npi_rxdma_control_status():
* This function is called to operate on the control
* and status register.
*
* Parameters:
* handle - NPI handle
* op_mode - OP_GET: get hardware control and status
* OP_SET: set hardware control and status
* OP_UPDATE: update hardware control and status.
* OP_CLEAR: clear control and status register to 0s.
* channel - hardware RXDMA channel from 0 to 23.
* cs_p - pointer to hardware defined control and status
* structure.
* Return:
* NPI_SUCCESS
*
* Error:
* NPI error status code
*/
{
int status = NPI_SUCCESS;
if (!RXDMA_CHANNEL_VALID(channel)) {
"npi_rxdma_control_status",
"channel", channel));
}
switch (op_mode) {
case OP_GET:
break;
case OP_SET:
break;
case OP_UPDATE:
break;
default:
"npi_rxdma_control_status",
"control", op_mode));
}
return (status);
}
/*
* npi_rxdma_event_mask():
* This function is called to operate on the event mask
* register which is used for generating interrupts.
*
* Parameters:
* handle - NPI handle
* op_mode - OP_GET: get hardware event mask
* OP_SET: set hardware interrupt event masks
* OP_CLEAR: clear control and status register to 0s.
* channel - hardware RXDMA channel from 0 to 23.
* mask_p - pointer to hardware defined event mask
* structure.
* Return:
* NPI_SUCCESS - If set is complete successfully.
*
* Error:
* NPI error status code
*/
{
int status = NPI_SUCCESS;
if (!RXDMA_CHANNEL_VALID(channel)) {
"npi_rxdma_event_mask",
"channel", channel));
}
switch (op_mode) {
case OP_GET:
break;
case OP_SET:
break;
case OP_UPDATE:
break;
default:
"npi_rxdma_event_mask",
"eventmask", op_mode));
}
return (status);
}
/*
* npi_rxdma_event_mask_config():
* This function is called to operate on the event mask
* register which is used for generating interrupts
* and status register.
*
* Parameters:
* handle - NPI handle
* op_mode - OP_GET: get hardware event mask
* OP_SET: set hardware interrupt event masks
* OP_CLEAR: clear control and status register to 0s.
* channel - hardware RXDMA channel from 0 to 23.
* mask_cfgp - pointer to NPI defined event mask
* enum data type.
* Return:
* NPI_SUCCESS - If set is complete successfully.
*
* Error:
* NPI error status code
*/
{
int status = NPI_SUCCESS;
if (!RXDMA_CHANNEL_VALID(channel)) {
"npi_rxdma_event_mask_config",
"channel", channel));
}
switch (op_mode) {
case OP_GET:
break;
case OP_SET:
break;
case OP_UPDATE:
configuration | value);
break;
case OP_CLEAR:
break;
default:
"npi_rxdma_event_mask_config",
"eventmask", op_mode));
}
return (status);
}