npi_ipp.c revision d710877a882793772862760e3df660935734018d
/*
* CDDL HEADER START
*
* The contents of this file are subject to the terms of the
* Common Development and Distribution License (the "License").
* You may not use this file except in compliance with the License.
*
* You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
* See the License for the specific language governing permissions
* and limitations under the License.
*
* When distributing Covered Code, include this CDDL HEADER in each
* file and include the License file at usr/src/OPENSOLARIS.LICENSE.
* If applicable, add the following below this CDDL HEADER, with the
* fields enclosed by brackets "[]" replaced with your own identifying
* information: Portions Copyright [yyyy] [name of copyright owner]
*
* CDDL HEADER END
*/
/*
* Copyright 2007 Sun Microsystems, Inc. All rights reserved.
* Use is subject to license terms.
*/
#pragma ident "%Z%%M% %I% %E% SMI"
#include <npi_ipp.h>
uint64_t ipp_fzc_offset[] = {
};
const char *ipp_fzc_name[] = {
"IPP_CONFIG_REG",
"IPP_DISCARD_PKT_CNT_REG",
"IPP_TCP_CKSUM_ERR_CNT_REG",
"IPP_ECC_ERR_COUNTER_REG",
"IPP_INT_STATUS_REG",
"IPP_INT_MASK_REG",
"IPP_PFIFO_RD_DATA0_REG",
"IPP_PFIFO_RD_DATA1_REG",
"IPP_PFIFO_RD_DATA2_REG",
"IPP_PFIFO_RD_DATA3_REG",
"IPP_PFIFO_RD_DATA4_REG",
"IPP_PFIFO_WR_DATA0_REG",
"IPP_PFIFO_WR_DATA1_REG",
"IPP_PFIFO_WR_DATA2_REG",
"IPP_PFIFO_WR_DATA3_REG",
"IPP_PFIFO_WR_DATA4_REG",
"IPP_PFIFO_RD_PTR_REG",
"IPP_PFIFO_WR_PTR_REG",
"IPP_DFIFO_RD_DATA0_REG",
"IPP_DFIFO_RD_DATA1_REG",
"IPP_DFIFO_RD_DATA2_REG",
"IPP_DFIFO_RD_DATA3_REG",
"IPP_DFIFO_RD_DATA4_REG",
"IPP_DFIFO_WR_DATA0_REG",
"IPP_DFIFO_WR_DATA1_REG",
"IPP_DFIFO_WR_DATA2_REG",
"IPP_DFIFO_WR_DATA3_REG",
"IPP_DFIFO_WR_DATA4_REG",
"IPP_DFIFO_RD_PTR_REG",
"IPP_DFIFO_WR_PTR_REG",
"IPP_STATE_MACHINE_REG",
"IPP_CKSUM_STATUS_REG",
"IPP_FFLP_CKSUM_INFO_REG",
"IPP_DEBUG_SELECT_REG",
"IPP_DFIFO_ECC_SYNDROME_REG",
"IPP_DFIFO_EOPM_RD_PTR_REG",
"IPP_ECC_CTRL_REG",
};
{
int num_regs, i;
"\nIPP PORT Register Dump for port %d\n", port));
for (i = 0; i < num_regs; i++) {
#if defined(__i386)
#else
#endif
"%s\t 0x%08llx \n",
}
"\n IPP FZC Register Dump for port %d done\n", port));
return (NPI_SUCCESS);
}
void
{
int num_regs, i;
"\nIPP PORT Register read (to clear) for port %d\n", port));
for (i = 0; i < num_regs; i++) {
#if defined(__i386)
#else
#endif
}
}
/*
* IPP Reset Routine
*/
{
val |= IPP_SOFT_RESET;
do {
cnt--;
if (cnt == 0) {
" npi_ipp_reset"
" HW Error: IPP_RESET <0x%x>", val));
}
return (NPI_SUCCESS);
}
/*
* IPP Configuration Routine
*/
{
switch (op) {
case ENABLE:
case DISABLE:
" npi_ipp_config",
" Invalid Input config <0x%x>",
config));
}
else
break;
case INIT:
if ((config & ~CFG_IPP_ALL) != 0) {
" npi_ipp_config"
" Invalid Input config <0x%x>",
config));
}
val &= (IPP_IP_MAX_PKT_BYTES_MASK);
break;
default:
" npi_ipp_config"
" Invalid Input op <0x%x>", op));
}
return (NPI_SUCCESS);
}
{
if (bytes > IPP_IP_MAX_PKT_BYTES_MASK) {
" npi_ipp_set_max_pktsize"
" Invalid Input Max bytes <0x%x>",
bytes));
}
return (NPI_SUCCESS);
}
/*
* IPP Interrupt Configuration Routine
*/
{
switch (op) {
case ENABLE:
case DISABLE:
" npi_ipp_iconfig"
" Invalid Input iconfig <0x%x>",
iconfig));
}
else
break;
case INIT:
if ((iconfig & ~ICFG_IPP_ALL) != 0) {
" npi_ipp_iconfig"
" Invalid Input iconfig <0x%x>",
iconfig));
}
break;
default:
" npi_ipp_iconfig"
" Invalid Input iconfig <0x%x>",
iconfig));
}
return (NPI_SUCCESS);
}
{
return (NPI_SUCCESS);
}
{
return (NPI_SUCCESS);
}
{
return (NPI_SUCCESS);
}
{
return (NPI_SUCCESS);
}
{
return (NPI_SUCCESS);
}
{
if (addr >= 64) {
" npi_ipp_write_pfifo"
" Invalid PFIFO address <0x%x>", addr));
}
return (NPI_SUCCESS);
}
{
if (addr >= 64) {
" npi_ipp_read_pfifo"
" Invalid PFIFO address <0x%x>", addr));
}
return (NPI_SUCCESS);
}
{
if (addr >= 2048) {
" npi_ipp_write_dfifo"
" Invalid DFIFO address <0x%x>", addr));
}
val &= ~IPP_DFIFO_PIO_WR_EN;
return (NPI_SUCCESS);
}
{
if (addr >= 2048) {
" npi_ipp_read_dfifo"
" Invalid DFIFO address <0x%x>", addr));
}
return (NPI_SUCCESS);
}
{
return (NPI_SUCCESS);
}
{
return (NPI_SUCCESS);
}
{
return (NPI_SUCCESS);
}
{
return (NPI_SUCCESS);
}
{
return (NPI_SUCCESS);
}
{
return (NPI_SUCCESS);
}