nvme_reg.h revision 24979ca36afa68d08e082148fcbf4c5dc73f7849
/*
* This file and its contents are supplied under the terms of the
* Common Development and Distribution License ("CDDL"), version 1.0.
* You may only use this file in accordance with the terms of version
* 1.0 of the CDDL.
*
* A full copy of the text of the CDDL should have accompanied this
* source. A copy of the CDDL is also available via the Internet at
*/
/*
* Copyright 2016 Nexenta Systems, Inc. All rights reserved.
*/
/*
* NVMe hardware interface
*/
#ifndef _NVME_REG_H
#define _NVME_REG_H
#pragma pack(1)
#ifdef __cplusplus
extern "C" {
#endif
/*
* NVMe constants
*/
#define NVME_MAX_ADMIN_QUEUE_LEN 4096
/*
* NVMe version
*/
typedef struct {
/*
* NVMe registers and register fields
*/
#define NVME_REG_SQTDBL(nvme, n) \
#define NVME_REG_CQHDBL(nvme, n) \
/* CAP -- Controller Capabilities */
typedef union {
struct {
} b;
uint64_t r;
/* VS -- Version */
typedef union {
struct {
} b;
uint32_t r;
/* CC -- Controller Configuration */
typedef union {
struct {
} b;
uint32_t r;
/* CSTS -- Controller Status */
typedef union {
struct {
} b;
uint32_t r;
/* NSSR -- NVM Subsystem Reset */
typedef uint32_t nvme_reg_nssr_t;
/* AQA -- Admin Queue Attributes */
typedef union {
struct {
} b;
uint32_t r;
/*
* The spec specifies the lower 12 bits of ASQ and ACQ as reserved, which is
* probably a specification bug. The full 64bit regs are used as base address,
* and the lower bits must be zero to ensure alignment on the page size
* specified in CC.MPS.
*/
/* ASQ -- Admin Submission Queue Base Address */
/* ACQ -- Admin Completion Queue Base Address */
/* SQyTDBL -- Submission Queue y Tail Doorbell */
typedef union {
struct {
} b;
uint32_t r;
/* CQyHDBL -- Completion Queue y Head Doorbell */
typedef union {
struct {
} b;
uint32_t r;
/*
* NVMe submission queue entries
*/
typedef struct {
} nvme_sgl_t;
/* NVMe SGL descriptor type */
#define NVME_SGL_DATA_BLOCK 0
#define NVME_SGL_BIT_BUCKET 1
#define NVME_SGL_SEGMENT 2
#define NVME_SGL_LAST_SEGMENT 3
#define NVME_SGL_VENDOR 0xf
/* NVMe submission queue entry */
typedef struct {
union {
} sqe_m;
union {
} sqe_dptr; /* Data Pointer */
} nvme_sqe_t;
/* NVMe admin command opcodes */
#define NVME_OPC_DELETE_SQUEUE 0x0
#define NVME_OPC_CREATE_SQUEUE 0x1
#define NVME_OPC_GET_LOG_PAGE 0x2
#define NVME_OPC_DELETE_CQUEUE 0x4
#define NVME_OPC_CREATE_CQUEUE 0x5
#define NVME_OPC_IDENTIFY 0x6
#define NVME_OPC_ABORT 0x8
#define NVME_OPC_SET_FEATURES 0x9
#define NVME_OPC_GET_FEATURES 0xa
#define NVME_OPC_ASYNC_EVENT 0xc
#define NVME_OPC_FW_ACTIVATE 0x10
#define NVME_OPC_FW_IMAGE_LOAD 0x11
/* NVMe NVM command set specific admin command opcodes */
#define NVME_OPC_NVM_FORMAT 0x80
#define NVME_OPC_NVM_SEC_SEND 0x81
#define NVME_OPC_NVM_SEC_RECV 0x82
/* NVMe NVM command opcodes */
#define NVME_OPC_NVM_FLUSH 0x0
#define NVME_OPC_NVM_WRITE 0x1
#define NVME_OPC_NVM_READ 0x2
#define NVME_OPC_NVM_WRITE_UNC 0x4
#define NVME_OPC_NVM_COMPARE 0x5
#define NVME_OPC_NVM_WRITE_ZERO 0x8
#define NVME_OPC_NVM_DSET_MGMT 0x9
#define NVME_OPC_NVM_RESV_REG 0xd
#define NVME_OPC_NVM_RESV_REPRT 0xe
#define NVME_OPC_NVM_RESV_ACQ 0x11
#define NVME_OPC_NVM_RESV_REL 0x12
/*
* NVMe completion queue entry
*/
typedef struct {
typedef struct {
} nvme_cqe_t;
/* NVMe completion status code type */
#define NVME_CQE_SCT_GENERIC 0 /* Generic Command Status */
/* NVMe completion status code (generic) */
/* NVMe completion status code (generic NVM commands) */
/* NVMe completion status code (command specific) */
/* NVMe completion status code (NVM command specific */
/* NVMe completion status code (data / metadata integrity) */
/*
* NVMe Asynchronous Event Request
*/
typedef union {
struct {
} b;
uint32_t r;
/*
* NVMe Create Completion/Submission Queue
*/
typedef union {
struct {
} b;
uint32_t r;
typedef union {
struct {
} b;
uint32_t r;
typedef union {
struct {
} b;
uint32_t r;
/*
* NVMe Identify
*/
/* NVMe Identify parameters (cdw10) */
/* NVMe Queue Entry Size bitfield */
typedef struct {
/* NVMe Power State Descriptor */
typedef struct {
/* NVMe Identify Controller Data Structure */
typedef struct {
/* Controller Capabilities & Features */
struct { /* Multi-Interface Capabilities */
} id_mic;
/* Admin Command Set Attributes */
struct { /* Optional Admin Command Support */
} id_oacs;
struct { /* Firmware Updates */
} id_frmw;
struct { /* Log Page Attributes */
} id_lpa;
struct { /* Admin Vendor Specific Command Conf */
} id_avscc;
struct { /* Autonomous Power State Trans (1.1) */
} id_apsta;
/* NVM Command Set Attributes */
struct { /* Optional NVM Command Support */
} id_oncs;
struct { /* Fused Operation Support */
} id_fuses;
struct { /* Format NVM Attributes */
} id_fna;
struct { /* Volatile Write Cache */
} id_vwc;
struct { /* NVM Vendor Specific Command Conf */
} id_nvscc;
struct { /* SGL Support (1.1) */
} id_sgls;
/* I/O Command Set Attributes */
/* Power State Descriptors */
/* Vendor Specific */
/* NVMe Identify Namespace LBA Format */
typedef struct {
/* NVMe Identify Namespace Data Structure */
typedef struct {
struct { /* Namespace Features */
} id_nsfeat;
struct { /* Formatted LBA size */
} id_flbas;
struct { /* Metadata Capabilities */
} id_mc;
struct { /* Data Protection Capabilities */
} id_dpc;
struct { /* Data Protection Settings */
} id_dps;
struct { /* NS Multi-Path/Sharing Cap (1.1) */
} id_nmic;
struct { /* Reservation Capabilities (1.1) */
} id_rescap;
/*
* NVMe Abort Command
*/
typedef union {
struct {
} b;
uint32_t r;
/*
* NVMe Get / Set Features
*/
/* (1.1) */
/* Arbitration Feature */
typedef struct {
/* LBA Range Type Feature */
typedef struct {
typedef struct {
struct { /* Attributes */
} lr_attr;
/* Volatile Write Cache Feature */
typedef union {
struct {
} b;
uint32_t r;
/* Number of Queues */
typedef union {
struct {
} b;
uint32_t r;
/*
* NVMe Get Log Page
*/
typedef union {
struct {
} b;
uint32_t r;
typedef struct {
typedef struct {
typedef struct {
typedef struct {
#ifdef __cplusplus
}
#endif
#pragma pack() /* pack(1) */
#endif /* _NVME_REG_H */