unm_inc.h revision dda0720a40a5b9892e9c96b39ff67c6f504656af
/*
* CDDL HEADER START
*
* The contents of this file are subject to the terms of the
* Common Development and Distribution License (the "License").
* You may not use this file except in compliance with the License.
*
* You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
* See the License for the specific language governing permissions
* and limitations under the License.
*
* When distributing Covered Code, include this CDDL HEADER in each
* file and include the License file at usr/src/OPENSOLARIS.LICENSE.
* If applicable, add the following below this CDDL HEADER, with the
* fields enclosed by brackets "[]" replaced with your own identifying
* information: Portions Copyright [yyyy] [name of copyright owner]
*
* CDDL HEADER END
*/
/*
* Copyright 2008 NetXen, Inc. All rights reserved.
* Use is subject to license terms.
*/
#ifndef _UNM_INC_H_
#define _UNM_INC_H_
#ifdef __cplusplus
extern "C" {
#endif
#include "nx_errorcode.h"
#define PREALIGN(x)
#define POSTALIGN(x)
typedef char __int8_t;
typedef short __int16_t;
typedef int __int32_t;
typedef long long __int64_t;
typedef unsigned char __uint8_t;
typedef unsigned short __uint16_t;
typedef unsigned int __uint32_t;
typedef unsigned long long __uint64_t;
typedef __uint64_t jiffies_t;
typedef unsigned long long u64;
typedef unsigned long long U64;
#include "nx_hw_pci_regs.h"
#define UNM_CONF_X86 3
/*
* MAX_RCV_CTX : The number of receive contexts that are available on
* the phantom.
*/
#define MAX_RCV_CTX 1
/* ------------------------------------------------------------------------ */
/* CRB Hub and Agent addressing */
/* ------------------------------------------------------------------------ */
/*
* WARNING: pex_tgt_adr.v assumes if MSB of hub adr is set then it is an
* ILLEGAL hub!!!!!
*/
#define UNM_HW_H0_CH_HUB_ADR 0x05
#define UNM_HW_H1_CH_HUB_ADR 0x0E
#define UNM_HW_H2_CH_HUB_ADR 0x03
#define UNM_HW_H3_CH_HUB_ADR 0x01
#define UNM_HW_H4_CH_HUB_ADR 0x06
#define UNM_HW_H5_CH_HUB_ADR 0x07
#define UNM_HW_H6_CH_HUB_ADR 0x08
/*
* WARNING: pex_tgt_adr.v assumes if MSB of hub adr is set then it is an
* ILLEGAL hub!!!!!
*/
/* Hub 0 */
#define UNM_HW_MN_CRB_AGT_ADR 0x15
#define UNM_HW_MS_CRB_AGT_ADR 0x25
/* Hub 1 */
#define UNM_HW_PS_CRB_AGT_ADR 0x73
#define UNM_HW_SS_CRB_AGT_ADR 0x20
#define UNM_HW_RPMX3_CRB_AGT_ADR 0x0b
#define UNM_HW_QMS_CRB_AGT_ADR 0x00
#define UNM_HW_SQGS0_CRB_AGT_ADR 0x01
#define UNM_HW_SQGS1_CRB_AGT_ADR 0x02
#define UNM_HW_SQGS2_CRB_AGT_ADR 0x03
#define UNM_HW_SQGS3_CRB_AGT_ADR 0x04
#define UNM_HW_C2C0_CRB_AGT_ADR 0x58
#define UNM_HW_C2C1_CRB_AGT_ADR 0x59
#define UNM_HW_C2C2_CRB_AGT_ADR 0x5a
#define UNM_HW_RPMX2_CRB_AGT_ADR 0x0a
#define UNM_HW_RPMX4_CRB_AGT_ADR 0x0c
#define UNM_HW_RPMX7_CRB_AGT_ADR 0x0f
#define UNM_HW_RPMX9_CRB_AGT_ADR 0x12
#define UNM_HW_SMB_CRB_AGT_ADR 0x18
/* Hub 2 */
#define UNM_HW_NIU_CRB_AGT_ADR 0x31
#define UNM_HW_I2C0_CRB_AGT_ADR 0x19
#define UNM_HW_I2C1_CRB_AGT_ADR 0x29
#define UNM_HW_SN_CRB_AGT_ADR 0x10
#define UNM_HW_I2Q_CRB_AGT_ADR 0x20
#define UNM_HW_LPC_CRB_AGT_ADR 0x22
#define UNM_HW_ROMUSB_CRB_AGT_ADR 0x21
#define UNM_HW_QM_CRB_AGT_ADR 0x66
#define UNM_HW_SQG0_CRB_AGT_ADR 0x60
#define UNM_HW_SQG1_CRB_AGT_ADR 0x61
#define UNM_HW_SQG2_CRB_AGT_ADR 0x62
#define UNM_HW_SQG3_CRB_AGT_ADR 0x63
#define UNM_HW_RPMX1_CRB_AGT_ADR 0x09
#define UNM_HW_RPMX5_CRB_AGT_ADR 0x0d
#define UNM_HW_RPMX6_CRB_AGT_ADR 0x0e
#define UNM_HW_RPMX8_CRB_AGT_ADR 0x11
/* Hub 3 */
#define UNM_HW_PH_CRB_AGT_ADR 0x1A
#define UNM_HW_SRE_CRB_AGT_ADR 0x50
#define UNM_HW_EG_CRB_AGT_ADR 0x51
#define UNM_HW_RPMX0_CRB_AGT_ADR 0x08
/* Hub 4 */
#define UNM_HW_PEGN0_CRB_AGT_ADR 0x40
#define UNM_HW_PEGN1_CRB_AGT_ADR 0x41
#define UNM_HW_PEGN2_CRB_AGT_ADR 0x42
#define UNM_HW_PEGN3_CRB_AGT_ADR 0x43
#define UNM_HW_PEGNI_CRB_AGT_ADR 0x44
#define UNM_HW_PEGND_CRB_AGT_ADR 0x45
#define UNM_HW_PEGNC_CRB_AGT_ADR 0x46
#define UNM_HW_PEGR0_CRB_AGT_ADR 0x47
#define UNM_HW_PEGR1_CRB_AGT_ADR 0x48
#define UNM_HW_PEGR2_CRB_AGT_ADR 0x49
#define UNM_HW_PEGR3_CRB_AGT_ADR 0x4a
#define UNM_HW_PEGN4_CRB_AGT_ADR 0x4b
/* Hub 5 */
#define UNM_HW_PEGS0_CRB_AGT_ADR 0x40
#define UNM_HW_PEGS1_CRB_AGT_ADR 0x41
#define UNM_HW_PEGS2_CRB_AGT_ADR 0x42
#define UNM_HW_PEGS3_CRB_AGT_ADR 0x43
#define UNM_HW_PEGSI_CRB_AGT_ADR 0x44
#define UNM_HW_PEGSD_CRB_AGT_ADR 0x45
#define UNM_HW_PEGSC_CRB_AGT_ADR 0x46
/* Hub 6 */
#define UNM_HW_CAS0_CRB_AGT_ADR 0x46
#define UNM_HW_CAS1_CRB_AGT_ADR 0x47
#define UNM_HW_CAS2_CRB_AGT_ADR 0x48
#define UNM_HW_CAS3_CRB_AGT_ADR 0x49
#define UNM_HW_NCM_CRB_AGT_ADR 0x16
#define UNM_HW_TMR_CRB_AGT_ADR 0x17
#define UNM_HW_XDMA_CRB_AGT_ADR 0x05
#define UNM_HW_OCM0_CRB_AGT_ADR 0x06
#define UNM_HW_OCM1_CRB_AGT_ADR 0x07
/* This field defines PCI/X adr [25:20] of agents on the CRB */
/* */
#define UNM_HW_PX_MAP_CRB_PH 0
#define UNM_HW_PX_MAP_CRB_PS 1
#define UNM_HW_PX_MAP_CRB_MN 2
#define UNM_HW_PX_MAP_CRB_MS 3
#define UNM_HW_PX_MAP_CRB_SRE 5
#define UNM_HW_PX_MAP_CRB_NIU 6
#define UNM_HW_PX_MAP_CRB_QMN 7
#define UNM_HW_PX_MAP_CRB_SQN0 8
#define UNM_HW_PX_MAP_CRB_SQN1 9
#define UNM_HW_PX_MAP_CRB_SQN2 10
#define UNM_HW_PX_MAP_CRB_SQN3 11
#define UNM_HW_PX_MAP_CRB_QMS 12
#define UNM_HW_PX_MAP_CRB_SQS0 13
#define UNM_HW_PX_MAP_CRB_SQS1 14
#define UNM_HW_PX_MAP_CRB_SQS2 15
#define UNM_HW_PX_MAP_CRB_SQS3 16
#define UNM_HW_PX_MAP_CRB_PGN0 17
#define UNM_HW_PX_MAP_CRB_PGN1 18
#define UNM_HW_PX_MAP_CRB_PGN2 19
#define UNM_HW_PX_MAP_CRB_PGN3 20
#define UNM_HW_PX_MAP_CRB_PGND 21
#define UNM_HW_PX_MAP_CRB_PGNI 22
#define UNM_HW_PX_MAP_CRB_PGS0 23
#define UNM_HW_PX_MAP_CRB_PGS1 24
#define UNM_HW_PX_MAP_CRB_PGS2 25
#define UNM_HW_PX_MAP_CRB_PGS3 26
#define UNM_HW_PX_MAP_CRB_PGSD 27
#define UNM_HW_PX_MAP_CRB_PGSI 28
#define UNM_HW_PX_MAP_CRB_SN 29
#define UNM_HW_PX_MAP_CRB_EG 31
#define UNM_HW_PX_MAP_CRB_PH2 32
#define UNM_HW_PX_MAP_CRB_PS2 33
#define UNM_HW_PX_MAP_CRB_CAM 34
#define UNM_HW_PX_MAP_CRB_CAS0 35
#define UNM_HW_PX_MAP_CRB_CAS1 36
#define UNM_HW_PX_MAP_CRB_CAS2 37
#define UNM_HW_PX_MAP_CRB_C2C0 38
#define UNM_HW_PX_MAP_CRB_C2C1 39
#define UNM_HW_PX_MAP_CRB_TIMR 40
/* N/A: Not use in either Phantom1 or Phantom2 => use for TIMR */
/* #define PX_MAP_CRB_C2C2 40 */
/* #define PX_MAP_CRB_SS 41 */
#define UNM_HW_PX_MAP_CRB_RPMX1 42
#define UNM_HW_PX_MAP_CRB_RPMX2 43
#define UNM_HW_PX_MAP_CRB_RPMX3 44
#define UNM_HW_PX_MAP_CRB_RPMX4 45
#define UNM_HW_PX_MAP_CRB_RPMX5 46
#define UNM_HW_PX_MAP_CRB_RPMX6 47
#define UNM_HW_PX_MAP_CRB_RPMX7 48
#define UNM_HW_PX_MAP_CRB_XDMA 49
#define UNM_HW_PX_MAP_CRB_I2Q 50
#define UNM_HW_PX_MAP_CRB_ROMUSB 51
#define UNM_HW_PX_MAP_CRB_CAS3 52
#define UNM_HW_PX_MAP_CRB_RPMX0 53
#define UNM_HW_PX_MAP_CRB_RPMX8 54
#define UNM_HW_PX_MAP_CRB_RPMX9 55
#define UNM_HW_PX_MAP_CRB_OCM0 56
#define UNM_HW_PX_MAP_CRB_OCM1 57
#define UNM_HW_PX_MAP_CRB_SMB 58
#define UNM_HW_PX_MAP_CRB_I2C0 59
#define UNM_HW_PX_MAP_CRB_I2C1 60
#define UNM_HW_PX_MAP_CRB_LPC 61
#define UNM_HW_PX_MAP_CRB_PGNC 62
#define UNM_HW_PX_MAP_CRB_PGR0 63
#define UNM_HW_PX_MAP_CRB_PGR1 4
#define UNM_HW_PX_MAP_CRB_PGR2 30
#define UNM_HW_PX_MAP_CRB_PGR3 41
/* This field defines CRB adr [31:20] of the agents */
/* */
/*
* ROM USB CRB space is divided into 4 regions depending on decode of
* address bits [19:16]
*/
/* ROMUSB GLB register definitions */
/* Lock IDs for ROM lock */
#define ROM_LOCK_DRIVER 0x0d417340
/* Lock IDs for PHY lock */
#define PHY_LOCK_DRIVER 0x44524956
/* HACK upon HACK upon HACK (for PCIE builds) */
#define UNM_CRB_PCIE UNM_CRB_PCIX_MD
// window 1 pcie slot
/*
* ====================== BASE ADDRESSES ON-CHIP ======================
* Base addresses of major components on-chip.
* ====================== BASE ADDRESSES ON-CHIP ======================
*/
#define UNM_ADDR_DDR_NET (0x0000000000000000ULL)
#define UNM_ADDR_DDR_NET_MAX (0x000000000fffffffULL)
/*
* Imbus address bit used to indicate a host address. This bit is
* eliminated by the pcie bar and bar select before presentation
* over pcie.
*/
/* host memory via IMBUS */
#define NX_P2_ADDR_PCIE (0x0000000800000000ULL)
#define NX_P3_ADDR_PCIE (0x0000008000000000ULL)
#define UNM_ADDR_PCIE_MAX (0x0000000FFFFFFFFFULL)
#define UNM_ADDR_OCM0 (0x0000000200000000ULL)
#define UNM_ADDR_OCM0_MAX (0x00000002000fffffULL)
#define UNM_ADDR_OCM1 (0x0000000200400000ULL)
#define UNM_ADDR_OCM1_MAX (0x00000002004fffffULL)
#define UNM_ADDR_QDR_NET (0x0000000300000000ULL)
#define NX_P2_ADDR_QDR_NET_MAX (0x00000003001fffffULL)
#define NX_P3_ADDR_QDR_NET_MAX (0x0000000303ffffffULL)
/*
* The ifdef at the bottom should go. All drivers should start using the
* above 2 defines.
*/
#ifdef P3
#else
#endif
#define UNM_PCI_ARCH_CRB_BASE (UNM_PCI_DIRECT_CRB)
/* we're mapping 128MB of mem on the PCI bus */
#define UNM_PCI_MAPSIZE 128
#define UNM_PCI_DDR_NET (unsigned long)0x00000000
#define UNM_PCI_DDR_NET_MAX (unsigned long)0x01ffffff
#define UNM_PCI_DDR_MD (unsigned long)0x02000000
#define UNM_PCI_DDR_MD_MAX (unsigned long)0x03ffffff
#define UNM_PCI_QDR_NET (unsigned long)0x04000000
#define UNM_PCI_QDR_NET_MAX (unsigned long)0x043fffff
#define UNM_PCI_DIRECT_CRB (unsigned long)0x04400000
#define UNM_PCI_DIRECT_CRB_MAX (unsigned long)0x047fffff
#define UNM_PCI_CAMQM (unsigned long)0x04800000
#define UNM_PCI_CAMQM_MAX (unsigned long)0x04ffffff
#define UNM_PCI_OCM0 (unsigned long)0x05000000
#define UNM_PCI_OCM0_MAX (unsigned long)0x050fffff
#define UNM_PCI_OCM1 (unsigned long)0x05100000
#define UNM_PCI_OCM1_MAX (unsigned long)0x051fffff
#define UNM_PCI_CRBSPACE (unsigned long)0x06000000
#define UNM_PCI_CRBSPACE_MAX (unsigned long)0x07ffffff
#define UNM_PCI_128MB_SIZE (unsigned long)0x08000000
#define UNM_PCI_32MB_SIZE (unsigned long)0x02000000
#define UNM_PCI_2MB_SIZE (unsigned long)0x00200000
/*
*/
typedef long native_t; /* most efficient integer on h/w */
/*
* h/w block.
*/
/*
* Configuration registers.
*/
/* P3 802.3ap */
/*
* Register offsets for MN
*/
#define MIU_CONTROL (0x000)
#define MIU_TAG (0x004)
#define MIU_TEST_AGT_CTRL (0x090)
#define MIU_TEST_AGT_ADDR_LO (0x094)
#define MIU_TEST_AGT_ADDR_HI (0x098)
#define MIU_TEST_AGT_WRDATA_LO (0x0a0)
#define MIU_TEST_AGT_WRDATA_HI (0x0a4)
#define MIU_TEST_AGT_RDDATA_LO (0x0a8)
#define MIU_TEST_AGT_RDDATA_HI (0x0ac)
#define MIU_TEST_AGT_ADDR_MASK 0xfffffff8
#define MIU_TEST_AGT_UPPER_ADDR(off) (0)
/* MIU_TEST_AGT_CTRL flags. work for SIU as well */
#define MIU_TA_CTL_START 1
#define MIU_TA_CTL_ENABLE 2
#define MIU_TA_CTL_WRITE 4
#define MIU_TA_CTL_BUSY 8
#define SIU_TEST_AGT_CTRL (0x060)
#define SIU_TEST_AGT_ADDR_LO (0x064)
#define SIU_TEST_AGT_ADDR_HI (0x078)
#define SIU_TEST_AGT_WRDATA_LO (0x068)
#define SIU_TEST_AGT_WRDATA_HI (0x06c)
#define SIU_TEST_AGT_RDDATA_LO (0x070)
#define SIU_TEST_AGT_RDDATA_HI (0x074)
#define SIU_TEST_AGT_ADDR_MASK 0x3ffff8
/* XG Link status */
#define XG_LINK_UP 0x10
/* ====================== Configuration Constants ======================== */
#define UNM_NIU_MAX_GBE_PORTS 4
#define UNM_NIU_MAX_XG_PORTS 2
#define MIN_CORE_CLK_SPEED 200
#define MAX_CORE_CLK_SPEED 400
#define ACCEPTABLE_CORE_CLK_RANGE(speed) \
#define P2_TICKS_PER_SEC 2048
#define CHECK_TICKS_PER_SEC(ticks) \
/* ============================= 1GbE =============================== */
/* Nibble or Byte mode for phy interface (GbE mode only) */
typedef enum {
UNM_NIU_10_100_MB = 0,
/* Promiscous mode options (GbE mode only) */
typedef enum {
/*
* NIU GB Drop CRC Register
*/
typedef struct {
rsvd:28;
/*
* NIU GB GMII Mode Register (applies to GB0, GB1, GB2, GB3)
* To change the mode, turn off the existing mode, then turn on the new mode.
*/
typedef struct {
rsvd:29;
/*
* NIU GB MII Mode Register (applies to GB0, GB1, GB2, GB3)
* To change the mode, turn off the existing mode, then turn on the new mode.
*/
typedef struct {
rsvd:29;
/*
* NIU GB MAC Config Register 0 (applies to GB0, GB1, GB2, GB3)
*/
typedef struct {
rsvd1:2,
rsvd2:7,
rsvd3:11,
/*
* NIU GB MAC Config Register 1 (applies to GB0, GB1, GB2, GB3)
*/
typedef struct {
rsvd1:1,
rsvd2:2,
rsvd3:2,
rsvd4:16;
/*
* NIU XG Pause Ctl Register
*/
typedef struct {
rsvd:26;
/*
* NIU GBe Pause Ctl Register
*/
typedef struct {
rsvd:24;
/*
* NIU XG MAC Config Register
*/
typedef struct {
rsvd1:1,
rsvd2:1,
rsvd3:22,
/*
* NIU GB MII Mgmt Config Register (applies to GB0, GB1, GB2, GB3)
*/
typedef struct {
/* 4:clk/10, 5:clk/14, 6:clk/20, 7:clk/28 */
rsvd1:1,
rsvd2:25,
/*
* NIU GB MII Mgmt Command Register (applies to GB0, GB1, GB2, GB3)
*/
typedef struct {
rsvd:30;
/*
* NIU GB MII Mgmt Address Register (applies to GB0, GB1, GB2, GB3)
*/
typedef struct {
rsvd1:3,
rsvd:19;
/*
* NIU GB MII Mgmt Indicators Register (applies to GB0, GB1, GB2, GB3)
* Read-only register.
*/
typedef struct {
rsvd:29;
/*
* NIU GB Station Address High Register
* NOTE: this value is in network byte order.
*/
typedef struct {
/*
* NIU GB Station Address Low Register
* NOTE: this value is in network byte order.
*/
typedef struct {
rsvd:16,
/* ============================ PHY Definitions ========================== */
/*
*/
typedef enum {
/*
* PHY-Specific Status Register (reg 17).
*/
typedef struct {
/* 0:<50m, 1:50-80m, 2:80-110m, 3:110-140m, 4:>140m */
rsvd:16;
/*
* Interrupt Register definition
* This definition applies to registers 18 and 19 (int enable and int status).
*/
typedef struct {
jabber:1,
reserved:2,
downshift:1,
symbol_error:1,
rsvd:16;
/* ============================= 10GbE =============================== */
/*
* NIU Mode Register.
*/
typedef struct {
rsvd:29;
/* ========================== Interface Functions ======================= */
/* Generic enable for GbE ports. Will detect the speed of the link. */
long unm_niu_gbe_init_port(long port);
/* XG Link status */
#define XG_LINK_UP 0x10
#define XG_LINK_DOWN 0x20
#define XG_LINK_UP_P3 0x1
#define XG_LINK_DOWN_P3 0x2
#define XG_LINK_UNKNOWN_P3 0
#define XG_LINK_STATE_P3_MASK 0xf
#define MTU_MARGIN 100
#define PF_LINK_SPEED_MHZ 100
#define PF_LINK_SPEED_MASK 0xff
/*
*/
typedef union {
struct {
/*
* =1 if watchdog is active.
* =0 if watchdog is inactive
* This is read-only for anyone
* but the watchdog itself.
*/
unsigned int enabled: 1,
/*
* Set this to 1 to send disable
* request to watchdog . Watchdog
* will complete the shutdown
* process and acknowledge it
* by clearing this bit and the
* "enable" bit.
*/
disable_request: 1,
/*
* Set this to 1 to send enable
* request to watchdog . Watchdog
* will complete the enable
* process and acknowledge it
* by clearing this bit and
* setting the "enable" bit.
*/
enable_request: 1,
unused: 29;
} s1;
#define UNM_PORT_MODE_NONE 0
#define UNM_PORT_MODE_XG 1
#define UNM_PORT_MODE_GB 2
#define UNM_PORT_MODE_802_3_AP 3
#define UNM_PORT_MODE_AUTO_NEG 4
#define UNM_PORT_MODE_AUTO_NEG_1G 5
#define UNM_PORT_MODE_AUTO_NEG_XG 6
#define PCIE_DCR (0x00d8)
#define PCIE_DB_DATA2 (0x10070)
#define PCIE_DB_CTRL (0x100a0)
#define PCIE_DB_ADDR (0x100a4)
#define PCIE_DB_DATA (0x100a8)
#define PCIE_IMBUS_CONTROL (0x101b8)
#define PCIE_SETUP_FUNCTION (0x12040)
#define PCIE_SETUP_FUNCTION2 (0x12048)
#define PCIE_TGT_SPLIT_CHICKEN (0x12080)
#define PCIE_CHICKEN3 (0x120c8)
#define PCIE_MAX_MASTER_SPLIT (0x14048)
#define PCIE_MAX_DMA_XFER_SIZE (0x1404c)
/*
* Following define address space withing PCIX CRB space to talk with
* devices on the storage side PCI bus.
*/
#define PCIX_PS_MEM_SPACE (0x90000)
/*
* Configuration registers. These are the same offsets on both host and
* storage side PCI blocks.
*/
/* Used for PS PCI Memory access */
#define PCIX_PS_OP_ADDR_LO (0x10000)
#define PCIX_CRB_WINDOW (0x10210)
#define PCIX_CRB_WINDOW_F0 (0x10210)
#define PCIX_CRB_WINDOW_F1 (0x10230)
#define PCIX_CRB_WINDOW_F2 (0x10250)
#define PCIX_CRB_WINDOW_F3 (0x10270)
#define PCIX_CRB_WINDOW_F4 (0x102ac)
#define PCIX_CRB_WINDOW_F5 (0x102bc)
#define PCIX_CRB_WINDOW_F6 (0x102cc)
#define PCIX_CRB_WINDOW_F7 (0x102dc)
#define PCIX_MN_WINDOW (0x10200)
#define PCIX_MN_WINDOW_F0 (0x10200)
#define PCIX_MN_WINDOW_F1 (0x10220)
#define PCIX_MN_WINDOW_F2 (0x10240)
#define PCIX_MN_WINDOW_F3 (0x10260)
#define PCIX_MN_WINDOW_F4 (0x102a0)
#define PCIX_MN_WINDOW_F5 (0x102b0)
#define PCIX_MN_WINDOW_F6 (0x102c0)
#define PCIX_MN_WINDOW_F7 (0x102d0)
#define PCIX_SN_WINDOW (0x10208)
#define PCIX_SN_WINDOW_F0 (0x10208)
#define PCIX_SN_WINDOW_F1 (0x10228)
#define PCIX_SN_WINDOW_F2 (0x10248)
#define PCIX_SN_WINDOW_F3 (0x10268)
#define PCIX_SN_WINDOW_F4 (0x102a8)
#define PCIX_SN_WINDOW_F5 (0x102b8)
#define PCIX_SN_WINDOW_F6 (0x102c8)
#define PCIX_SN_WINDOW_F7 (0x102d8)
/*
* CRB window register.
*/
typedef struct {
rsvd2:6;
/*
* Tell which interrupt source we want to operate on.
*/
typedef enum {
UNM_PCIX_INT_SRC_DMA0, /* DMA engine 0 */
UNM_PCIX_INT_SRC_DMA1, /* DMA engine 1 */
UNM_PCIX_INT_SRC_I2Q /* I2Q block */
typedef enum {
UNM_PCIX_INT_SRC_ALLOW, /* Allow this src to int. the host */
UNM_PCIX_INT_SRC_MASK /* Mask this src */
/*
* PCIX Interrupt Mask Register.
*/
typedef struct {
/* 0=DMA0 not masked, 1=masked */
/* 0=DMA1 not masked, 1=masked */
dma1:1,
/* 0=I2Q not masked, 1=masked */
i2q:1,
dma0_err:1,
dma1_err:1,
mega_err:1,
ps_serr_int:1,
rsvd:15;
// These are offset to a particular Peg's CRB base address
#define CRB_REG_EX_PC 0x3c
/*
* to either the Primary Queue Manager or the Secondary Queue Manager.
*/
/*
* General configuration constants.
*/
#define UNM_QM_MAX_SIDE 1
/*
* Data movement registers (differs based on processor).
*/
(W)*sizeof (unm_dataword_t))
(W)*sizeof (unm_dataword_t))
/*
* Control commands to the QM block.
*/
/*
* Platform-specific fields in the queue command word
*/
#define UNM_QM_CMD_SIDE 0
/* Casper and Peg need this bit. PCI interface does not */
#define UNM_QM_CMD_START 1
/*
* Pegasus has two QM ports. This is the default one to use (unless
* QM async interface is called explicitly with other port).
*/
#define UNM_QM_DEFAULT_PORT 0
/*
* Status result returned to caller of unm_qm_request_status()
*/
typedef enum {
/* error in HW - most likely PCI bug. retry */
unm_qm_status_done, /* done with last command */
unm_qm_status_busy, /* busy */
unm_qm_status_notfound, /* queue is empty to read or full to write */
unm_qm_status_error /* error (e.g. timeout) encountered */
/*
*/
/*
* Configuration registers.
*/
/*
* List the bit positions in the registers of the interrupt sources.
*/
typedef enum {
UNM_I2Q_SRC_PCI32 = 0, /* PCI32 block */
/* [29:31] reserved */
/* [48:63] reserved */
/*
*/
typedef struct {
typedef struct {
rsvd:16;
/*
* List the possible interrupt sources and the
* control operations to be performed for each.
*/
typedef enum {
UNM_I2Q_CTL_SRCUNKNOWN = 0, /* undefined */
UNM_I2Q_CTL_PCI, /* PCI block */
UNM_I2Q_CTL_CASPER, /* Casper */
UNM_I2Q_CTL_QM /* Queue Manager */
typedef enum {
UNM_I2Q_CTL_OPUNKNOWN = 0, /* undefined */
UNM_I2Q_CTL_ADD, /* add int'ing for that source */
UNM_I2Q_CTL_DEL /* stop int'ing for that source */
/*
* h/w block.
*/
/*
* Configuration registers.
*/
#define UNM_SQM_BASE(G) \
((G) == 0 ? UNM_CRB_SQM_NET_0 : \
((G) == 1 ? UNM_CRB_SQM_NET_1 : \
/*
* Interrupt enables and interrupt status for all 16 queues in a group.
*/
typedef struct {
rsvd:16;
/*
* Control operation for an SQM Group interrupt.
*/
typedef enum {
UNM_SQM_INTOP_OPUNKNOWN = 0, /* undefined */
UNM_SQM_INTOP_GET, /* return all bits for that group */
UNM_SQM_INTOP_SET, /* assign all bits for that group */
UNM_SQM_INTOP_ADD, /* set one bit for that group */
UNM_SQM_INTOP_DEL /* clear one bit for that group */
typedef enum {
UNM_SQM_INTARG_ARGUNKNOWN = 0, /* undefined */
UNM_SQM_INTARG_ENABLE, /* affect the 'enable' register */
UNM_SQM_INTARG_STATUS /* affect the 'status' register */
unsigned long unm_xport_lock(void);
void unm_xport_unlock(unsigned long);
do { \
return (-1); \
} while (0)
do { \
return (-1); \
} while (0)
do { \
} while (0)
do { \
} while (0)
do { \
return (-1); \
} while (0)
do { \
return (-1); \
} while (0)
do { \
return (-1); \
} while (0)
do { \
return (-1); \
} while (0)
/*
* Configuration registers.
*/
#ifdef PCIX
#else
#endif
#define PCIE_PS_STRAP_RESET (0x18000)
#define M25P_INSTR_WREN 0x06
#define M25P_INSTR_RDSR 0x05
#define M25P_INSTR_PP 0x02
#define M25P_INSTR_SE 0xd8
#define CAM_RAM_P2I_ENABLE 0xc
#define CAM_RAM_P2D_ENABLE 0x8
#define PCIX_IMBTAG (0x18004)
// FOR PORT 1
// FOR PORT 2
// PORT 3
#define PHAN_VENDOR_ID 0x4040
#define CAM_RAM_PEG_ENABLES 0x4
/*
* The PCI VendorID and DeviceID for our board.
*/
#define PCI_VENDOR_ID_NX 0x4040
#define PCI_DEVICE_ID_NX_XG 0x0001
#define PCI_DEVICE_ID_NX_CX4 0x0002
#define PCI_DEVICE_ID_NX_QG 0x0003
#define PCI_DEVICE_ID_NX_IMEZ 0x0004
#define PCI_DEVICE_ID_NX_HMEZ 0x0005
#define PCI_DEVICE_ID_NX_IMEZ_DUP 0x0024
#define PCI_DEVICE_ID_NX_HMEZ_DUP 0x0025
#define PCI_DEVICE_ID_NX_P3_XG 0x0100
/*
* Time base tick control registers (global and per-flow).
*/
typedef struct {
/* half period of time cycle */
/* global: in units of core clock */
/* per-flow: in units of global ticks */
rsvd:15,
typedef struct
{
id_pool_0:2,
rsvd1:1,
id_pool_1:2,
rsvd2:1,
id_pool_2:2,
rsvd3:1,
id_pool_3:2,
rsvd4:9,
mode_select:2,
rsvd5:2,
enable_pool:4;
typedef struct {
enable:1,
command:1,
busy:1,
rsvd:28;
#define UNM_MIU_TEST_AGENT_CMD_READ 0
#define UNM_MIU_TEST_AGENT_CMD_WRITE 1
#define UNM_MIU_TEST_AGENT_BUSY 1
#define UNM_MIU_TEST_AGENT_ENABLE 1
#define UNM_MIU_TEST_AGENT_START 1
#ifdef __cplusplus
}
#endif
#endif /* _UNM_INC_H_ */