47693af92e50a1ad81825eb01b7157a211269613mx * CDDL HEADER START
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47693af92e50a1ad81825eb01b7157a211269613mx * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
47693af92e50a1ad81825eb01b7157a211269613mx * See the License for the specific language governing permissions
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47693af92e50a1ad81825eb01b7157a211269613mx * When distributing Covered Code, include this CDDL HEADER in each
47693af92e50a1ad81825eb01b7157a211269613mx * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
47693af92e50a1ad81825eb01b7157a211269613mx * If applicable, add the following below this CDDL HEADER, with the
47693af92e50a1ad81825eb01b7157a211269613mx * fields enclosed by brackets "[]" replaced with your own identifying
47693af92e50a1ad81825eb01b7157a211269613mx * information: Portions Copyright [yyyy] [name of copyright owner]
47693af92e50a1ad81825eb01b7157a211269613mx * CDDL HEADER END
bdb9230ac765cb7af3fc1f4119caf2c5720dceb3Garrett D'Amore * Copyright 2009 Sun Microsystems, Inc. All rights reserved.
47693af92e50a1ad81825eb01b7157a211269613mx * Use is subject to license terms.
6f3e57ac9d0b054c3169579f3422080b8ba10105mx#define NGE_DBG NGE_DBG_MII /* debug flag for this code */
6f3e57ac9d0b054c3169579f3422080b8ba10105mx * The arrays below can be indexed by the MODE bits from the mac2phy
6f3e57ac9d0b054c3169579f3422080b8ba10105mx * register to determine the current speed/duplex settings.
6f3e57ac9d0b054c3169579f3422080b8ba10105mx 0, /* MII_AUX_STATUS_MODE_NONE */
6f3e57ac9d0b054c3169579f3422080b8ba10105mxstatic uint16_t nge_mii_access(nge_t *ngep, nge_regno_t regno,
6f3e57ac9d0b054c3169579f3422080b8ba10105mx#pragma inline(nge_mii_access)
6f3e57ac9d0b054c3169579f3422080b8ba10105mxnge_mii_access(nge_t *ngep, nge_regno_t regno, uint16_t data, uint32_t cmd)
6f3e57ac9d0b054c3169579f3422080b8ba10105mx * Clear the privous interrupt event
6f3e57ac9d0b054c3169579f3422080b8ba10105mx * Check whether the current operation has been finished
6f3e57ac9d0b054c3169579f3422080b8ba10105mx * The current operation can not be finished successfully
6f3e57ac9d0b054c3169579f3422080b8ba10105mx * The driver should halt the current operation
6f3e57ac9d0b054c3169579f3422080b8ba10105mx * Assemble the operation cmd
a55f711916b9f7718fabc2d1822bf5719aa6140fMiles Xu, Sun Microsystems mdio_adr.adr_bits.phy_reg = (uint16_t)regno;
6f3e57ac9d0b054c3169579f3422080b8ba10105mx mdio_adr.adr_bits.mdio_rw = (cmd == NGE_MDIO_WRITE) ? 1 : 0;
6f3e57ac9d0b054c3169579f3422080b8ba10105mx * To check whether the read/write operation is finished
6f3e57ac9d0b054c3169579f3422080b8ba10105mx return ((uint16_t)~0);
6f3e57ac9d0b054c3169579f3422080b8ba10105mx * Read the data from MDIO data register
6f3e57ac9d0b054c3169579f3422080b8ba10105mx * To check whether the read/write operation is valid
6f3e57ac9d0b054c3169579f3422080b8ba10105mx return ((uint16_t)~0);
6f3e57ac9d0b054c3169579f3422080b8ba10105mx#pragma inline(nge_mii_get16)
6f3e57ac9d0b054c3169579f3422080b8ba10105mxvoid nge_mii_put16(nge_t *ngep, nge_regno_t regno, uint16_t data);
6f3e57ac9d0b054c3169579f3422080b8ba10105mx#pragma inline(nge_mii_put16)
6f3e57ac9d0b054c3169579f3422080b8ba10105mxnge_mii_put16(nge_t *ngep, nge_regno_t regno, uint16_t data)
6f3e57ac9d0b054c3169579f3422080b8ba10105mx (void) nge_mii_access(ngep, regno, data, NGE_MDIO_WRITE);
6f3e57ac9d0b054c3169579f3422080b8ba10105mx * Basic low-level function to probe for a PHY
6f3e57ac9d0b054c3169579f3422080b8ba10105mx * Returns TRUE if the PHY responds with valid data, FALSE otherwise
6f3e57ac9d0b054c3169579f3422080b8ba10105mx * Scan the phys to find the right address
6f3e57ac9d0b054c3169579f3422080b8ba10105mx * of the phy
6f3e57ac9d0b054c3169579f3422080b8ba10105mx * Probe maximum for 32 phy addresses
6f3e57ac9d0b054c3169579f3422080b8ba10105mx for (i = 0; i < NGE_PHY_NUMBER; i++) {
6f3e57ac9d0b054c3169579f3422080b8ba10105mx * Read the MII_STATUS register twice, in
6f3e57ac9d0b054c3169579f3422080b8ba10105mx * order to clear any sticky bits (but they should
6f3e57ac9d0b054c3169579f3422080b8ba10105mx * have been cleared by the RESET, I think).
6f3e57ac9d0b054c3169579f3422080b8ba10105mx * Basic low-level function to powerup the phy and remove the isolation
6f3e57ac9d0b054c3169579f3422080b8ba10105mx * Basic low-level function to reset the PHY.
6f3e57ac9d0b054c3169579f3422080b8ba10105mx * Doesn't incorporate any special-case workarounds.
6f3e57ac9d0b054c3169579f3422080b8ba10105mx * Returns TRUE on success, FALSE if the RESET bit doesn't clear
6f3e57ac9d0b054c3169579f3422080b8ba10105mx * Set the PHY RESET bit, then wait up to 5 ms for it to self-clear
c322ff79f6149528aa6dc5018328f071dcf1e50fmx /* We should wait for 500ms. It's defined in the manual */
6f3e57ac9d0b054c3169579f3422080b8ba10105mx NGE_DEBUG(("nge_phy_reset: FAILED, control now 0x%x", control));
bdb9230ac765cb7af3fc1f4119caf2c5720dceb3Garrett D'Amore if (MII_PHY_MFG(ngep->phy_id) == MII_ID_CICADA) {
6f3e57ac9d0b054c3169579f3422080b8ba10105mx * Synchronise the (copper) PHY's speed/duplex/autonegotiation capabilities
6f3e57ac9d0b054c3169579f3422080b8ba10105mx * and advertisements with the required settings as specified by the various
6f3e57ac9d0b054c3169579f3422080b8ba10105mx * param_* variables that can be poked via the NDD interface.
6f3e57ac9d0b054c3169579f3422080b8ba10105mx * We always reset the PHY and reprogram *all* the relevant registers,
6f3e57ac9d0b054c3169579f3422080b8ba10105mx * not just those changed. This should cause the link to go down, and then
6f3e57ac9d0b054c3169579f3422080b8ba10105mx * back up again once the link is stable and autonegotiation (if enabled)
6f3e57ac9d0b054c3169579f3422080b8ba10105mx * is complete. We should get a link state change interrupt somewhere along
6f3e57ac9d0b054c3169579f3422080b8ba10105mx * the way ...
6f3e57ac9d0b054c3169579f3422080b8ba10105mx * NOTE: <genlock> must already be held by the caller
6f3e57ac9d0b054c3169579f3422080b8ba10105mxstatic void
6f3e57ac9d0b054c3169579f3422080b8ba10105mx "pause %d asym_pause %d "
6f3e57ac9d0b054c3169579f3422080b8ba10105mx "1000fdx %d "
6f3e57ac9d0b054c3169579f3422080b8ba10105mx "100fdx %d 100hdx %d "
6f3e57ac9d0b054c3169579f3422080b8ba10105mx "10fdx %d 10hdx %d ",
6f3e57ac9d0b054c3169579f3422080b8ba10105mx * PHY settings are normally based on the param_* variables,
6f3e57ac9d0b054c3169579f3422080b8ba10105mx * but if any loopback mode is in effect, that takes precedence.
6f3e57ac9d0b054c3169579f3422080b8ba10105mx * NGE supports MAC-internal loopback, PHY-internal loopback,
6f3e57ac9d0b054c3169579f3422080b8ba10105mx * and External loopback at a variety of speeds (with a special
6f3e57ac9d0b054c3169579f3422080b8ba10105mx * cable). In all cases, autoneg is turned OFF, full-duplex
6f3e57ac9d0b054c3169579f3422080b8ba10105mx * is turned ON, and the speed/mastership is forced.
6f3e57ac9d0b054c3169579f3422080b8ba10105mx "pause %d asym_pause %d "
6f3e57ac9d0b054c3169579f3422080b8ba10105mx "1000fdx %d "
6f3e57ac9d0b054c3169579f3422080b8ba10105mx "100fdx %d 100hdx %d "
6f3e57ac9d0b054c3169579f3422080b8ba10105mx "10fdx %d 10hdx %d ",
6f3e57ac9d0b054c3169579f3422080b8ba10105mx * We should have at least one technology capability set;
6f3e57ac9d0b054c3169579f3422080b8ba10105mx * if not, we select a default of 10Mb/s half-duplex
6f3e57ac9d0b054c3169579f3422080b8ba10105mx * Now transform the adv_* variables into the proper settings
6f3e57ac9d0b054c3169579f3422080b8ba10105mx * of the PHY registers ...
6f3e57ac9d0b054c3169579f3422080b8ba10105mx * If autonegotiation is (now) enabled, we want to trigger
6f3e57ac9d0b054c3169579f3422080b8ba10105mx * a new autonegotiation cycle once the PHY has been
6f3e57ac9d0b054c3169579f3422080b8ba10105mx * programmed with the capabilities to be advertised.
6f3e57ac9d0b054c3169579f3422080b8ba10105mx * Munge in any other fixed bits we require ...
6f3e57ac9d0b054c3169579f3422080b8ba10105mx * Restart the PHY and write the new values.
c322ff79f6149528aa6dc5018328f071dcf1e50fmx nge_error(ngep, "nge_update_copper: failed to restart phy");
6f3e57ac9d0b054c3169579f3422080b8ba10105mx * Loopback bit in control register is not reset sticky
6f3e57ac9d0b054c3169579f3422080b8ba10105mx * write it after PHY restart.
6f3e57ac9d0b054c3169579f3422080b8ba10105mx * Read the status from the PHY (which is self-clearing
6f3e57ac9d0b054c3169579f3422080b8ba10105mx * on read!); also read & clear the main (Ethernet) MAC status
6f3e57ac9d0b054c3169579f3422080b8ba10105mx * (the relevant bits of this are write-one-to-clear).
6f3e57ac9d0b054c3169579f3422080b8ba10105mx NGE_DEBUG(("nge_check_copper: link %d/%s, MII status 0x%x "
6f3e57ac9d0b054c3169579f3422080b8ba10105mx * If the PHY status changed, record the time
6f3e57ac9d0b054c3169579f3422080b8ba10105mx * Judge the giga speed by reading control
6f3e57ac9d0b054c3169579f3422080b8ba10105mx * and status register
6f3e57ac9d0b054c3169579f3422080b8ba10105mx * We will only consider the link UP if all the readings
6f3e57ac9d0b054c3169579f3422080b8ba10105mx * are consistent and give meaningful results ...
6f3e57ac9d0b054c3169579f3422080b8ba10105mx linkup &= nge_copper_link_duplex[duplex] != LINK_DUPLEX_UNKNOWN;
6f3e57ac9d0b054c3169579f3422080b8ba10105mx * Record current register values, then reread status
6f3e57ac9d0b054c3169579f3422080b8ba10105mx * register & loop until it stabilises ...
6f3e57ac9d0b054c3169579f3422080b8ba10105mx /* Get the Link Partner Ability */
6f3e57ac9d0b054c3169579f3422080b8ba10105mx mii_exstatus = nge_mii_get16(ngep, MII_1000BASE_T_STATUS);
6f3e57ac9d0b054c3169579f3422080b8ba10105mx ngep->param_link_duplex = nge_copper_link_duplex[duplex];
6f3e57ac9d0b054c3169579f3422080b8ba10105mx NGE_DEBUG(("nge_check_copper: link now %s speed %d duplex %d",
6f3e57ac9d0b054c3169579f3422080b8ba10105mx * Because the network chipset embedded in Ck8-04 bridge is only a mac chipset,
6f3e57ac9d0b054c3169579f3422080b8ba10105mx * the different vendor can use different media(serdes and copper).
6f3e57ac9d0b054c3169579f3422080b8ba10105mx * To make it easier to extend the driver to support more platforms with ck8-04,
6f3e57ac9d0b054c3169579f3422080b8ba10105mx * For example, one platform with serdes support,
6f3e57ac9d0b054c3169579f3422080b8ba10105mx * wrapper phy operation functions.
6f3e57ac9d0b054c3169579f3422080b8ba10105mx * But now, only supply copper phy operations.
6f3e57ac9d0b054c3169579f3422080b8ba10105mx * Here we have to determine which media we're using (copper or serdes).
6f3e57ac9d0b054c3169579f3422080b8ba10105mx * Once that's done, we can initialise the physical layer appropriately.
6f3e57ac9d0b054c3169579f3422080b8ba10105mx /* Get the phy type from MAC2PHY register */
6f3e57ac9d0b054c3169579f3422080b8ba10105mx if ((ngep->phy_mode != RGMII_IN) && (ngep->phy_mode != MII_IN)) {
6f3e57ac9d0b054c3169579f3422080b8ba10105mx * Probe for the type of the PHY.