mr_sas.h revision a1ed883a3c2acc53bbb9a171ef07aeb8eaf78736
/*
* mr_sas.h: header for mr_sas
*
* Solaris MegaRAID driver for SAS2.0 controllers
* Copyright (c) 2008-2012, LSI Logic Corporation.
* All rights reserved.
*
* Version:
* Author:
* Swaminathan K S
* Arun Chandrashekhar
* Manju R
* Rasheed
* Shakeel Bukhari
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
*
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
*
* 3. Neither the name of the author nor the names of its contributors may be
* used to endorse or promote products derived from this software without
* specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
* OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
* DAMAGE.
*/
/*
* Copyright 2013 Nexenta Systems, Inc. All rights reserved.
* Copyright 2015 Garrett D'Amore <garrett@damore.org>
*/
#ifndef _MR_SAS_H_
#define _MR_SAS_H_
#ifdef __cplusplus
extern "C" {
#endif
#include "mr_sas_list.h"
#include "ld_pd_map.h"
/*
* MegaRAID SAS2.0 Driver meta data
*/
#define MRSAS_VERSION "6.503.00.00ILLUMOS"
#define MRSAS_RELDATE "July 30, 2012"
#define MRSAS_TRUE 1
#define MRSAS_FALSE 0
#define ADAPTER_RESET_NOT_REQUIRED 0
#define ADAPTER_RESET_REQUIRED 1
#define PDSUPPORT 1
/*
* MegaRAID SAS2.0 device id conversion definitions.
*/
#define INST2LSIRDCTL(x) ((x) << INST_MINOR_SHIFT)
int rem; \
} else { \
} \
}
/*
* MegaRAID SAS2.0 supported controllers
*/
#define PCI_DEVICE_ID_LSI_2108VDE 0x0078
#define PCI_DEVICE_ID_LSI_2108V 0x0079
#define PCI_DEVICE_ID_LSI_SKINNY 0x0071
#define PCI_DEVICE_ID_LSI_SKINNY_NEW 0x0073
#define PCI_DEVICE_ID_LSI_TBOLT 0x005b
#define PCI_DEVICE_ID_LSI_INVADER 0x005d
#define PCI_DEVICE_ID_LSI_FURY 0x005f
/*
* Register Index for 2108 Controllers.
*/
#define REGISTER_SET_IO_2108 (2)
#define MRSAS_MAX_SGE_CNT 0x50
#define MRSAS_APP_RESERVED_CMDS 32
#define MRSAS_APP_MIN_RESERVED_CMDS 4
#define MRSAS_IOCTL_DRIVER 0x12341234
#define MRSAS_IOCTL_FIRMWARE 0x12345678
#define MRSAS_IOCTL_AEN 0x87654321
#define MRSAS_1_SECOND 1000000
#ifdef PDSUPPORT
#define UNCONFIGURED_GOOD 0x0
#define PD_SYSTEM 0x40
#define MR_EVT_PD_STATE_CHANGE 0x0072
#define MR_EVT_PD_REMOVED_EXT 0x00f8
#define MR_EVT_PD_INSERTED_EXT 0x00f7
#define MR_DCMD_PD_GET_INFO 0x02020000
#define MRSAS_TBOLT_PD_LUN 1
#define MRSAS_TBOLT_PD_TGT_MAX 255
#define MRSAS_TBOLT_GET_PD_MAX(s) ((s)->mr_tbolt_pd_max)
#endif
/* Raid Context Flags */
#define MR_RAID_CTX_RAID_FLAGS_IO_SUB_TYPE_SHIFT 0x4
#define MR_RAID_CTX_RAID_FLAGS_IO_SUB_TYPE_MASK 0x30
typedef enum MR_RAID_FLAGS_IO_SUB_TYPE {
/* Dynamic Enumeration Flags */
#define MRSAS_LD_LUN 0
#define WWN_STRLEN 17
#define LD_SYNC_BIT 1
#define LD_SYNC_SHIFT 14
/* ThunderBolt (TB) specific */
#define MRSAS_THUNDERBOLT_MSG_SIZE 256
#define MRSAS_THUNDERBOLT_MAX_COMMANDS 1024
#define MRSAS_THUNDERBOLT_MAX_REPLY_COUNT 1024
#define MRSAS_THUNDERBOLT_REPLY_SIZE 8
#define MRSAS_THUNDERBOLT_MAX_CHAIN_COUNT 1
#define MPI2_FUNCTION_PASSTHRU_IO_REQUEST 0xF0
#define MPI2_FUNCTION_LD_IO_REQUEST 0xF1
#define MR_EVT_LD_FAST_PATH_IO_STATUS_CHANGED (0xFFFF)
#define MR_INTERNAL_MFI_FRAMES_SMID 1
#define MR_CTRL_EVENT_WAIT_SMID 2
#define MR_INTERNAL_DRIVER_RESET_SMID 3
/*
* =====================================
* MegaRAID SAS2.0 MFI firmware definitions
* =====================================
*/
/*
* MFI stands for MegaRAID SAS2.0 FW Interface. This is just a moniker for
* protocol between the software and firmware. Commands are issued using
* "message frames"
*/
/*
* FW posts its state in upper 4 bits of outbound_msg_0 register
*/
#define MFI_STATE_MASK 0xF0000000
#define MFI_STATE_UNDEFINED 0x00000000
#define MFI_STATE_BB_INIT 0x10000000
#define MFI_STATE_FW_INIT 0x40000000
#define MFI_STATE_WAIT_HANDSHAKE 0x60000000
#define MFI_STATE_FW_INIT_2 0x70000000
#define MFI_STATE_DEVICE_SCAN 0x80000000
#define MFI_STATE_BOOT_MESSAGE_PENDING 0x90000000
#define MFI_STATE_FLUSH_CACHE 0xA0000000
#define MFI_STATE_READY 0xB0000000
#define MFI_STATE_OPERATIONAL 0xC0000000
#define MFI_STATE_FAULT 0xF0000000
#define MRMFI_FRAME_SIZE 64
/*
* During FW init, clear pending cmds & reset state using inbound_msg_0
*
* ABORT : Abort all pending cmds
* READY : Move from OPERATIONAL to READY state; discard queue info
* MFIMODE : Discard (possible) low MFA posted in 64-bit mode (??)
* CLR_HANDSHAKE: FW is waiting for HANDSHAKE from BIOS or Driver
*/
#define MFI_INIT_ABORT 0x00000001
#define MFI_INIT_READY 0x00000002
#define MFI_INIT_MFIMODE 0x00000004
#define MFI_INIT_CLEAR_HANDSHAKE 0x00000008
#define MFI_INIT_HOTPLUG 0x00000010
#define MFI_STOP_ADP 0x00000020
/*
* MFI frame flags
*/
#define MFI_FRAME_POST_IN_REPLY_QUEUE 0x0000
#define MFI_FRAME_DONT_POST_IN_REPLY_QUEUE 0x0001
#define MFI_FRAME_SGL32 0x0000
#define MFI_FRAME_SGL64 0x0002
#define MFI_FRAME_SENSE32 0x0000
#define MFI_FRAME_SENSE64 0x0004
#define MFI_FRAME_DIR_NONE 0x0000
#define MFI_FRAME_DIR_WRITE 0x0008
#define MFI_FRAME_DIR_READ 0x0010
#define MFI_FRAME_DIR_BOTH 0x0018
#define MFI_FRAME_IEEE 0x0020
/*
* Definition for cmd_status
*/
#define MFI_CMD_STATUS_POLL_MODE 0xFF
#define MFI_CMD_STATUS_SYNC_MODE 0xFF
/*
* MFI command opcodes
*/
#define MFI_CMD_OP_INIT 0x00
#define MFI_CMD_OP_LD_READ 0x01
#define MFI_CMD_OP_LD_WRITE 0x02
#define MFI_CMD_OP_LD_SCSI 0x03
#define MFI_CMD_OP_PD_SCSI 0x04
#define MFI_CMD_OP_DCMD 0x05
#define MFI_CMD_OP_ABORT 0x06
#define MFI_CMD_OP_SMP 0x07
#define MFI_CMD_OP_STP 0x08
#define MR_DCMD_CTRL_GET_INFO 0x01010000
#define MR_DCMD_CTRL_CACHE_FLUSH 0x01101000
#define MR_FLUSH_CTRL_CACHE 0x01
#define MR_FLUSH_DISK_CACHE 0x02
#define MR_DCMD_CTRL_SHUTDOWN 0x01050000
#define MRSAS_ENABLE_DRIVE_SPINDOWN 0x01
#define MR_DCMD_CTRL_EVENT_GET_INFO 0x01040100
#define MR_DCMD_CTRL_EVENT_GET 0x01040300
#define MR_DCMD_CTRL_EVENT_WAIT 0x01040500
#define MR_DCMD_LD_GET_PROPERTIES 0x03030000
/*
* Solaris Specific MAX values
*/
#define MAX_SGL 24
/*
* MFI command completion codes
*/
enum MFI_STAT {
MFI_STAT_OK = 0x00,
MFI_STAT_INVALID_CMD = 0x01,
MFI_STAT_INVALID_DCMD = 0x02,
MFI_STAT_INVALID_PARAMETER = 0x03,
MFI_STAT_INVALID_SEQUENCE_NUMBER = 0x04,
MFI_STAT_ABORT_NOT_POSSIBLE = 0x05,
MFI_STAT_APP_HOST_CODE_NOT_FOUND = 0x06,
MFI_STAT_APP_IN_USE = 0x07,
MFI_STAT_APP_NOT_INITIALIZED = 0x08,
MFI_STAT_ARRAY_INDEX_INVALID = 0x09,
MFI_STAT_ARRAY_ROW_NOT_EMPTY = 0x0a,
MFI_STAT_DEVICE_NOT_FOUND = 0x0c,
MFI_STAT_DRIVE_TOO_SMALL = 0x0d,
MFI_STAT_FLASH_ALLOC_FAIL = 0x0e,
MFI_STAT_FLASH_BUSY = 0x0f,
MFI_STAT_FLASH_ERROR = 0x10,
MFI_STAT_FLASH_IMAGE_BAD = 0x11,
MFI_STAT_FLASH_IMAGE_INCOMPLETE = 0x12,
MFI_STAT_FLASH_NOT_OPEN = 0x13,
MFI_STAT_FLASH_NOT_STARTED = 0x14,
MFI_STAT_FLUSH_FAILED = 0x15,
MFI_STAT_HOST_CODE_NOT_FOUNT = 0x16,
MFI_STAT_LD_CC_IN_PROGRESS = 0x17,
MFI_STAT_LD_INIT_IN_PROGRESS = 0x18,
MFI_STAT_LD_LBA_OUT_OF_RANGE = 0x19,
MFI_STAT_LD_MAX_CONFIGURED = 0x1a,
MFI_STAT_LD_NOT_OPTIMAL = 0x1b,
MFI_STAT_LD_RBLD_IN_PROGRESS = 0x1c,
MFI_STAT_LD_RECON_IN_PROGRESS = 0x1d,
MFI_STAT_LD_WRONG_RAID_LEVEL = 0x1e,
MFI_STAT_MAX_SPARES_EXCEEDED = 0x1f,
MFI_STAT_MEMORY_NOT_AVAILABLE = 0x20,
MFI_STAT_MFC_HW_ERROR = 0x21,
MFI_STAT_NO_HW_PRESENT = 0x22,
MFI_STAT_NOT_FOUND = 0x23,
MFI_STAT_NOT_IN_ENCL = 0x24,
MFI_STAT_PD_CLEAR_IN_PROGRESS = 0x25,
MFI_STAT_PD_TYPE_WRONG = 0x26,
MFI_STAT_PR_DISABLED = 0x27,
MFI_STAT_ROW_INDEX_INVALID = 0x28,
MFI_STAT_SAS_CONFIG_INVALID_DATA = 0x2a,
MFI_STAT_SAS_CONFIG_INVALID_PAGE = 0x2b,
MFI_STAT_SAS_CONFIG_INVALID_TYPE = 0x2c,
MFI_STAT_SCSI_DONE_WITH_ERROR = 0x2d,
MFI_STAT_SCSI_IO_FAILED = 0x2e,
MFI_STAT_SHUTDOWN_FAILED = 0x30,
MFI_STAT_TIME_NOT_SET = 0x31,
MFI_STAT_WRONG_STATE = 0x32,
MFI_STAT_LD_OFFLINE = 0x33,
MFI_STAT_INVALID_STATUS = 0xFF
};
enum MR_EVT_CLASS {
MR_EVT_CLASS_DEBUG = -2,
MR_EVT_CLASS_PROGRESS = -1,
MR_EVT_CLASS_INFO = 0,
MR_EVT_CLASS_WARNING = 1,
MR_EVT_CLASS_FATAL = 3,
};
enum MR_EVT_LOCALE {
MR_EVT_LOCALE_LD = 0x0001,
MR_EVT_LOCALE_PD = 0x0002,
MR_EVT_LOCALE_ENCL = 0x0004,
MR_EVT_LOCALE_BBU = 0x0008,
MR_EVT_LOCALE_SAS = 0x0010,
MR_EVT_LOCALE_CTRL = 0x0020,
MR_EVT_LOCALE_CONFIG = 0x0040,
MR_EVT_LOCALE_CLUSTER = 0x0080,
MR_EVT_LOCALE_ALL = 0xffff
};
enum MR_EVT_ARGS {
};
#define MR_EVT_CFG_CLEARED 0x0004
#define MR_EVT_LD_CREATED 0x008a
#define MR_EVT_LD_DELETED 0x008b
#define MR_EVT_CFG_FP_CHANGE 0x017B
enum LD_STATE {
LD_OFFLINE = 0,
LD_DEGRADED = 2,
LD_OPTIMAL = 3,
LD_INVALID = 0xFF
};
enum MRSAS_EVT {
MRSAS_EVT_CONFIG_TGT = 0,
};
#define DMA_OBJ_ALLOCATED 1
#define DMA_OBJ_REALLOCATED 2
#define DMA_OBJ_FREED 3
/*
* dma_obj_t - Our DMA object
* @param buffer : kernel virtual address
* @param size : size of the data to be allocated
* @param acc_handle : access handle
* @param dma_handle : dma handle
* @param dma_cookie : scatter-gather list
* @param dma_attr : dma attributes for this buffer
*
* Our DMA object. The caller must initialize the size and dma attributes
* (dma_attr) fields before allocating the resources.
*/
typedef struct {
} dma_obj_t;
struct mrsas_eventinfo {
struct mrsas_instance *instance;
int tgt;
int lun;
int event;
};
struct mrsas_ld {
};
#ifdef PDSUPPORT
struct mrsas_tbolt_pd {
};
struct mrsas_tbolt_pd_info {
uint8_t a;
struct {
} pathInfo;
};
#endif
typedef struct mrsas_instance {
/* ThunderBolt (TB) specific */
int instance;
int baseaddress;
char iocnode[16];
int fm_capabilities;
/*
* Driver resources unroll flags. The flag is set for resources that
* are needed to be free'd at detach() time.
*/
struct _unroll {
} unroll;
/* function template pointer */
struct mrsas_function_template *func_ptr;
/* MSI interrupts specific */
int intr_type;
int intr_cnt;
int intr_cap;
struct mrsas_ld *mr_ld_list;
/* ThunderBolt (TB) specific */
#ifdef PDSUPPORT
struct mrsas_tbolt_pd *mr_tbolt_pd_list;
#endif
/* Virtual address of request desc frame pool */
/* Physical address of request desc frame pool */
/* Virtual address of reply Frame */
/* Physical address of reply Frame */
/* Physical address of Last reply frame */
struct mrsas_cmd *map_update_cmd;
} mrsas_t;
/*
* Function templates for various controller specific functions
*/
struct mrsas_function_template {
int (*issue_cmd_in_sync_mode)(struct mrsas_instance *,
struct mrsas_cmd *);
int (*issue_cmd_in_poll_mode)(struct mrsas_instance *,
struct mrsas_cmd *);
void (*enable_intr)(struct mrsas_instance *);
void (*disable_intr)(struct mrsas_instance *);
int (*intr_ack)(struct mrsas_instance *);
int (*init_adapter)(struct mrsas_instance *);
/* int (*reset_adapter)(struct mrsas_instance *); */
};
/*
* ### Helper routines ###
*/
/*
* con_log() - console log routine
* @param level : indicates the severity of the message.
* @fparam mt : format string
*
* con_log displays the error messages on the console based on the current
* debug level. Also it attaches the appropriate kernel severity level with
* the message.
*
*
* console messages debug levels
*/
#define CL_NONE 0 /* No debug information */
#ifdef __SUNPRO_C
#define __func__ ""
#endif
/*
* ### SCSA definitions ###
*/
/*
* ### Data structures for ioctl inteface and internal commands ###
*/
/*
* Data direction flags
*/
#define UIOC_RD 0x00001
#define UIOC_WR 0x00002
#define SCP2ADAPTER(scp) \
#define MRDRV_IS_LOGICAL(ap) \
#define HIGH_LEVEL_INTR 1
#define NORMAL_LEVEL_INTR 0
#define IO_TIMEOUT_VAL 0
#define IO_RETRY_COUNT 3
#define MAX_FW_RESET_COUNT 3
/*
* scsa_cmd - Per-command mr private data
* @param cmd_dmahandle : dma handle
* @param cmd_dmacookies : current dma cookies
* @param cmd_pkt : scsi_pkt reference
* @param cmd_dmacount : dma count
* @param cmd_cookie : next cookie
* @param cmd_ncookies : cookies per window
* @param cmd_cookiecnt : cookies per sub-win
* @param cmd_nwin : number of dma windows
* @param cmd_curwin : current dma window
* @param cmd_dma_offset : current window offset
* @param cmd_dma_len : current window length
* @param cmd_flags : private flags
* @param cmd_cdblen : length of cdb
* @param cmd_scblen : length of scb
* @param cmd_buf : command buffer
* @param channel : channel for scsi sub-system
* @param target : target for scsi sub-system
* @param lun : LUN for scsi sub-system
*
* - Allocated at same time as scsi_pkt by scsi_hba_pkt_alloc(9E)
* - Pointed to by pkt_ha_private field in scsi_pkt
*/
struct scsa_cmd {
struct mrsas_device *mrsas_dev;
};
struct mrsas_cmd {
/*
* ThunderBolt(TB) We would be needing to have a placeholder
* for RAID_MSG_IO_REQUEST inside this structure. We are
* supposed to embed the mr_frame inside the RAID_MSG and post
* it down to the firmware.
*/
union mrsas_frame *frame;
};
#define MAX_MGMT_ADAPTERS 1024
#define IOC_SIGNATURE "MR-SAS"
#define IOC_CMD_FIRMWARE 0x0
#define MRSAS_DRIVER_IOCTL_COMMON 0xF0010000
#define MRSAS_DRIVER_IOCTL_DRIVER_VERSION 0xF0010100
#define MRSAS_DRIVER_IOCTL_PCI_INFORMATION 0xF0010200
#define MRSAS_DRIVER_IOCTL_MRRAID_STATISTICS 0xF0010300
#define MRSAS_MAX_SENSE_LENGTH 32
struct mrsas_mgmt_info {
int max_index;
};
#pragma pack(1)
/*
* SAS controller properties
*/
struct mrsas_ctrl_prop {
};
/*
* SAS controller information
*/
struct mrsas_ctrl_info {
/* PCI device information */
struct {
} pci;
/* Host interface information */
struct {
/* Device (backend) interface information */
struct {
/* List of components residing in flash. All str are null terminated */
struct {
char name[8];
char version[32];
char build_date[16];
char built_time[16];
} image_component[8];
/*
* List of flash components that have been flashed on the card, but
* are not in use, pending reset of the adapter. This list will be
* empty if a flash operation has not occurred. All stings are null
* terminated
*/
struct {
char name[8];
char version[32];
char build_date[16];
char build_time[16];
} pending_image_component[8];
char product_name[80];
char serial_no[32];
/*
* Other physical/controller/operation information. Indicates the
* presence of the hardware
*/
struct {
} hw_present;
/* Maximum data transfer sizes */
/* Logical and physical device counts */
/* Memory size information */
/* Error counters */
/* Cluster information */
/* Controller capabilities structures */
struct {
} raid_levels;
struct {
struct {
struct {
struct {
struct {
/* Include the controller properties (changeable items) */
struct mrsas_ctrl_prop properties;
};
/*
* ==================================
* MegaRAID SAS2.0 driver definitions
* ==================================
*/
#define MRDRV_MAX_NUM_CMD 1024
#define MRDRV_MAX_PD_CHANNELS 2
#define MRDRV_MAX_LD_CHANNELS 2
#define MRDRV_MAX_CHANNELS (MRDRV_MAX_PD_CHANNELS + \
#define MRDRV_MAX_DEV_PER_CHANNEL 128
#define MRDRV_DEFAULT_INIT_ID -1
#define MRDRV_MAX_CMD_PER_LUN 1000
#define MRDRV_MAX_LUN 1
#define MRDRV_MAX_LD 64
#define MRDRV_RESET_WAIT_TIME 300
#define MRDRV_RESET_NOTICE_INTERVAL 5
#define MRSAS_IOCTL_CMD 0
#define MRDRV_TGT_VALID 1
/*
* FW can accept both 32 and 64 bit SGLs. We want to allocate 32/64 bit
* SGLs based on the size of dma_addr_t
*/
#define OB_INTR_MASK 0xFFFFFFFF
#define OB_DOORBELL_CLEAR_MASK 0xFFFFFFFF
#define SYSTOIOP_INTERRUPT_MASK 0x80000000
#define OB_SCRATCH_PAD_2_OFF 0xB4
#define WRITE_TBOLT_SEQ_OFF 0x00000004
#define DIAG_TBOLT_RESET_ADAPTER 0x00000004
#define HOST_TBOLT_DIAG_OFF 0x00000008
#define RESET_TBOLT_STATUS_OFF 0x000003C3
#define WRITE_SEQ_OFF 0x000000FC
#define HOST_DIAG_OFF 0x000000F8
#define DIAG_RESET_ADAPTER 0x00000004
#define DIAG_WRITE_ENABLE 0x00000080
#define SYSTOIOP_INTERRUPT_MASK 0x80000000
#define IB_LOW_QPORT 0xC0
#define IB_HIGH_QPORT 0xC4
/*
* All MFI register set macros accept mrsas_register_set*
*/
(v))
/* Thunderbolt specific registers */
#define WR_TBOLT_IB_WRITE_SEQ(v, instance) \
#define WR_MPI2_REPLY_POST_INDEX(v, instance)\
(uint32_t *)\
(v))
#define RD_MPI2_REPLY_POST_INDEX(instance)\
(uint32_t *)\
#define WR_OB_DOORBELL_REGISTER_CLEAR(v, instance)\
(v))
(v))
/*
* When FW is in MFI_STATE_READY or MFI_STATE_OPERATIONAL, the state data
* of Outbound Msg Reg 0 indicates max concurrent cmds supported, max SGEs
* supported per cmd and if 64-bit MFAs (M64) is enabled or disabled.
*/
#define MFI_OB_INTR_STATUS_MASK 0x00000002
/*
* This MFI_REPLY_2108_MESSAGE_INTR flag is used also
* in enable_intr_ppc also. Hence bit 2, i.e. 0x4 has
* been set in this flag along with bit 1.
*/
#define MFI_REPLY_2108_MESSAGE_INTR 0x00000001
#define MFI_REPLY_2108_MESSAGE_INTR_MASK 0x00000005
/* Fusion interrupt mask */
#define MFI_FUSION_ENABLE_INTERRUPT_MASK (0x00000008)
#define MFI_POLL_TIMEOUT_SECS 60
#define MFI_DISABLE_INTR(instance) \
{ \
}
/* By default, the firmware programs for 8 Kbytes of memory */
#define DEFAULT_MFI_MEM_SZ 8192
#define MINIMUM_MFI_MEM_SZ 4096
/* DCMD Message Frame MAILBOX0-11 */
#define DCMD_MBOX_SZ 12
/*
* on_off_property of mrsas_ctrl_prop
* bit0-9, 11-31 are reserved
*/
struct mrsas_register_set {
};
struct mrsas_sge32 {
};
struct mrsas_sge64 {
};
struct mrsas_sge_ieee {
};
union mrsas_sgl {
};
struct mrsas_header {
};
union mrsas_sgl_frame {
};
struct mrsas_init_frame {
};
struct mrsas_init_queue_info {
};
struct mrsas_io_frame {
};
struct mrsas_pthru_frame {
};
struct mrsas_dcmd_frame {
/* uint8_t mbox[DCMD_MBOX_SZ]; */ /* 1Ch */
union { /* 1Ch */
uint8_t b[DCMD_MBOX_SZ];
uint16_t s[6];
uint32_t w[3];
} mbox;
};
struct mrsas_abort_frame {
};
struct mrsas_smp_frame {
};
struct mrsas_stp_frame {
};
union mrsas_frame {
struct mrsas_header hdr;
struct mrsas_init_frame init;
struct mrsas_io_frame io;
struct mrsas_pthru_frame pthru;
struct mrsas_dcmd_frame dcmd;
struct mrsas_abort_frame abort;
struct mrsas_smp_frame smp;
struct mrsas_stp_frame stp;
};
typedef struct mrsas_pd_address {
union {
struct {
} pd_address;
struct {
} encl_address;
}address;
union {
} connected;
union mrsas_evt_class_locale {
struct {
} members;
};
struct mrsas_evt_log_info {
};
struct mrsas_progress {
};
struct mrsas_evtarg_ld {
};
struct mrsas_evtarg_pd {
};
struct mrsas_evt_detail {
union mrsas_evt_class_locale cl;
union {
struct {
struct mrsas_evtarg_pd pd;
} cdbSense;
struct mrsas_evtarg_ld ld;
struct {
struct mrsas_evtarg_ld ld;
} ld_count;
struct {
struct mrsas_evtarg_ld ld;
} ld_lba;
struct {
struct mrsas_evtarg_ld ld;
} ld_owner;
struct {
struct mrsas_evtarg_ld ld;
struct mrsas_evtarg_pd pd;
struct {
struct mrsas_evtarg_ld ld;
struct mrsas_progress prog;
} ld_prog;
struct {
struct mrsas_evtarg_ld ld;
} ld_state;
struct {
struct mrsas_evtarg_ld ld;
} ld_strip;
struct mrsas_evtarg_pd pd;
struct {
struct mrsas_evtarg_pd pd;
} pd_err;
struct {
struct mrsas_evtarg_pd pd;
} pd_lba;
struct {
struct mrsas_evtarg_pd pd;
struct mrsas_evtarg_ld ld;
} pd_lba_ld;
struct {
struct mrsas_evtarg_pd pd;
struct mrsas_progress prog;
} pd_prog;
struct {
struct mrsas_evtarg_pd pd;
} pd_state;
struct {
} pci;
char str[96];
struct {
} time;
struct {
char str[64];
} ecc;
uint8_t b[96];
uint16_t s[48];
uint32_t w[24];
uint64_t d[12];
} args;
char description[128];
};
/* only 63 are usable by the application */
#define MAX_LOGICAL_DRIVES 64
/* only 255 physical devices may be used */
#define MAX_PHYSICAL_DEVICES 256
#define MAX_PD_PER_ENCLOSURE 64
/* maximum disks per array */
#define MAX_ROW_SIZE 32
/* maximum spans per logical drive */
#define MAX_SPAN_DEPTH 8
/* maximum number of arrays a hot spare may be dedicated to */
#define MAX_ARRAYS_DEDICATED 16
/* maximum number of arrays which may exist */
#define MAX_ARRAYS 128
/* maximum number of foreign configs that may ha managed at once */
#define MAX_FOREIGN_CONFIGS 8
/* maximum spares (global and dedicated combined) */
/* maximum possible Target IDs (i.e. 0 to 63) */
#define MAX_TARGET_ID 63
/* maximum number of supported enclosures */
#define MAX_ENCLOSURES 32
/* maximum number of PHYs per controller */
#define MAX_PHYS_PER_CONTROLLER 16
/* maximum number of LDs per array (due to DDF limitations) */
#define MAX_LDS_PER_ARRAY 16
/*
* -----------------------------------------------------------------------------
* -----------------------------------------------------------------------------
*
* Logical Drive commands
*
* -----------------------------------------------------------------------------
* -----------------------------------------------------------------------------
*/
/*
* Input: dcmd.opcode - MR_DCMD_LD_GET_LIST
* dcmd.mbox - reserved
* dcmd.sge IN - ptr to returned MR_LD_LIST structure
* Desc: Return the logical drive list structure
* Status: No error
*/
/*
* defines the logical drive reference structure
*/
typedef union _MR_LD_REF { /* LD reference structure */
struct {
} ld_ref;
} MR_LD_REF; /* 4 bytes */
/*
* defines the logical drive list structure
*/
typedef struct _MR_LD_LIST {
struct {
} MR_LD_LIST;
struct mrsas_drv_ver {
};
#define PCI_TYPE0_ADDRESSES 6
#define PCI_TYPE1_ADDRESSES 2
#define PCI_TYPE2_ADDRESSES 5
struct mrsas_pci_common_header {
union {
struct {
} type_0;
struct {
} type_1;
struct {
struct {
} type_2;
} header;
};
struct mrsas_pci_link_capability {
union {
struct {
} bits;
} cap;
};
struct mrsas_pci_link_status_capability {
union {
struct {
} bits;
} stat_cap;
};
struct mrsas_pci_capabilities {
};
struct mrsas_pci_information
{
struct mrsas_pci_common_header pciHeaderInfo;
struct mrsas_pci_capabilities capability;
};
struct mrsas_ioctl {
union mrsas_sgl_frame sgl_frame;
};
struct mrsas_aen {
};
#pragma pack()
#ifndef DDI_VENDOR_LSI
#define DDI_VENDOR_LSI "LSI"
#endif /* DDI_VENDOR_LSI */
int mrsas_config_scsi_device(struct mrsas_instance *,
struct scsi_device *, dev_info_t **);
#ifdef PDSUPPORT
uint8_t, dev_info_t **);
#endif
int alloc_space_for_mpi2(struct mrsas_instance *);
int mrsas_issue_init_mpi2(struct mrsas_instance *);
int (*)(), caddr_t);
int mrsas_tbolt_tran_start(struct scsi_address *,
register struct scsi_pkt *);
int tbolt_issue_cmd_in_poll_mode(struct mrsas_instance *,
struct mrsas_cmd *);
int tbolt_issue_cmd_in_sync_mode(struct mrsas_instance *,
struct mrsas_cmd *);
void tbolt_enable_intr(struct mrsas_instance *);
void tbolt_disable_intr(struct mrsas_instance *);
int tbolt_intr_ack(struct mrsas_instance *);
struct buf *, int, int (*)());
int mrsas_dma_move(struct mrsas_instance *,
uchar_t);
void tbolt_complete_cmd_in_sync_mode(struct mrsas_instance *,
struct mrsas_cmd *);
int alloc_req_rep_desc(struct mrsas_instance *);
int mrsas_mode_sense_build(struct scsi_pkt *);
void push_pending_mfi_pkt(struct mrsas_instance *,
struct mrsas_cmd *);
int mrsas_issue_pending_cmds(struct mrsas_instance *);
int mrsas_print_pending_cmds(struct mrsas_instance *);
int mrsas_complete_pending_cmds(struct mrsas_instance *);
int create_mfi_frame_pool(struct mrsas_instance *);
void destroy_mfi_frame_pool(struct mrsas_instance *);
int create_mfi_mpi_frame_pool(struct mrsas_instance *);
void destroy_mfi_mpi_frame_pool(struct mrsas_instance *);
int create_mpi2_frame_pool(struct mrsas_instance *);
void destroy_mpi2_frame_pool(struct mrsas_instance *);
void mrsas_tbolt_free_additional_dma_buffer(struct mrsas_instance *);
void free_req_desc_pool(struct mrsas_instance *);
void free_space_for_mpi2(struct mrsas_instance *);
void mrsas_dump_reply_desc(struct mrsas_instance *);
void display_scsi_inquiry(caddr_t);
int mrsas_mode_sense_build(struct scsi_pkt *);
int mrsas_tbolt_get_ld_map_info(struct mrsas_instance *);
int mfi_state_transition_to_ready(struct mrsas_instance *);
/* FMA functions. */
void mrsas_fm_ereport(struct mrsas_instance *, char *);
#ifdef __cplusplus
}
#endif
#endif /* _MR_SAS_H_ */