mii_marvell.c revision cea606427170954e8cfcfa5417f3b60394180cb9
/*
* CDDL HEADER START
*
* The contents of this file are subject to the terms of the
* Common Development and Distribution License (the "License").
* You may not use this file except in compliance with the License.
*
* You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
* See the License for the specific language governing permissions
* and limitations under the License.
*
* When distributing Covered Code, include this CDDL HEADER in each
* file and include the License file at usr/src/OPENSOLARIS.LICENSE.
* If applicable, add the following below this CDDL HEADER, with the
* fields enclosed by brackets "[]" replaced with your own identifying
* information: Portions Copyright [yyyy] [name of copyright owner]
*
* CDDL HEADER END
*/
/*
* Copyright 2009 Sun Microsystems, Inc. All rights reserved.
* Use is subject to license terms.
*/
/*
* MII overrides for Marvell PHYs.
*/
#include "miipriv.h"
#define MV_PSC_TXFIFO_DEPTH 0xc000
#define MV_PSC_RXFIFO_DEPTH 0x3000
#define MV_PSC_FORCE_GOOD_LINK 0x0400
#define MV_PSC_DIS_SCRAMBLER 0x0200
#define MV_PSC_MII_5BIT_EN 0x0100
#define MV_PSC_EN_DETECT_MASK 0x0300
#define MV_PSC_EN_EXT_DISTANCE 0x0080
#define MV_PSC_AUTO_X_MODE 0x0060
#define MV_PSC_AUTO_X_1000T 0x0040
#define MV_PSC_MDIX_MANUAL 0x0010
#define MV_PSC_MDI_MANUAL 0x0000
#define MV_PSC_MODE_AUTO 0x0180
#define MV_PSC_MODE_COPPER 0x0280
#define MV_PSC_MODE_1000BASEX 0x0380
#define MV_PSC_DIS_125CLK 0x0010
#define MV_PSC_MAC_PDOWN 0x0008
#define MV_PSC_SQE_TEST 0x0004
#define MV_PSC_POL_REVERSE 0x0002
#define MV_PSC_JABBER_DIS 0x0001
/* 88E3016 */
#define MV_PSC_AUTO_MDIX 0x0030
#define MV_PSC_SIGDET_POLARITY 0x0040
#define MV_PSC_EXT_DIST 0x0080
#define MV_PSC_FEFI_DIS 0x0100
#define MV_PSC_NLP_GEN_DIS 0x0800
#define MV_PSC_LPNP 0x1000
#define MV_PSC_NLP_CHK_DIS 0x2000
#define MV_PSC_EN_DETECT 0x4000
/* LED control page 3, 88E1116, 88E1149 */
#define MV_PSC_LED_LOS_MASK 0xf000
#define MV_PSC_LED_INIT_MASK 0x0f00
#define MV_PSC_LED_STA1_MASK 0x00f0
#define MV_PSC_LED_STA0_MASK 0x000f
#define MV_PSC_LED_STA0_CTRL(x) (((x)) & MV_PSC_LED_STA0_MASK)
#define MV_INTEN_PULSE_MASK 0x7000
#define MV_INTEN_PULSE_NOSTR 0x0000
#define MV_INTEN_PULSE_21MS 0x1000
#define MV_INTEN_PULSE_42MS 0x2000
#define MV_INTEN_PULSE_84MS 0x3000
#define MV_INTEN_PULSE_170MS 0x4000
#define MV_INTEN_PULSE_340MS 0x5000
#define MV_INTEN_PULSE_670MS 0x6000
#define MV_INTEN_PULSE_1300MS 0x7000
#define MV_INTEN_BLINK_MASK 0x0700
#define MV_INTEN_BLINK_42MS 0x0000
#define MV_INTEN_BLINK_84MS 0x0100
#define MV_INTEN_BLINK_170MS 0x0200
#define MV_INTEN_BLINK_340MS 0x0300
#define MV_INTEN_BLINK_670MS 0x0400
#define MV_EPSC_DOWN_NO_IDLE 0x8000
#define MV_EPSC_FIBER_LOOPBACK 0x4000
#define MV_EPSC_TX_CLK_2_5 0x0060
#define MV_EPSC_TX_CLK_25 0x0070
#define MV_EPSC_TX_CLK_0 0x0000
#define MV_LED_PSEL_COLX 0x00
#define MV_LED_PSEL_ERROR 0x01
#define MV_LED_PSEL_DUPLEX 0x02
#define MV_LED_PSEL_DP_COL 0x03
#define MV_LED_PSEL_SPEED 0x04
#define MV_LED_PSEL_LINK 0x05
#define MV_LED_PSEL_TX 0x06
#define MV_LED_PSEL_RX 0x07
#define MV_LED_PSEL_ACT 0x08
#define MV_LED_PSEL_LNK_RX 0x09
#define MV_LED_PSEL_LNK_ACT 0x0a
#define MV_LED_PSEL_ACT_BL 0x0b
#define MV_LED_PSEL_TX_BL 0x0c
#define MV_LED_PSEL_RX_BL 0x0d
#define MV_LED_PSEL_COLX_BL 0x0e
#define MV_LED_PSEL_INACT 0x0f
#define MV_LED_PSEL_LED2(x) (x << 8)
#define MV_LED_PSEL_LED1(x) (x << 4)
#define MV_LED_PSEL_LED0(x) (x << 0)
static int
{
int rv;
reg |= MV_PSC_AUTO_MDIX;
reg |= MV_PSC_LPNP;
/* enable class A driver for Yukon FE+ A0. */
/* LED2 = ACT blink, LED1 = LINK), LED0 = SPEED */
/* calibration, values not documented */
/* Normal BMCR reset now */
return (rv);
}
static int
{
int rv;
/*
* The PHY apparently needs a soft reset, but supposedly
* retains most of the other critical state.
*/
reg |= MII_CONTROL_RESET;
reg &= ~(MV_PSC_AUTO_MDIX);
reg |= MV_PSC_LPNP;
return (rv);
}
static int
{
int rv;
reg &= ~MV_PSC_POL_REVERSE;
return (rv);
}
static int
{
int rv;
/* make sure that this PHY uses page 0 (copper) */
/* Disable energy detect mode */
reg &= ~MV_PSC_EN_DETECT_MASK;
reg &= ~MV_PSC_POL_REVERSE;
/*
* Fix for signal amplitude in 10BASE-T, undocumented.
* This is from the Marvell reference source code.
*/
/*
* EC_U: IEEE A/B 1000BASE-T symmetry failure
*
* EC_U is rev 0, Ultra 2 is rev 1 (at least the
* unit I have), so we trigger on revid.
*/
}
/* page 3 is led control */
/*
* Weird... undocumented logic in the Intel e1000g driver.
* I'm not sure what these values really do.
*/
return (rv);
}
static int
{
/* make sure that this PHY uses page 0 (copper) */
reg &= ~MV_PSC_POWER_DOWN;
/* Disable energy detect mode */
reg &= ~MV_PSC_EN_DETECT_MASK;
reg &= ~MV_PSC_POL_REVERSE;
/* page 3 is led control */
}
static int
{
/* Disable energy detect mode */
reg &= ~MV_PSC_EN_DETECT_MASK;
reg &= ~MV_PSC_POL_REVERSE;
}
static int
{
/* Disable energy detect mode */
reg &= ~MV_PSC_EN_DETECT_MASK;
reg &= ~MV_PSC_POL_REVERSE;
/* force TX CLOCK to 25 MHz */
}
static int
{
/* interface indicates fiber */
/* Go into locked 1000BASE-X mode */
reg &= ~MV_PSC_MODE_MASK;
} else {
/* Disable energy detect mode */
reg &= ~MV_PSC_EN_DETECT_MASK;
reg &= ~MV_PSC_POL_REVERSE;
}
}
static int
{
/* interface indicates fiber */
} else {
reg &= ~MV_PSC_AUTO_X_MODE;
reg &= ~MV_PSC_POL_REVERSE;
}
/* force TX CLOCK to 25 MHz */
}
static int
{
reg &= ~MV_PSC_AUTO_X_MODE;
reg &= ~MV_PSC_POL_REVERSE;
/* Normal BMCR reset now */
}
static int
{
int rv;
/*
* If not autonegotiating, then we need to reset the PHY according to
* Marvell. I don't think this is according to the spec. Apparently
* the register states are not lost during this.
*/
}
return (rv);
}
{
case MII_OUI_MARVELL:
break;
break;
break;
break;
break;
break;
break;
break;
break;
break;
default:
/* Unknown PHY model */
return (B_FALSE);
}
break;
default:
return (B_FALSE);
}
return (B_TRUE);
}