ixgbe_type.h revision 69b5a878d62fdee1b12e78371ce6cc8abddcad15
/******************************************************************************
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/*$FreeBSD: src/sys/dev/ixgbe/ixgbe_type.h,v 1.14 2012/07/05 20:51:44 jfv Exp $*/
#ifndef _IXGBE_TYPE_H_
#define _IXGBE_TYPE_H_
#include "ixgbe_osdep.h"
/* Vendor ID */
#define IXGBE_INTEL_VENDOR_ID 0x8086
/* Device IDs */
#define IXGBE_DEV_ID_82598 0x10B6
#define IXGBE_DEV_ID_82598_BX 0x1508
#define IXGBE_DEV_ID_82598AF_DUAL_PORT 0x10C6
#define IXGBE_DEV_ID_82598AF_SINGLE_PORT 0x10C7
#define IXGBE_DEV_ID_82598AT 0x10C8
#define IXGBE_DEV_ID_82598AT2 0x150B
#define IXGBE_DEV_ID_82598EB_SFP_LOM 0x10DB
#define IXGBE_DEV_ID_82598EB_CX4 0x10DD
#define IXGBE_DEV_ID_82598_CX4_DUAL_PORT 0x10EC
#define IXGBE_DEV_ID_82598_DA_DUAL_PORT 0x10F1
#define IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM 0x10E1
#define IXGBE_DEV_ID_82598EB_XF_LR 0x10F4
#define IXGBE_DEV_ID_82599_KX4 0x10F7
#define IXGBE_DEV_ID_82599_KX4_MEZZ 0x1514
#define IXGBE_DEV_ID_82599_KR 0x1517
#define IXGBE_DEV_ID_82599_COMBO_BACKPLANE 0x10F8
#define IXGBE_SUBDEV_ID_82599_KX4_KR_MEZZ 0x000C
#define IXGBE_DEV_ID_82599_CX4 0x10F9
#define IXGBE_DEV_ID_82599_SFP 0x10FB
#define IXGBE_SUBDEV_ID_82599_SFP 0x11A9
#define IXGBE_SUBDEV_ID_82599_560FLR 0x17D0
#define IXGBE_DEV_ID_82599_BACKPLANE_FCOE 0x152A
#define IXGBE_DEV_ID_82599_SFP_FCOE 0x1529
#define IXGBE_DEV_ID_82599_SFP_EM 0x1507
#define IXGBE_DEV_ID_82599_SFP_SF2 0x154D
#define IXGBE_DEV_ID_82599EN_SFP 0x1557
#define IXGBE_DEV_ID_82599_XAUI_LOM 0x10FC
#define IXGBE_DEV_ID_82599_T3_LOM 0x151C
#define IXGBE_DEV_ID_82599_VF 0x10ED
#define IXGBE_DEV_ID_X540_VF 0x1515
#define IXGBE_DEV_ID_X540T 0x1528
#define IXGBE_DEV_ID_X540T1 0x1560
/* General Registers */
#define IXGBE_CTRL 0x00000
#define IXGBE_STATUS 0x00008
#define IXGBE_CTRL_EXT 0x00018
#define IXGBE_ESDP 0x00020
#define IXGBE_EODSDP 0x00028
#define IXGBE_I2CCTL 0x00028
#define IXGBE_PHY_GPIO 0x00028
#define IXGBE_MAC_GPIO 0x00030
#define IXGBE_PHYINT_STATUS0 0x00100
#define IXGBE_PHYINT_STATUS1 0x00104
#define IXGBE_PHYINT_STATUS2 0x00108
#define IXGBE_LEDCTL 0x00200
#define IXGBE_FRTIMER 0x00048
#define IXGBE_TCPTIMER 0x0004C
#define IXGBE_CORESPARE 0x00600
#define IXGBE_EXVET 0x05078
/* NVM Registers */
#define IXGBE_EEC 0x10010
#define IXGBE_EERD 0x10014
#define IXGBE_EEWR 0x10018
#define IXGBE_FLA 0x1001C
#define IXGBE_EEMNGCTL 0x10110
#define IXGBE_EEMNGDATA 0x10114
#define IXGBE_FLMNGCTL 0x10118
#define IXGBE_FLMNGDATA 0x1011C
#define IXGBE_FLMNGCNT 0x10120
#define IXGBE_FLOP 0x1013C
#define IXGBE_GRC 0x10200
#define IXGBE_SRAMREL 0x10210
#define IXGBE_PHYDBG 0x10218
/* General Receive Control */
#define IXGBE_VPDDIAG0 0x10204
#define IXGBE_VPDDIAG1 0x10208
/* I2CCTL Bit Masks */
#define IXGBE_I2C_CLK_IN 0x00000001
#define IXGBE_I2C_CLK_OUT 0x00000002
#define IXGBE_I2C_DATA_IN 0x00000004
#define IXGBE_I2C_DATA_OUT 0x00000008
#define IXGBE_I2C_CLOCK_STRETCHING_TIMEOUT 500
/* Interrupt Registers */
#define IXGBE_EICR 0x00800
#define IXGBE_EICS 0x00808
#define IXGBE_EIMS 0x00880
#define IXGBE_EIMC 0x00888
#define IXGBE_EIAC 0x00810
#define IXGBE_EIAM 0x00890
/* 82599 EITR is only 12 bits, with the lower 3 always zero */
/*
* 82598 EITR is 16 bits but set the limits based on the max
* supported by all ixgbe hardware
*/
#define IXGBE_MAX_INT_RATE 488281
#define IXGBE_MIN_INT_RATE 956
#define IXGBE_MAX_EITR 0x00000FF8
#define IXGBE_MIN_EITR 8
#define IXGBE_EITR_ITR_INT_MASK 0x00000FF8
#define IXGBE_EITR_LLI_MOD 0x00008000
#define IXGBE_EITR_CNT_WDIS 0x80000000
#define IXGBE_EITRSEL 0x00894
#define IXGBE_GPIE 0x00898
/* Flow Control Registers */
#define IXGBE_FCADBUL 0x03210
#define IXGBE_FCADBUH 0x03214
#define IXGBE_FCAMACL 0x04328
#define IXGBE_FCAMACH 0x0432C
#define IXGBE_PFCTOP 0x03008
#define IXGBE_FCRTV 0x032A0
#define IXGBE_FCCFG 0x03D00
#define IXGBE_TFCS 0x0CE00
/* Receive DMA Registers */
#define IXGBE_RSCDBU 0x03028
#define IXGBE_RDDCC 0x02F20
#define IXGBE_RXMEMWRAP 0x03190
#define IXGBE_STARCTRL 0x03024
/*
* Split and Replication Receive Control Registers
* 00-15 : 0x02100 + n*4
* 16-64 : 0x01014 + n*0x40
* 64-127: 0x0D014 + (n-64)*0x40
*/
/*
* Rx DCA Control Register:
* 00-15 : 0x02200 + n*4
* 16-64 : 0x0100C + n*0x40
* 64-127: 0x0D00C + (n-64)*0x40
*/
#define IXGBE_RDRXCTL 0x02F00
#define IXGBE_RDRXCTL_RSC_PUSH 0x80
/* 8 of these 0x03C00 - 0x03C1C */
#define IXGBE_RXCTRL 0x03000
#define IXGBE_DROPEN 0x03D04
#define IXGBE_RXPBSIZE_SHIFT 10
/* Receive Registers */
#define IXGBE_RXCSUM 0x05000
#define IXGBE_RFCTL 0x05008
#define IXGBE_DRECCCTL 0x02F08
#define IXGBE_DRECCCTL_DISABLE 0
#define IXGBE_DRECCCTL2 0x02F8C
/* Multicast Table Array - 128 entries */
/* Packet split receive type */
/* array of 4096 1-bit vlan filters */
/*array of 4096 4-bit vlan vmdq indices */
#define IXGBE_FCTRL 0x05080
#define IXGBE_VLNCTRL 0x05088
#define IXGBE_MCSTCTRL 0x05090
#define IXGBE_MRQC 0x05818
#define IXGBE_RQTC 0x0EC70
#define IXGBE_MTQC 0x08120
#define IXGBE_VT_CTL 0x051B0
/* 64 Mailboxes, 16 DW each */
#define IXGBE_QDE 0x2F04
#define IXGBE_RXFECCERR0 0x051B8
#define IXGBE_LLITHRESH 0x0EC90
#define IXGBE_IMIRVP 0x05AC0
#define IXGBE_VMD_CTL 0x0581C
/* Flow Director registers */
#define IXGBE_FDIRCTRL 0x0EE00
#define IXGBE_FDIRHKEY 0x0EE68
#define IXGBE_FDIRSKEY 0x0EE6C
#define IXGBE_FDIRDIP4M 0x0EE3C
#define IXGBE_FDIRSIP4M 0x0EE40
#define IXGBE_FDIRTCPM 0x0EE44
#define IXGBE_FDIRUDPM 0x0EE48
#define IXGBE_FDIRIP6M 0x0EE74
#define IXGBE_FDIRM 0x0EE70
/* Flow Director Stats registers */
#define IXGBE_FDIRFREE 0x0EE38
#define IXGBE_FDIRLEN 0x0EE4C
#define IXGBE_FDIRUSTAT 0x0EE50
#define IXGBE_FDIRFSTAT 0x0EE54
#define IXGBE_FDIRMATCH 0x0EE58
#define IXGBE_FDIRMISS 0x0EE5C
/* Flow Director Programming registers */
#define IXGBE_FDIRIPSA 0x0EE18
#define IXGBE_FDIRIPDA 0x0EE1C
#define IXGBE_FDIRPORT 0x0EE20
#define IXGBE_FDIRVLAN 0x0EE24
#define IXGBE_FDIRHASH 0x0EE28
#define IXGBE_FDIRCMD 0x0EE2C
/* Transmit DMA registers */
#define IXGBE_DTXCTL 0x07E00
#define IXGBE_DMATXCTL 0x04A80
#define IXGBE_PFDTXGSWC 0x08220
#define IXGBE_DTXMXSZRQ 0x08100
#define IXGBE_DTXTCPFLGL 0x04A88
#define IXGBE_DTXTCPFLGH 0x04A8C
#define IXGBE_LBDRPEN 0x0CA00
/* Anti-spoofing defines */
#define IXGBE_SPOOF_MACAS_MASK 0xFF
#define IXGBE_SPOOF_VLANAS_MASK 0xFF00
#define IXGBE_SPOOF_VLANAS_SHIFT 8
#define IXGBE_PFVFSPOOF_REG_COUNT 8
/* 16 of these (0-15) */
/* Tx DCA Control register : 128 of these (0-127) */
#define IXGBE_TIPG 0x0CB00
#define IXGBE_MNGTXMAP 0x0CD10
#define IXGBE_TIPG_FIBER_DEFAULT 3
#define IXGBE_TXPBSIZE_SHIFT 10
/* Wake up registers */
#define IXGBE_WUC 0x05800
#define IXGBE_WUFC 0x05808
#define IXGBE_WUS 0x05810
#define IXGBE_IPAV 0x05838
#define IXGBE_WUPL 0x05900
/* Ext Flexible Host Filter Table */
#define IXGBE_FLEXIBLE_FILTER_COUNT_MAX 4
#define IXGBE_EXT_FLEXIBLE_FILTER_COUNT_MAX 2
/* Each Flexible Filter is at most 128 (0x80) bytes in length */
#define IXGBE_FLEXIBLE_FILTER_SIZE_MAX 128
/* Definitions for power management and wakeup registers */
/* Wake Up Control */
/* Wake Up Filter Control */
/* Mask for Ext. flex filters */
#define IXGBE_WUFC_EXT_FLX_FILTERS 0x00300000
/* Wake Up Status */
#define IXGBE_WUS_LNKC IXGBE_WUFC_LNKC
#define IXGBE_WUS_MAG IXGBE_WUFC_MAG
#define IXGBE_WUS_EX IXGBE_WUFC_EX
#define IXGBE_WUS_MC IXGBE_WUFC_MC
#define IXGBE_WUS_BC IXGBE_WUFC_BC
#define IXGBE_WUS_ARP IXGBE_WUFC_ARP
#define IXGBE_WUS_IPV4 IXGBE_WUFC_IPV4
#define IXGBE_WUS_IPV6 IXGBE_WUFC_IPV6
#define IXGBE_WUS_MNG IXGBE_WUFC_MNG
#define IXGBE_WUS_FLX0 IXGBE_WUFC_FLX0
#define IXGBE_WUS_FLX1 IXGBE_WUFC_FLX1
#define IXGBE_WUS_FLX2 IXGBE_WUFC_FLX2
#define IXGBE_WUS_FLX3 IXGBE_WUFC_FLX3
#define IXGBE_WUS_FLX4 IXGBE_WUFC_FLX4
#define IXGBE_WUS_FLX5 IXGBE_WUFC_FLX5
/* Wake Up Packet Length */
#define IXGBE_WUPL_LENGTH_MASK 0xFFFF
/* DCB registers */
#define IXGBE_DCB_MAX_TRAFFIC_CLASS 8
#define IXGBE_RMCS 0x03D00
#define IXGBE_DPMCS 0x07F40
#define IXGBE_PDPMCS 0x0CD00
#define IXGBE_RUPPBMR 0x050A0
/* Security Control Registers */
#define IXGBE_SECTXCTRL 0x08800
#define IXGBE_SECTXSTAT 0x08804
#define IXGBE_SECTXBUFFAF 0x08808
#define IXGBE_SECTXMINIFG 0x08810
#define IXGBE_SECRXCTRL 0x08D00
#define IXGBE_SECRXSTAT 0x08D04
/* Security Bit Fields and Masks */
#define IXGBE_SECTXCTRL_SECTX_DIS 0x00000001
#define IXGBE_SECTXCTRL_TX_DIS 0x00000002
#define IXGBE_SECTXCTRL_STORE_FORWARD 0x00000004
#define IXGBE_SECTXSTAT_SECTX_RDY 0x00000001
#define IXGBE_SECTXSTAT_ECC_TXERR 0x00000002
#define IXGBE_SECRXCTRL_SECRX_DIS 0x00000001
#define IXGBE_SECRXCTRL_RX_DIS 0x00000002
#define IXGBE_SECRXSTAT_SECRX_RDY 0x00000001
#define IXGBE_SECRXSTAT_ECC_RXERR 0x00000002
/* LinkSec (MacSec) Registers */
#define IXGBE_LSECTXCAP 0x08A00
#define IXGBE_LSECRXCAP 0x08F00
#define IXGBE_LSECTXCTRL 0x08A04
#define IXGBE_LSECTXSA 0x08A10
#define IXGBE_LSECTXPN0 0x08A14
#define IXGBE_LSECTXPN1 0x08A18
#define IXGBE_LSECRXCTRL 0x08F04
#define IXGBE_LSECRXSCL 0x08F08
#define IXGBE_LSECRXSCH 0x08F0C
/* LinkSec (MacSec) Bit Fields and Masks */
#define IXGBE_LSECTXCAP_SUM_MASK 0x00FF0000
#define IXGBE_LSECTXCAP_SUM_SHIFT 16
#define IXGBE_LSECRXCAP_SUM_MASK 0x00FF0000
#define IXGBE_LSECRXCAP_SUM_SHIFT 16
#define IXGBE_LSECTXCTRL_EN_MASK 0x00000003
#define IXGBE_LSECTXCTRL_DISABLE 0x0
#define IXGBE_LSECTXCTRL_AUTH 0x1
#define IXGBE_LSECTXCTRL_AUTH_ENCRYPT 0x2
#define IXGBE_LSECTXCTRL_AISCI 0x00000020
#define IXGBE_LSECTXCTRL_PNTHRSH_MASK 0xFFFFFF00
#define IXGBE_LSECTXCTRL_RSV_MASK 0x000000D8
#define IXGBE_LSECRXCTRL_EN_MASK 0x0000000C
#define IXGBE_LSECRXCTRL_EN_SHIFT 2
#define IXGBE_LSECRXCTRL_DISABLE 0x0
#define IXGBE_LSECRXCTRL_CHECK 0x1
#define IXGBE_LSECRXCTRL_STRICT 0x2
#define IXGBE_LSECRXCTRL_DROP 0x3
#define IXGBE_LSECRXCTRL_PLSH 0x00000040
#define IXGBE_LSECRXCTRL_RP 0x00000080
#define IXGBE_LSECRXCTRL_RSV_MASK 0xFFFFFF33
/* IpSec Registers */
#define IXGBE_IPSTXIDX 0x08900
#define IXGBE_IPSTXSALT 0x08904
#define IXGBE_IPSRXIDX 0x08E00
#define IXGBE_IPSRXSPI 0x08E14
#define IXGBE_IPSRXIPIDX 0x08E18
#define IXGBE_IPSRXSALT 0x08E2C
#define IXGBE_IPSRXMOD 0x08E30
#define IXGBE_SECTXCTRL_STORE_FORWARD_ENABLE 0x4
/* DCB registers */
#define IXGBE_RTRPCS 0x02430
#define IXGBE_RTTDCS 0x04900
#define IXGBE_RTTPCS 0x0CD00
#define IXGBE_RTRUP2TC 0x03020
#define IXGBE_RTTUP2TC 0x0C800
#define IXGBE_RTTDQSEL 0x04904
#define IXGBE_RTTDT1C 0x04908
#define IXGBE_RTTDT1S 0x0490C
#define IXGBE_RTTDTECC 0x04990
#define IXGBE_RTTDTECC_NO_BCN 0x00000100
#define IXGBE_RTTBCNRC 0x04984
#define IXGBE_RTTBCNRC_RS_ENA 0x80000000
#define IXGBE_RTTBCNRC_RF_DEC_MASK 0x00003FFF
#define IXGBE_RTTBCNRC_RF_INT_SHIFT 14
#define IXGBE_RTTBCNRC_RF_INT_MASK \
#define IXGBE_RTTBCNRM 0x04980
/* BCN (for DCB) Registers */
#define IXGBE_RTTBCNRS 0x04988
#define IXGBE_RTTBCNCR 0x08B00
#define IXGBE_RTTBCNACH 0x08B04
#define IXGBE_RTTBCNACL 0x08B08
#define IXGBE_RTTBCNTG 0x04A90
#define IXGBE_RTTBCNIDX 0x08B0C
#define IXGBE_RTTBCNCP 0x08B10
#define IXGBE_RTFRTIMER 0x08B14
#define IXGBE_RTTBCNRTT 0x05150
#define IXGBE_RTTBCNRD 0x0498C
/* FCoE DMA Context Registers */
#define IXGBE_FCBUFF_BUFFSIZE_SHIFT 3
#define IXGBE_FCBUFF_BUFFCNT_SHIFT 8
#define IXGBE_FCBUFF_OFFSET_SHIFT 16
#define IXGBE_FCDMARW_LASTSIZE_SHIFT 16
/* FCoE Filter Context Registers */
/* FCoE Receive Control */
#define IXGBE_FCRXCTRL_FCOEVER_SHIFT 8
/* FCoE Redirection */
/* Stats registers */
#define IXGBE_CRCERRS 0x04000
#define IXGBE_ILLERRC 0x04004
#define IXGBE_ERRBC 0x04008
#define IXGBE_MSPDC 0x04010
#define IXGBE_MLFC 0x04034
#define IXGBE_MRFC 0x04038
#define IXGBE_RLEC 0x04040
#define IXGBE_LXONTXC 0x03F60
#define IXGBE_LXONRXC 0x0CF60
#define IXGBE_LXOFFTXC 0x03F68
#define IXGBE_LXOFFRXC 0x0CF68
#define IXGBE_LXONRXCNT 0x041A4
#define IXGBE_LXOFFRXCNT 0x041A8
#define IXGBE_PRC64 0x0405C
#define IXGBE_PRC127 0x04060
#define IXGBE_PRC255 0x04064
#define IXGBE_PRC511 0x04068
#define IXGBE_PRC1023 0x0406C
#define IXGBE_PRC1522 0x04070
#define IXGBE_GPRC 0x04074
#define IXGBE_BPRC 0x04078
#define IXGBE_MPRC 0x0407C
#define IXGBE_GPTC 0x04080
#define IXGBE_GORCL 0x04088
#define IXGBE_GORCH 0x0408C
#define IXGBE_GOTCL 0x04090
#define IXGBE_GOTCH 0x04094
#define IXGBE_RUC 0x040A4
#define IXGBE_RFC 0x040A8
#define IXGBE_ROC 0x040AC
#define IXGBE_RJC 0x040B0
#define IXGBE_MNGPRC 0x040B4
#define IXGBE_MNGPDC 0x040B8
#define IXGBE_MNGPTC 0x0CF90
#define IXGBE_TORL 0x040C0
#define IXGBE_TORH 0x040C4
#define IXGBE_TPR 0x040D0
#define IXGBE_TPT 0x040D4
#define IXGBE_PTC64 0x040D8
#define IXGBE_PTC127 0x040DC
#define IXGBE_PTC255 0x040E0
#define IXGBE_PTC511 0x040E4
#define IXGBE_PTC1023 0x040E8
#define IXGBE_PTC1522 0x040EC
#define IXGBE_MPTC 0x040F0
#define IXGBE_BPTC 0x040F4
#define IXGBE_XEC 0x04120
#define IXGBE_SSVPC 0x08780
#define IXGBE_O2BGPTC 0x041C4
#define IXGBE_O2BSPC 0x087B0
#define IXGBE_B2OSPC 0x041C0
#define IXGBE_B2OGPRC 0x02F90
#define IXGBE_BUPRC 0x04180
#define IXGBE_BMPRC 0x04184
#define IXGBE_BBPRC 0x04188
#define IXGBE_BUPTC 0x0418C
#define IXGBE_BMPTC 0x04190
#define IXGBE_BBPTC 0x04194
#define IXGBE_BCRCERRS 0x04198
#define IXGBE_BXONRXC 0x0419C
#define IXGBE_BXOFFRXC 0x041E0
#define IXGBE_BXONTXC 0x041E4
#define IXGBE_BXOFFTXC 0x041E8
#define IXGBE_PCRC8ECL 0x0E810
#define IXGBE_PCRC8ECH 0x0E811
#define IXGBE_PCRC8ECH_MASK 0x1F
#define IXGBE_LDPCECL 0x0E820
#define IXGBE_LDPCECH 0x0E821
/* Management */
#define IXGBE_MANC 0x05820
#define IXGBE_MFVAL 0x05824
#define IXGBE_MANC2H 0x05860
#define IXGBE_MIPAF 0x058B0
#define IXGBE_LSWFW 0x15014
#define IXGBE_BMCIPVAL 0x05060
#define IXGBE_BMCIP_IPADDR_TYPE 0x00000001
#define IXGBE_BMCIP_IPADDR_VALID 0x00000002
/* Management Bit Fields and Masks */
#define IXGBE_MANC_EN_BMC2OS_SHIFT 28
/* Firmware Semaphore Register */
#define IXGBE_FWSM_MODE_MASK 0xE
/* ARC Subsystem registers */
#define IXGBE_HICR 0x15F00
#define IXGBE_FWSTS 0x15F0C
#define IXGBE_HSMC0R 0x15F04
#define IXGBE_HSMC1R 0x15F08
#define IXGBE_SWSR 0x15F10
#define IXGBE_HFDR 0x15FE8
/* Driver sets this bit when done to put command in RAM */
#define IXGBE_HICR_C 0x02
#define IXGBE_HICR_FW_RESET_ENABLE 0x40
#define IXGBE_HICR_FW_RESET 0x80
/* PCI-E registers */
#define IXGBE_GCR 0x11000
#define IXGBE_GTV 0x11004
#define IXGBE_FUNCTAG 0x11008
#define IXGBE_GLT 0x1100C
#define IXGBE_PCIEPIPEADR 0x11004
#define IXGBE_PCIEPIPEDAT 0x11008
#define IXGBE_GSCL_1 0x11010
#define IXGBE_GSCL_2 0x11014
#define IXGBE_GSCL_3 0x11018
#define IXGBE_GSCL_4 0x1101C
#define IXGBE_GSCN_0 0x11020
#define IXGBE_GSCN_1 0x11024
#define IXGBE_GSCN_2 0x11028
#define IXGBE_GSCN_3 0x1102C
#define IXGBE_FACTPS 0x10150
#define IXGBE_PCIEANACTL 0x11040
#define IXGBE_SWSM 0x10140
#define IXGBE_FWSM 0x10148
#define IXGBE_GSSR 0x10160
#define IXGBE_MREVID 0x11064
#define IXGBE_DCA_ID 0x11070
#define IXGBE_DCA_CTRL 0x11074
#define IXGBE_SWFW_SYNC IXGBE_GSSR
/* PCI-E registers 82599-Specific */
#define IXGBE_GCR_EXT 0x11050
#define IXGBE_GSCL_5_82599 0x11030
#define IXGBE_GSCL_6_82599 0x11034
#define IXGBE_GSCL_7_82599 0x11038
#define IXGBE_GSCL_8_82599 0x1103C
#define IXGBE_PHYADR_82599 0x11040
#define IXGBE_PHYDAT_82599 0x11044
#define IXGBE_PHYCTL_82599 0x11048
#define IXGBE_PBACLR_82599 0x11068
#define IXGBE_CIAA_82599 0x11088
#define IXGBE_CIAD_82599 0x1108C
#define IXGBE_PICAUSE 0x110B0
#define IXGBE_PIENA 0x110B8
#define IXGBE_CDQ_MBR_82599 0x110B4
#define IXGBE_PCIESPARE 0x110BC
#define IXGBE_MISC_REG_82599 0x110F0
#define IXGBE_ECC_CTRL_0_82599 0x11100
#define IXGBE_ECC_CTRL_1_82599 0x11104
#define IXGBE_ECC_STATUS_82599 0x110E0
#define IXGBE_BAR_CTRL_82599 0x110F4
/* PCI Express Control */
#define IXGBE_GCR_CMPL_TMOUT_MASK 0x0000F000
#define IXGBE_GCR_CMPL_TMOUT_10ms 0x00001000
#define IXGBE_GCR_CMPL_TMOUT_RESEND 0x00010000
#define IXGBE_GCR_CAP_VER2 0x00040000
#define IXGBE_GCR_EXT_MSIX_EN 0x80000000
#define IXGBE_GCR_EXT_BUFFERS_CLEAR 0x40000000
#define IXGBE_GCR_EXT_VT_MODE_16 0x00000001
#define IXGBE_GCR_EXT_VT_MODE_32 0x00000002
#define IXGBE_GCR_EXT_VT_MODE_64 0x00000003
#define IXGBE_GCR_EXT_SRIOV (IXGBE_GCR_EXT_MSIX_EN | \
#define IXGBE_GCR_EXT_VT_MODE_MASK 0x00000003
/* Time Sync Registers */
/* Diagnostic Registers */
#define IXGBE_RDSTATCTL 0x02C20
#define IXGBE_RDHMPN 0x02F08
#define IXGBE_RDPROBE 0x02F20
#define IXGBE_RDMAM 0x02F30
#define IXGBE_RDMAD 0x02F34
#define IXGBE_TDSTATCTL 0x07C20
#define IXGBE_TDHMPN 0x07F08
#define IXGBE_TDHMPN2 0x082FC
#define IXGBE_TXDESCIC 0x082CC
#define IXGBE_TDPROBE 0x07F20
#define IXGBE_TXBUFCTRL 0x0C600
#define IXGBE_TXBUFDATA0 0x0C610
#define IXGBE_TXBUFDATA1 0x0C614
#define IXGBE_TXBUFDATA2 0x0C618
#define IXGBE_TXBUFDATA3 0x0C61C
#define IXGBE_RXBUFCTRL 0x03600
#define IXGBE_RXBUFDATA0 0x03610
#define IXGBE_RXBUFDATA1 0x03614
#define IXGBE_RXBUFDATA2 0x03618
#define IXGBE_RXBUFDATA3 0x0361C
#define IXGBE_RFVAL 0x050A4
#define IXGBE_MDFTC1 0x042B8
#define IXGBE_MDFTC2 0x042C0
#define IXGBE_MDFTFIFO1 0x042C4
#define IXGBE_MDFTFIFO2 0x042C8
#define IXGBE_MDFTS 0x042CC
#define IXGBE_PCIEECCCTL 0x1106C
#define IXGBE_PCIEECCCTL0 0x11100
#define IXGBE_PCIEECCCTL1 0x11104
#define IXGBE_RXDBUECC 0x03F70
#define IXGBE_TXDBUECC 0x0CF70
#define IXGBE_RXDBUEST 0x03F74
#define IXGBE_TXDBUEST 0x0CF74
#define IXGBE_PBTXECC 0x0C300
#define IXGBE_PBRXECC 0x03300
#define IXGBE_GHECCR 0x110B0
/* MAC Registers */
#define IXGBE_PCS1GCFIG 0x04200
#define IXGBE_PCS1GLCTL 0x04208
#define IXGBE_PCS1GLSTA 0x0420C
#define IXGBE_PCS1GDBG0 0x04210
#define IXGBE_PCS1GDBG1 0x04214
#define IXGBE_PCS1GANA 0x04218
#define IXGBE_PCS1GANLP 0x0421C
#define IXGBE_PCS1GANNP 0x04220
#define IXGBE_PCS1GANLPNP 0x04224
#define IXGBE_HLREG0 0x04240
#define IXGBE_HLREG1 0x04244
#define IXGBE_PAP 0x04248
#define IXGBE_MACA 0x0424C
#define IXGBE_APAE 0x04250
#define IXGBE_ARD 0x04254
#define IXGBE_AIS 0x04258
#define IXGBE_MSCA 0x0425C
#define IXGBE_MSRWD 0x04260
#define IXGBE_MLADD 0x04264
#define IXGBE_MHADD 0x04268
#define IXGBE_MAXFRS 0x04268
#define IXGBE_TREG 0x0426C
#define IXGBE_PCSS1 0x04288
#define IXGBE_PCSS2 0x0428C
#define IXGBE_XPCSS 0x04290
#define IXGBE_MFLCN 0x04294
#define IXGBE_SERDESC 0x04298
#define IXGBE_MACS 0x0429C
#define IXGBE_AUTOC 0x042A0
#define IXGBE_LINKS 0x042A4
#define IXGBE_LINKS2 0x04324
#define IXGBE_AUTOC2 0x042A8
#define IXGBE_AUTOC3 0x042AC
#define IXGBE_ANLP1 0x042B0
#define IXGBE_ANLP2 0x042B4
#define IXGBE_MACC 0x04330
#define IXGBE_ATLASCTL 0x04800
#define IXGBE_MMNGC 0x042D0
#define IXGBE_ANLPNP1 0x042D4
#define IXGBE_ANLPNP2 0x042D8
#define IXGBE_KRPCSFC 0x042E0
#define IXGBE_KRPCSS 0x042E4
#define IXGBE_FECS1 0x042E8
#define IXGBE_FECS2 0x042EC
#define IXGBE_SMADARCTL 0x14F10
#define IXGBE_MPVC 0x04318
#define IXGBE_SGMIIC 0x04314
/* Statistics Registers */
#define IXGBE_RXNFGPC 0x041B0
#define IXGBE_RXNFGBCL 0x041B4
#define IXGBE_RXNFGBCH 0x041B8
#define IXGBE_RXDGPC 0x02F50
#define IXGBE_RXDGBCL 0x02F54
#define IXGBE_RXDGBCH 0x02F58
#define IXGBE_RXDDGPC 0x02F5C
#define IXGBE_RXDDGBCL 0x02F60
#define IXGBE_RXDDGBCH 0x02F64
#define IXGBE_RXLPBKGPC 0x02F68
#define IXGBE_RXLPBKGBCL 0x02F6C
#define IXGBE_RXLPBKGBCH 0x02F70
#define IXGBE_RXDLPBKGPC 0x02F74
#define IXGBE_RXDLPBKGBCL 0x02F78
#define IXGBE_RXDLPBKGBCH 0x02F7C
#define IXGBE_TXDGPC 0x087A0
#define IXGBE_TXDGBCL 0x087A4
#define IXGBE_TXDGBCH 0x087A8
#define IXGBE_RXDSTATCTRL 0x02F40
/* Copper Pond 2 link timeout */
#define IXGBE_VALIDATE_LINK_READY_TIMEOUT 50
/* Omer CORECTL */
#define IXGBE_CORECTL 0x014F00
/* BARCTRL */
#define IXGBE_BARCTRL 0x110F4
#define IXGBE_BARCTRL_FLSIZE 0x0700
#define IXGBE_BARCTRL_FLSIZE_SHIFT 8
#define IXGBE_BARCTRL_CSRSIZE 0x2000
/* RSCCTL Bit Masks */
#define IXGBE_RSCCTL_RSCEN 0x01
#define IXGBE_RSCCTL_MAXDESC_1 0x00
#define IXGBE_RSCCTL_MAXDESC_4 0x04
#define IXGBE_RSCCTL_MAXDESC_8 0x08
#define IXGBE_RSCCTL_MAXDESC_16 0x0C
/* RSCDBU Bit Masks */
#define IXGBE_RSCDBU_RSCSMALDIS_MASK 0x0000007F
#define IXGBE_RSCDBU_RSCACKDIS 0x00000080
/* RDRXCTL Bit Masks */
#define IXGBE_RDRXCTL_MVMEN 0x00000020
/* RQTC Bit Masks and Shifts */
#define IXGBE_RQTC_TC0_MASK (0x7 << 0)
/* PSRTYPE.RQPL Bit masks and shift */
#define IXGBE_PSRTYPE_RQPL_MASK 0x7
#define IXGBE_PSRTYPE_RQPL_SHIFT 29
/* CTRL Bit Masks */
/* FACTPS */
/* MHADD Bit Masks */
#define IXGBE_MHADD_MFS_MASK 0xFFFF0000
#define IXGBE_MHADD_MFS_SHIFT 16
/* Extended Device Control */
/* Direct Cache Access (DCA) definitions */
/* MSCA Bit Masks */
#define IXGBE_MSCA_NP_ADDR_SHIFT 0
/* MSRWD bit masks */
#define IXGBE_MSRWD_WRITE_DATA_MASK 0x0000FFFF
#define IXGBE_MSRWD_WRITE_DATA_SHIFT 0
#define IXGBE_MSRWD_READ_DATA_MASK 0xFFFF0000
#define IXGBE_MSRWD_READ_DATA_SHIFT 16
/* Atlas registers */
#define IXGBE_ATLAS_PDN_LPBK 0x24
#define IXGBE_ATLAS_PDN_10G 0xB
#define IXGBE_ATLAS_PDN_1G 0xC
#define IXGBE_ATLAS_PDN_AN 0xD
/* Atlas bit masks */
#define IXGBE_ATLASCTL_WRITE_CMD 0x00010000
#define IXGBE_ATLAS_PDN_TX_REG_EN 0x10
#define IXGBE_ATLAS_PDN_TX_10G_QL_ALL 0xF0
#define IXGBE_ATLAS_PDN_TX_1G_QL_ALL 0xF0
#define IXGBE_ATLAS_PDN_TX_AN_QL_ALL 0xF0
/* Omer bit masks */
#define IXGBE_CORECTL_WRITE_CMD 0x00010000
/* Device Type definitions for new protocol MDIO commands */
#define IXGBE_MDIO_PMA_PMD_DEV_TYPE 0x1
#define IXGBE_MDIO_PCS_DEV_TYPE 0x3
#define IXGBE_MDIO_PHY_XS_DEV_TYPE 0x4
#define IXGBE_MDIO_AUTO_NEG_DEV_TYPE 0x7
#define IXGBE_TWINAX_DEV 1
#define IXGBE_MDIO_VENDOR_SPECIFIC_1_10G_SPEED 0x0018
#define IXGBE_MDIO_VENDOR_SPECIFIC_1_1G_SPEED 0x0010
/* MII clause 22/28 definitions */
#define IXGBE_MDIO_PHY_LOW_POWER_MODE 0x0800
#define IXGBE_MII_RESTART 0x200
#define IXGBE_MII_AUTONEG_COMPLETE 0x20
#define IXGBE_MII_AUTONEG_LINK_UP 0x04
#define IXGBE_MII_AUTONEG_REG 0x0
#define IXGBE_PHY_REVISION_MASK 0xFFFFFFF0
#define IXGBE_MAX_PHY_ADDR 32
/* PHY IDs*/
#define TN1010_PHY_ID 0x00A19410
#define TNX_FW_REV 0xB
#define X540_PHY_ID 0x01540200
#define AQ_FW_REV 0x20
#define QT2022_PHY_ID 0x0043A400
#define ATH_PHY_ID 0x03429050
/* PHY Types */
#define IXGBE_M88E1145_E_PHY_ID 0x01410CD0
/* Special PHY Init Routine */
#define IXGBE_PHY_INIT_OFFSET_NL 0x002B
#define IXGBE_PHY_INIT_END_NL 0xFFFF
#define IXGBE_CONTROL_MASK_NL 0xF000
#define IXGBE_DATA_MASK_NL 0x0FFF
#define IXGBE_CONTROL_SHIFT_NL 12
#define IXGBE_DELAY_NL 0
#define IXGBE_DATA_NL 1
#define IXGBE_CONTROL_NL 0x000F
#define IXGBE_CONTROL_EOL_NL 0x0FFF
#define IXGBE_CONTROL_SOL_NL 0x0000
/* General purpose Interrupt Enable */
#define IXGBE_GPIE_EIAME 0x40000000
#define IXGBE_GPIE_PBA_SUPPORT 0x80000000
#define IXGBE_GPIE_RSC_DELAY_SHIFT 11
/* Packet Buffer Initialization */
#define IXGBE_MAX_PACKET_BUFFERS 8
#define IXGBE_MAX_PB 8
/* Packet buffer allocation strategies */
enum {
PBA_STRATEGY_EQUAL = 0, /* Distribute PB space equally */
#define PBA_STRATEGY_EQUAL PBA_STRATEGY_EQUAL
};
/* Transmit Flow Control status */
#define IXGBE_TFCS_TXOFF 0x00000001
#define IXGBE_TFCS_TXOFF0 0x00000100
#define IXGBE_TFCS_TXOFF1 0x00000200
#define IXGBE_TFCS_TXOFF2 0x00000400
#define IXGBE_TFCS_TXOFF3 0x00000800
#define IXGBE_TFCS_TXOFF4 0x00001000
#define IXGBE_TFCS_TXOFF5 0x00002000
#define IXGBE_TFCS_TXOFF6 0x00004000
#define IXGBE_TFCS_TXOFF7 0x00008000
/* TCP Timer */
#define IXGBE_TCPTIMER_KS 0x00000100
#define IXGBE_TCPTIMER_COUNT_ENABLE 0x00000200
#define IXGBE_TCPTIMER_COUNT_FINISH 0x00000400
#define IXGBE_TCPTIMER_LOOP 0x00000800
#define IXGBE_TCPTIMER_DURATION_MASK 0x000000FF
/* HLREG0 Bit Masks */
/* VMD_CTL bitmasks */
#define IXGBE_VMD_CTL_VMDQ_EN 0x00000001
#define IXGBE_VMD_CTL_VMDQ_FILTER 0x00000002
/* VT_CTL bitmasks */
#define IXGBE_VT_CTL_POOL_SHIFT 7
/* VMOLR bitmasks */
/* VFRE bitmask */
#define IXGBE_VFRE_ENABLE_ALL 0xFFFFFFFF
/* RDHMPN and TDHMPN bitmasks */
#define IXGBE_RDHMPN_RDICADDR 0x007FF800
#define IXGBE_RDHMPN_RDICRDREQ 0x00800000
#define IXGBE_RDHMPN_RDICADDR_SHIFT 11
#define IXGBE_TDHMPN_TDICADDR 0x003FF800
#define IXGBE_TDHMPN_TDICRDREQ 0x00800000
#define IXGBE_TDHMPN_TDICADDR_SHIFT 11
#define IXGBE_RDMAM_MEM_SEL_SHIFT 13
#define IXGBE_RDMAM_DWORD_SHIFT 9
#define IXGBE_RDMAM_DESC_COMP_FIFO 1
#define IXGBE_RDMAM_DFC_CMD_FIFO 2
#define IXGBE_RDMAM_RSC_HEADER_ADDR 3
#define IXGBE_RDMAM_TCN_STATUS_RAM 4
#define IXGBE_RDMAM_WB_COLL_FIFO 5
#define IXGBE_RDMAM_QSC_CNT_RAM 6
#define IXGBE_RDMAM_QSC_FCOE_RAM 7
#define IXGBE_RDMAM_QSC_QUEUE_CNT 8
#define IXGBE_RDMAM_QSC_QUEUE_RAM 0xA
#define IXGBE_RDMAM_QSC_RSC_RAM 0xB
#define IXGBE_RDMAM_DESC_COM_FIFO_RANGE 135
#define IXGBE_RDMAM_DESC_COM_FIFO_COUNT 4
#define IXGBE_RDMAM_DFC_CMD_FIFO_RANGE 48
#define IXGBE_RDMAM_DFC_CMD_FIFO_COUNT 7
#define IXGBE_RDMAM_RSC_HEADER_ADDR_RANGE 32
#define IXGBE_RDMAM_RSC_HEADER_ADDR_COUNT 4
#define IXGBE_RDMAM_TCN_STATUS_RAM_RANGE 256
#define IXGBE_RDMAM_TCN_STATUS_RAM_COUNT 9
#define IXGBE_RDMAM_WB_COLL_FIFO_RANGE 8
#define IXGBE_RDMAM_WB_COLL_FIFO_COUNT 4
#define IXGBE_RDMAM_QSC_CNT_RAM_RANGE 64
#define IXGBE_RDMAM_QSC_CNT_RAM_COUNT 4
#define IXGBE_RDMAM_QSC_FCOE_RAM_RANGE 512
#define IXGBE_RDMAM_QSC_FCOE_RAM_COUNT 5
#define IXGBE_RDMAM_QSC_QUEUE_CNT_RANGE 32
#define IXGBE_RDMAM_QSC_QUEUE_CNT_COUNT 4
#define IXGBE_RDMAM_QSC_QUEUE_RAM_RANGE 128
#define IXGBE_RDMAM_QSC_QUEUE_RAM_COUNT 8
#define IXGBE_RDMAM_QSC_RSC_RAM_RANGE 32
#define IXGBE_RDMAM_QSC_RSC_RAM_COUNT 8
#define IXGBE_TXDESCIC_READY 0x80000000
/* Receive Checksum Control */
/* FCRTL Bit Masks */
/* PAP bit masks*/
/* RMCS Bit Masks */
/* Receive Arbitration Control: 0 Round Robin, 1 DFP */
#define IXGBE_RMCS_RAC 0x00000004
/* Deficit Fixed Prio ena */
#define IXGBE_RMCS_DFP IXGBE_RMCS_RAC
/* FCCFG Bit Masks */
/* Interrupt register bitmasks */
/* Extended Interrupt Cause Read */
/* Extended Interrupt Cause Set */
/* Extended Interrupt Mask Set */
/* Extended Interrupt Mask Clear */
#define IXGBE_EIMS_ENABLE_MASK ( \
IXGBE_EIMS_LSC | \
/* Immediate Interrupt Rx (A.K.A. Low Latency Interrupt) */
#define IXGBE_MAX_FTQF_FILTERS 128
#define IXGBE_FTQF_PROTOCOL_MASK 0x00000003
#define IXGBE_FTQF_PROTOCOL_TCP 0x00000000
#define IXGBE_FTQF_PROTOCOL_UDP 0x00000001
#define IXGBE_FTQF_PROTOCOL_SCTP 2
#define IXGBE_FTQF_PRIORITY_MASK 0x00000007
#define IXGBE_FTQF_PRIORITY_SHIFT 2
#define IXGBE_FTQF_POOL_MASK 0x0000003F
#define IXGBE_FTQF_POOL_SHIFT 8
#define IXGBE_FTQF_5TUPLE_MASK_MASK 0x0000001F
#define IXGBE_FTQF_5TUPLE_MASK_SHIFT 25
#define IXGBE_FTQF_SOURCE_ADDR_MASK 0x1E
#define IXGBE_FTQF_DEST_ADDR_MASK 0x1D
#define IXGBE_FTQF_SOURCE_PORT_MASK 0x1B
#define IXGBE_FTQF_DEST_PORT_MASK 0x17
#define IXGBE_FTQF_PROTOCOL_COMP_MASK 0x0F
#define IXGBE_FTQF_POOL_MASK_EN 0x40000000
#define IXGBE_FTQF_QUEUE_ENABLE 0x80000000
/* Interrupt clear mask */
#define IXGBE_IRQ_CLEAR_MASK 0xFFFFFFFF
/* Interrupt Vector Allocation Registers */
#define IXGBE_IVAR_REG_NUM 25
#define IXGBE_IVAR_REG_NUM_82599 64
#define IXGBE_IVAR_TXRX_ENTRY 96
#define IXGBE_IVAR_RX_ENTRY 64
#define IXGBE_IVAR_TX_ENTRY 32
#define IXGBE_MAX_ETQF_FILTERS 8
#define IXGBE_ETQF_POOL_SHIFT 20
#define IXGBE_ETQS_RX_QUEUE_SHIFT 16
/*
* ETQF filter list: one static filter per filter consumer. This is
* to avoid filter collisions later. Add new filters
* here!!
*
* Current filters:
* EAPOL 802.1x (0x888e): Filter 0
* FCoE (0x8906): Filter 2
* 1588 (0x88f7): Filter 3
* FIP (0x8914): Filter 4
*/
#define IXGBE_ETQF_FILTER_EAPOL 0
#define IXGBE_ETQF_FILTER_FCOE 2
#define IXGBE_ETQF_FILTER_1588 3
#define IXGBE_ETQF_FILTER_FIP 4
/* VLAN Control Bit Masks */
/* VLAN pool filtering masks */
#define IXGBE_VLVF_ENTRIES 64
#define IXGBE_VLVF_VLANID_MASK 0x00000FFF
/* Per VF Port VLAN insertion rules */
/* STATUS Bit Masks */
/* ESDP Bit Masks */
/* LEDCTL Bit Masks */
#define IXGBE_LED_IVRT_BASE 0x00000040
#define IXGBE_LED_BLINK_BASE 0x00000080
#define IXGBE_LED_MODE_MASK_BASE 0x0000000F
/* LED modes */
#define IXGBE_LED_LINK_UP 0x0
#define IXGBE_LED_LINK_10G 0x1
#define IXGBE_LED_MAC 0x2
#define IXGBE_LED_FILTER 0x3
#define IXGBE_LED_LINK_ACTIVE 0x4
#define IXGBE_LED_LINK_1G 0x5
#define IXGBE_LED_ON 0xE
#define IXGBE_LED_OFF 0xF
/* AUTOC Bit Masks */
#define IXGBE_AUTOC_KX4_KX_SUPP_MASK 0xC0000000
#define IXGBE_AUTOC_KX4_SUPP 0x80000000
#define IXGBE_AUTOC_KX_SUPP 0x40000000
#define IXGBE_AUTOC_PAUSE 0x30000000
#define IXGBE_AUTOC_ASM_PAUSE 0x20000000
#define IXGBE_AUTOC_SYM_PAUSE 0x10000000
#define IXGBE_AUTOC_RF 0x08000000
#define IXGBE_AUTOC_PD_TMR 0x06000000
#define IXGBE_AUTOC_AN_RX_LOOSE 0x01000000
#define IXGBE_AUTOC_AN_RX_DRIFT 0x00800000
#define IXGBE_AUTOC_AN_RX_ALIGN 0x007C0000
#define IXGBE_AUTOC_FECA 0x00040000
#define IXGBE_AUTOC_FECR 0x00020000
#define IXGBE_AUTOC_KR_SUPP 0x00010000
#define IXGBE_AUTOC_AN_RESTART 0x00001000
#define IXGBE_AUTOC_FLU 0x00000001
#define IXGBE_AUTOC_LMS_SHIFT 13
#define IXGBE_AUTOC_1G_PMA_PMD_MASK 0x00000200
#define IXGBE_AUTOC_1G_PMA_PMD_SHIFT 9
#define IXGBE_AUTOC_10G_PMA_PMD_MASK 0x00000180
#define IXGBE_AUTOC_10G_PMA_PMD_SHIFT 7
#define IXGBE_AUTOC2_UPPER_MASK 0xFFFF0000
#define IXGBE_AUTOC2_10G_SERIAL_PMA_PMD_MASK 0x00030000
#define IXGBE_AUTOC2_10G_SERIAL_PMA_PMD_SHIFT 16
#define IXGBE_MACC_FLU 0x00000001
#define IXGBE_MACC_FSV_10G 0x00030000
#define IXGBE_MACC_FS 0x00040000
#define IXGBE_MAC_RX2TX_LPBK 0x00000002
/* LINKS Bit Masks */
#define IXGBE_LINKS_KX_AN_COMP 0x80000000
#define IXGBE_LINKS_UP 0x40000000
#define IXGBE_LINKS_SPEED 0x20000000
#define IXGBE_LINKS_MODE 0x18000000
#define IXGBE_LINKS_RX_MODE 0x06000000
#define IXGBE_LINKS_TX_MODE 0x01800000
#define IXGBE_LINKS_XGXS_EN 0x00400000
#define IXGBE_LINKS_SGMII_EN 0x02000000
#define IXGBE_LINKS_PCS_1G_EN 0x00200000
#define IXGBE_LINKS_1G_AN_EN 0x00100000
#define IXGBE_LINKS_KX_AN_IDLE 0x00080000
#define IXGBE_LINKS_1G_SYNC 0x00040000
#define IXGBE_LINKS_10G_ALIGN 0x00020000
#define IXGBE_LINKS_10G_LANE_SYNC 0x00017000
#define IXGBE_LINKS_TL_FAULT 0x00001000
#define IXGBE_LINKS_SIGNAL 0x00000F00
#define IXGBE_LINKS_SPEED_82599 0x30000000
#define IXGBE_LINKS_SPEED_10G_82599 0x30000000
#define IXGBE_LINKS_SPEED_1G_82599 0x20000000
#define IXGBE_LINKS_SPEED_100_82599 0x10000000
#define IXGBE_LINKS2_AN_SUPPORTED 0x00000040
/* PCS1GLSTA Bit Masks */
#define IXGBE_PCS1GLSTA_LINK_OK 1
#define IXGBE_PCS1GLSTA_SYNK_OK 0x10
#define IXGBE_PCS1GLSTA_AN_COMPLETE 0x10000
#define IXGBE_PCS1GLSTA_AN_PAGE_RX 0x20000
#define IXGBE_PCS1GLSTA_AN_TIMED_OUT 0x40000
#define IXGBE_PCS1GLSTA_AN_REMOTE_FAULT 0x80000
#define IXGBE_PCS1GLSTA_AN_ERROR_RWS 0x100000
#define IXGBE_PCS1GANA_SYM_PAUSE 0x80
#define IXGBE_PCS1GANA_ASM_PAUSE 0x100
/* PCS1GLCTL Bit Masks */
#define IXGBE_PCS1GLCTL_FLV_LINK_UP 1
#define IXGBE_PCS1GLCTL_FORCE_LINK 0x20
#define IXGBE_PCS1GLCTL_LOW_LINK_LATCH 0x40
#define IXGBE_PCS1GLCTL_AN_ENABLE 0x10000
#define IXGBE_PCS1GLCTL_AN_RESTART 0x20000
/* ANLP1 Bit Masks */
#define IXGBE_ANLP1_PAUSE 0x0C00
#define IXGBE_ANLP1_SYM_PAUSE 0x0400
#define IXGBE_ANLP1_ASM_PAUSE 0x0800
#define IXGBE_ANLP1_AN_STATE_MASK 0x000f0000
/* SW Semaphore Register bitmasks */
/* SW_FW_SYNC/GSSR definitions */
#define IXGBE_GSSR_EEP_SM 0x0001
#define IXGBE_GSSR_PHY0_SM 0x0002
#define IXGBE_GSSR_PHY1_SM 0x0004
#define IXGBE_GSSR_MAC_CSR_SM 0x0008
#define IXGBE_GSSR_FLASH_SM 0x0010
#define IXGBE_GSSR_SW_MNG_SM 0x0400
/* FW Status register bitmask */
/* EEC Register */
#define IXGBE_EEC_FWE_SHIFT 4
/* EEPROM Addressing bits based on type (0-small, 1-large) */
#define IXGBE_EEC_ADDR_SIZE 0x00000400
#define IXGBE_EEC_SIZE_SHIFT 11
#define IXGBE_EEPROM_WORD_SIZE_SHIFT 6
#define IXGBE_EEPROM_OPCODE_BITS 8
/* Part Number String Length */
#define IXGBE_PBANUM_LENGTH 11
/* Checksum and EEPROM pointers */
#define IXGBE_PBANUM_PTR_GUARD 0xFAFA
#define IXGBE_EEPROM_CHECKSUM 0x3F
#define IXGBE_EEPROM_SUM 0xBABA
#define IXGBE_PCIE_ANALOG_PTR 0x03
#define IXGBE_ATLAS0_CONFIG_PTR 0x04
#define IXGBE_PHY_PTR 0x04
#define IXGBE_ATLAS1_CONFIG_PTR 0x05
#define IXGBE_OPTION_ROM_PTR 0x05
#define IXGBE_PCIE_GENERAL_PTR 0x06
#define IXGBE_PCIE_CONFIG0_PTR 0x07
#define IXGBE_PCIE_CONFIG1_PTR 0x08
#define IXGBE_CORE0_PTR 0x09
#define IXGBE_CORE1_PTR 0x0A
#define IXGBE_MAC0_PTR 0x0B
#define IXGBE_MAC1_PTR 0x0C
#define IXGBE_CSR0_CONFIG_PTR 0x0D
#define IXGBE_CSR1_CONFIG_PTR 0x0E
#define IXGBE_FW_PTR 0x0F
#define IXGBE_PBANUM0_PTR 0x15
#define IXGBE_PBANUM1_PTR 0x16
#define IXGBE_ALT_MAC_ADDR_PTR 0x37
#define IXGBE_FREE_SPACE_PTR 0X3E
#define IXGBE_SAN_MAC_ADDR_PTR 0x28
#define IXGBE_DEVICE_CAPS 0x2C
#define IXGBE_SERIAL_NUMBER_MAC_ADDR 0x11
#define IXGBE_PCIE_MSIX_82599_CAPS 0x72
#define IXGBE_MAX_MSIX_VECTORS_82599 0x40
#define IXGBE_PCIE_MSIX_82598_CAPS 0x62
#define IXGBE_MAX_MSIX_VECTORS_82598 0x13
/* MSI-X capability fields masks */
#define IXGBE_PCIE_MSIX_TBL_SZ_MASK 0x7FF
/* Legacy EEPROM word offsets */
#define IXGBE_ISCSI_BOOT_CAPS 0x0033
#define IXGBE_ISCSI_SETUP_PORT_0 0x0030
#define IXGBE_ISCSI_SETUP_PORT_1 0x0034
/* EEPROM Commands - SPI */
#define IXGBE_EEPROM_STATUS_RDY_SPI 0x01
/* EEPROM reset Write Enable latch */
#define IXGBE_EEPROM_WRDI_OPCODE_SPI 0x04
/* EEPROM Read Register */
#define IXGBE_NVM_POLL_READ 0 /* Flag for polling for rd complete */
#define IXGBE_ETH_LENGTH_OF_ADDRESS 6
#define IXGBE_EEPROM_PAGE_SIZE_MAX 128
#ifndef IXGBE_EEPROM_GRANT_ATTEMPTS
#endif
/* Number of 5 microseconds we wait for EERD read and
* EERW write to complete */
#define IXGBE_EERD_EEWR_ATTEMPTS 100000
/* # attempts we wait for flush update to complete */
#define IXGBE_FLUDONE_ATTEMPTS 20000
#define IXGBE_SAN_MAC_ADDR_PORT0_OFFSET 0x0
#define IXGBE_SAN_MAC_ADDR_PORT1_OFFSET 0x3
#define IXGBE_DEVICE_CAPS_ALLOW_ANY_SFP 0x1
#define IXGBE_DEVICE_CAPS_FCOE_OFFLOADS 0x2
#define IXGBE_FW_LESM_PARAMETERS_PTR 0x2
#define IXGBE_FW_LESM_STATE_1 0x1
#define IXGBE_FW_PASSTHROUGH_PATCH_CONFIG_PTR 0x4
#define IXGBE_FW_PATCH_VERSION_4 0x7
/* PCI Bus Info */
#define IXGBE_PCI_DEVICE_STATUS 0xAA
#define IXGBE_PCI_DEVICE_STATUS_TRANSACTION_PENDING 0x0020
#define IXGBE_PCI_LINK_STATUS 0xB2
#define IXGBE_PCI_DEVICE_CONTROL2 0xC8
#define IXGBE_PCI_LINK_WIDTH 0x3F0
#define IXGBE_PCI_LINK_WIDTH_1 0x10
#define IXGBE_PCI_LINK_WIDTH_2 0x20
#define IXGBE_PCI_LINK_WIDTH_4 0x40
#define IXGBE_PCI_LINK_WIDTH_8 0x80
#define IXGBE_PCI_LINK_SPEED 0xF
#define IXGBE_PCI_LINK_SPEED_2500 0x1
#define IXGBE_PCI_LINK_SPEED_5000 0x2
#define IXGBE_PCI_LINK_SPEED_8000 0x3
#define IXGBE_PCI_HEADER_TYPE_REGISTER 0x0E
#define IXGBE_PCI_HEADER_TYPE_MULTIFUNC 0x80
#define IXGBE_PCI_DEVICE_CONTROL2_16ms 0x0005
/* Number of 100 microseconds we wait for PCI Express master disable */
#define IXGBE_PCI_MASTER_DISABLE_TIMEOUT 800
/* Check whether address is multicast. This is little-endian specific check.*/
#define IXGBE_IS_MULTICAST(Address) \
/* Check whether an address is broadcast. */
#define IXGBE_IS_BROADCAST(Address) \
/* RAH */
#define IXGBE_RAH_VIND_MASK 0x003C0000
#define IXGBE_RAH_VIND_SHIFT 18
#define IXGBE_RAH_AV 0x80000000
#define IXGBE_CLEAR_VMDQ_ALL 0xFFFFFFFF
/* Header split receive */
#define IXGBE_RFCTL_ISCSI_DIS 0x00000001
#define IXGBE_RFCTL_ISCSI_DWC_MASK 0x0000003E
#define IXGBE_RFCTL_ISCSI_DWC_SHIFT 1
#define IXGBE_RFCTL_RSC_DIS 0x00000010
#define IXGBE_RFCTL_NFSW_DIS 0x00000040
#define IXGBE_RFCTL_NFSR_DIS 0x00000080
#define IXGBE_RFCTL_NFS_VER_MASK 0x00000300
#define IXGBE_RFCTL_NFS_VER_SHIFT 8
#define IXGBE_RFCTL_NFS_VER_2 0
#define IXGBE_RFCTL_NFS_VER_3 1
#define IXGBE_RFCTL_NFS_VER_4 2
#define IXGBE_RFCTL_IPV6_DIS 0x00000400
#define IXGBE_RFCTL_IPV6_XSUM_DIS 0x00000800
#define IXGBE_RFCTL_IPFRSP_DIS 0x00004000
#define IXGBE_RFCTL_IPV6_EX_DIS 0x00010000
#define IXGBE_RFCTL_NEW_IPV6_EXT_DIS 0x00020000
/* Transmit Config masks */
/* Enable short packet padding to 64 bytes */
#define IXGBE_TX_PAD_ENABLE 0x00000400
/* This allows for 16K packets + 4k for vlan */
#define IXGBE_MAX_FRAME_SZ 0x40040000
/* Receive Config masks */
#define IXGBE_RXDCTL_RLPML_EN 0x00008000
#define IXGBE_TSAUXC_EN_CLK 0x00000004
#define IXGBE_TSAUXC_SYNCLK 0x00000008
#define IXGBE_TSAUXC_SDP0_INT 0x00000040
#define IXGBE_TSYNCRXCTL_TYPE_L2_V2 0x00
#define IXGBE_TSYNCRXCTL_TYPE_L4_V1 0x02
#define IXGBE_TSYNCRXCTL_TYPE_L2_L4_V2 0x04
#define IXGBE_TSYNCRXCTL_TYPE_EVENT_V2 0x0A
#define IXGBE_RXMTRL_V1_CTRLT_MASK 0x000000FF
#define IXGBE_RXMTRL_V1_SYNC_MSG 0x00
#define IXGBE_RXMTRL_V1_DELAY_REQ_MSG 0x01
#define IXGBE_RXMTRL_V1_FOLLOWUP_MSG 0x02
#define IXGBE_RXMTRL_V1_DELAY_RESP_MSG 0x03
#define IXGBE_RXMTRL_V1_MGMT_MSG 0x04
#define IXGBE_RXMTRL_V2_MSGID_MASK 0x0000FF00
#define IXGBE_RXMTRL_V2_SYNC_MSG 0x0000
#define IXGBE_RXMTRL_V2_DELAY_REQ_MSG 0x0100
#define IXGBE_RXMTRL_V2_PDELAY_REQ_MSG 0x0200
#define IXGBE_RXMTRL_V2_PDELAY_RESP_MSG 0x0300
#define IXGBE_RXMTRL_V2_FOLLOWUP_MSG 0x0800
#define IXGBE_RXMTRL_V2_DELAY_RESP_MSG 0x0900
#define IXGBE_RXMTRL_V2_PDELAY_FOLLOWUP_MSG 0x0A00
#define IXGBE_RXMTRL_V2_ANNOUNCE_MSG 0x0B00
#define IXGBE_RXMTRL_V2_SIGNALLING_MSG 0x0C00
#define IXGBE_RXMTRL_V2_MGMT_MSG 0x0D00
/* Receive Priority Flow Control Enable */
#define IXGBE_FCTRL_RPFCE 0x00004000
/* Multiple Receive Queue Control */
#define IXGBE_MRQC_RSS_FIELD_MASK 0xFFFF0000
#define IXGBE_MRQC_RSS_FIELD_IPV4_TCP 0x00010000
#define IXGBE_MRQC_RSS_FIELD_IPV4 0x00020000
#define IXGBE_MRQC_RSS_FIELD_IPV6_EX_TCP 0x00040000
#define IXGBE_MRQC_RSS_FIELD_IPV6_EX 0x00080000
#define IXGBE_MRQC_RSS_FIELD_IPV6 0x00100000
#define IXGBE_MRQC_RSS_FIELD_IPV6_TCP 0x00200000
#define IXGBE_MRQC_RSS_FIELD_IPV4_UDP 0x00400000
#define IXGBE_MRQC_RSS_FIELD_IPV6_UDP 0x00800000
#define IXGBE_MRQC_RSS_FIELD_IPV6_EX_UDP 0x01000000
#define IXGBE_MRQC_L3L4TXSWEN 0x00008000
/* Queue Drop Enable */
#define IXGBE_QDE_ENABLE 0x00000001
#define IXGBE_QDE_IDX_MASK 0x00007F00
#define IXGBE_QDE_IDX_SHIFT 8
#define IXGBE_QDE_WRITE 0x00010000
#define IXGBE_QDE_READ 0x00020000
#define IXGBE_RXDADV_IPSEC_STATUS_SECP 0x00020000
#define IXGBE_RXDADV_IPSEC_ERROR_INVALID_PROTOCOL 0x08000000
#define IXGBE_RXDADV_IPSEC_ERROR_INVALID_LENGTH 0x10000000
#define IXGBE_RXDADV_IPSEC_ERROR_AUTH_FAILED 0x18000000
#define IXGBE_RXDADV_IPSEC_ERROR_BIT_MASK 0x18000000
/* Multiple Transmit Queue Command Register */
/* Receive Descriptor bit definitions */
#define IXGBE_RXDADV_NEXTP_SHIFT 0x00000004
#define IXGBE_RXD_PRI_SHIFT 13
#define IXGBE_RXD_CFI_SHIFT 12
/* PSRTYPE bit definitions */
#define IXGBE_PSRTYPE_TCPHDR 0x00000010
#define IXGBE_PSRTYPE_UDPHDR 0x00000020
#define IXGBE_PSRTYPE_IPV4HDR 0x00000100
#define IXGBE_PSRTYPE_IPV6HDR 0x00000200
#define IXGBE_PSRTYPE_L2HDR 0x00001000
/* SRRCTL bit definitions */
#define IXGBE_SRRCTL_RDMTS_SHIFT 22
#define IXGBE_SRRCTL_RDMTS_MASK 0x01C00000
#define IXGBE_SRRCTL_DROP_EN 0x10000000
#define IXGBE_SRRCTL_BSIZEPKT_MASK 0x0000007F
#define IXGBE_SRRCTL_BSIZEHDR_MASK 0x00003F00
#define IXGBE_SRRCTL_DESCTYPE_LEGACY 0x00000000
#define IXGBE_SRRCTL_DESCTYPE_ADV_ONEBUF 0x02000000
#define IXGBE_SRRCTL_DESCTYPE_HDR_SPLIT 0x04000000
#define IXGBE_SRRCTL_DESCTYPE_HDR_REPLICATION_LARGE_PKT 0x08000000
#define IXGBE_SRRCTL_DESCTYPE_HDR_SPLIT_ALWAYS 0x0A000000
#define IXGBE_SRRCTL_DESCTYPE_MASK 0x0E000000
#define IXGBE_RXDPS_HDRSTAT_HDRSP 0x00008000
#define IXGBE_RXDPS_HDRSTAT_HDRLEN_MASK 0x000003FF
#define IXGBE_RXDADV_RSSTYPE_MASK 0x0000000F
#define IXGBE_RXDADV_PKTTYPE_MASK 0x0000FFF0
#define IXGBE_RXDADV_PKTTYPE_MASK_EX 0x0001FFF0
#define IXGBE_RXDADV_HDRBUFLEN_MASK 0x00007FE0
#define IXGBE_RXDADV_RSCCNT_MASK 0x001E0000
#define IXGBE_RXDADV_RSCCNT_SHIFT 17
#define IXGBE_RXDADV_HDRBUFLEN_SHIFT 5
#define IXGBE_RXDADV_SPLITHEADER_EN 0x00001000
#define IXGBE_RXDADV_SPH 0x8000
/* RSS Hash results */
#define IXGBE_RXDADV_RSSTYPE_NONE 0x00000000
#define IXGBE_RXDADV_RSSTYPE_IPV4_TCP 0x00000001
#define IXGBE_RXDADV_RSSTYPE_IPV4 0x00000002
#define IXGBE_RXDADV_RSSTYPE_IPV6_TCP 0x00000003
#define IXGBE_RXDADV_RSSTYPE_IPV6_EX 0x00000004
#define IXGBE_RXDADV_RSSTYPE_IPV6 0x00000005
#define IXGBE_RXDADV_RSSTYPE_IPV6_TCP_EX 0x00000006
#define IXGBE_RXDADV_RSSTYPE_IPV4_UDP 0x00000007
#define IXGBE_RXDADV_RSSTYPE_IPV6_UDP 0x00000008
#define IXGBE_RXDADV_RSSTYPE_IPV6_UDP_EX 0x00000009
/* RSS Packet Types as indicated in the receive descriptor. */
#define IXGBE_RXDADV_PKTTYPE_NONE 0x00000000
/* Security Processing bit Indication */
#define IXGBE_RXDADV_LNKSEC_STATUS_SECP 0x00020000
#define IXGBE_RXDADV_LNKSEC_ERROR_NO_SA_MATCH 0x08000000
#define IXGBE_RXDADV_LNKSEC_ERROR_REPLAY_ERROR 0x10000000
#define IXGBE_RXDADV_LNKSEC_ERROR_BIT_MASK 0x18000000
#define IXGBE_RXDADV_LNKSEC_ERROR_BAD_SIG 0x18000000
/* Masks to determine if packets should be dropped due to frame errors */
#define IXGBE_RXD_ERR_FRAME_ERR_MASK ( \
IXGBE_RXD_ERR_CE | \
IXGBE_RXD_ERR_LE | \
IXGBE_RXD_ERR_PE | \
#define IXGBE_RXDADV_ERR_FRAME_ERR_MASK ( \
/* Multicast bit mask */
#define IXGBE_MCSTCTRL_MFE 0x4
/* Number of Transmit and Receive Descriptors must be a multiple of 8 */
#define IXGBE_REQ_TX_DESCRIPTOR_MULTIPLE 8
#define IXGBE_REQ_RX_DESCRIPTOR_MULTIPLE 8
#define IXGBE_REQ_TX_BUFFER_GRANULARITY 1024
/* Vlan-specific macros */
/* SR-IOV specific macros */
/* Little Endian defines */
#ifndef __le16
#endif
#ifndef __le32
#endif
#ifndef __le64
#endif
#ifndef __be16
/* Big Endian defines */
#endif
enum ixgbe_fdir_pballoc_type {
};
/* Flow Director register values */
#define IXGBE_FDIRCTRL_PBALLOC_64K 0x00000001
#define IXGBE_FDIRCTRL_PBALLOC_128K 0x00000002
#define IXGBE_FDIRCTRL_PBALLOC_256K 0x00000003
#define IXGBE_FDIRCTRL_INIT_DONE 0x00000008
#define IXGBE_FDIRCTRL_PERFECT_MATCH 0x00000010
#define IXGBE_FDIRCTRL_REPORT_STATUS 0x00000020
#define IXGBE_FDIRCTRL_REPORT_STATUS_ALWAYS 0x00000080
#define IXGBE_FDIRCTRL_DROP_Q_SHIFT 8
#define IXGBE_FDIRCTRL_FLEX_SHIFT 16
#define IXGBE_FDIRCTRL_SEARCHLIM 0x00800000
#define IXGBE_FDIRCTRL_MAX_LENGTH_SHIFT 24
#define IXGBE_FDIRCTRL_FULL_THRESH_MASK 0xF0000000
#define IXGBE_FDIRCTRL_FULL_THRESH_SHIFT 28
#define IXGBE_FDIRTCPM_DPORTM_SHIFT 16
#define IXGBE_FDIRUDPM_DPORTM_SHIFT 16
#define IXGBE_FDIRIP6M_DIPM_SHIFT 16
#define IXGBE_FDIRM_VLANID 0x00000001
#define IXGBE_FDIRM_VLANP 0x00000002
#define IXGBE_FDIRM_POOL 0x00000004
#define IXGBE_FDIRM_L4P 0x00000008
#define IXGBE_FDIRM_FLEX 0x00000010
#define IXGBE_FDIRM_DIPv6 0x00000020
#define IXGBE_FDIRFREE_FREE_MASK 0xFFFF
#define IXGBE_FDIRFREE_FREE_SHIFT 0
#define IXGBE_FDIRFREE_COLL_MASK 0x7FFF0000
#define IXGBE_FDIRFREE_COLL_SHIFT 16
#define IXGBE_FDIRLEN_MAXLEN_MASK 0x3F
#define IXGBE_FDIRLEN_MAXLEN_SHIFT 0
#define IXGBE_FDIRLEN_MAXHASH_MASK 0x7FFF0000
#define IXGBE_FDIRLEN_MAXHASH_SHIFT 16
#define IXGBE_FDIRUSTAT_ADD_MASK 0xFFFF
#define IXGBE_FDIRUSTAT_ADD_SHIFT 0
#define IXGBE_FDIRUSTAT_REMOVE_MASK 0xFFFF0000
#define IXGBE_FDIRUSTAT_REMOVE_SHIFT 16
#define IXGBE_FDIRFSTAT_FADD_MASK 0x00FF
#define IXGBE_FDIRFSTAT_FADD_SHIFT 0
#define IXGBE_FDIRFSTAT_FREMOVE_MASK 0xFF00
#define IXGBE_FDIRFSTAT_FREMOVE_SHIFT 8
#define IXGBE_FDIRPORT_DESTINATION_SHIFT 16
#define IXGBE_FDIRVLAN_FLEX_SHIFT 16
#define IXGBE_FDIRHASH_BUCKET_VALID_SHIFT 15
#define IXGBE_FDIRHASH_SIG_SW_INDEX_SHIFT 16
#define IXGBE_FDIRCMD_CMD_MASK 0x00000003
#define IXGBE_FDIRCMD_CMD_ADD_FLOW 0x00000001
#define IXGBE_FDIRCMD_CMD_REMOVE_FLOW 0x00000002
#define IXGBE_FDIRCMD_CMD_QUERY_REM_FILT 0x00000003
#define IXGBE_FDIRCMD_FILTER_VALID 0x00000004
#define IXGBE_FDIRCMD_FILTER_UPDATE 0x00000008
#define IXGBE_FDIRCMD_IPv6DMATCH 0x00000010
#define IXGBE_FDIRCMD_L4TYPE_UDP 0x00000020
#define IXGBE_FDIRCMD_L4TYPE_TCP 0x00000040
#define IXGBE_FDIRCMD_L4TYPE_SCTP 0x00000060
#define IXGBE_FDIRCMD_IPV6 0x00000080
#define IXGBE_FDIRCMD_CLEARHT 0x00000100
#define IXGBE_FDIRCMD_DROP 0x00000200
#define IXGBE_FDIRCMD_INT 0x00000400
#define IXGBE_FDIRCMD_LAST 0x00000800
#define IXGBE_FDIRCMD_COLLISION 0x00001000
#define IXGBE_FDIRCMD_QUEUE_EN 0x00008000
#define IXGBE_FDIRCMD_FLOW_TYPE_SHIFT 5
#define IXGBE_FDIRCMD_RX_QUEUE_SHIFT 16
#define IXGBE_FDIRCMD_VT_POOL_SHIFT 24
#define IXGBE_FDIR_INIT_DONE_POLL 10
#define IXGBE_FDIRCMD_CMD_POLL 10
#define IXGBE_FDIR_DROP_QUEUE 127
/* Manageablility Host Interface defines */
/* CEM Support */
#define FW_CEM_HDR_LEN 0x4
#define FW_CEM_CMD_DRIVER_INFO 0xDD
#define FW_CEM_CMD_DRIVER_INFO_LEN 0x5
#define FW_CEM_CMD_RESERVED 0X0
#define FW_CEM_UNUSED_VER 0x0
#define FW_CEM_MAX_RETRIES 3
#define FW_CEM_RESP_STATUS_SUCCESS 0x1
/* Host Interface Command Structures */
struct ixgbe_hic_hdr {
union {
} cmd_or_resp;
};
struct ixgbe_hic_drv_info {
struct ixgbe_hic_hdr hdr;
};
/* Transmit Descriptor - Legacy */
struct ixgbe_legacy_tx_desc {
union {
struct {
} flags;
} lower;
union {
struct {
} fields;
} upper;
};
/* Transmit Descriptor - Advanced */
union ixgbe_adv_tx_desc {
struct {
} read;
struct {
} wb;
};
/* Receive Descriptor - Legacy */
struct ixgbe_legacy_rx_desc {
};
/* Receive Descriptor - Advanced */
union ixgbe_adv_rx_desc {
struct {
} read;
struct {
struct {
union {
struct {
} hs_rss;
} lo_dword;
union {
struct {
} csum_ip;
} hi_dword;
} lower;
struct {
} upper;
} wb; /* writeback */
};
/* Context descriptors */
struct ixgbe_adv_tx_context_desc {
};
/* Adv Transmit Descriptor Config Masks */
#define IXGBE_ADVTXD_POPTS_IXSM (IXGBE_TXD_POPTS_IXSM << \
#define IXGBE_ADVTXD_POPTS_TXSM (IXGBE_TXD_POPTS_TXSM << \
/* 1st&Last TSO-full iSCSI PDU */
#define IXGBE_ADVTXD_POPTS_ISCO_FULL 0x00001800
/* Autonegotiation advertised speeds */
typedef u32 ixgbe_autoneg_advertised;
/* Link speed */
typedef u32 ixgbe_link_speed;
#define IXGBE_LINK_SPEED_UNKNOWN 0
#define IXGBE_LINK_SPEED_100_FULL 0x0008
#define IXGBE_LINK_SPEED_1GB_FULL 0x0020
#define IXGBE_LINK_SPEED_10GB_FULL 0x0080
#define IXGBE_LINK_SPEED_82598_AUTONEG (IXGBE_LINK_SPEED_1GB_FULL | \
#define IXGBE_LINK_SPEED_82599_AUTONEG (IXGBE_LINK_SPEED_100_FULL | \
/* Physical layer type */
typedef u32 ixgbe_physical_layer;
#define IXGBE_PHYSICAL_LAYER_UNKNOWN 0
#define IXGBE_PHYSICAL_LAYER_10GBASE_T 0x0001
#define IXGBE_PHYSICAL_LAYER_1000BASE_T 0x0002
#define IXGBE_PHYSICAL_LAYER_100BASE_TX 0x0004
#define IXGBE_PHYSICAL_LAYER_SFP_PLUS_CU 0x0008
#define IXGBE_PHYSICAL_LAYER_10GBASE_LR 0x0010
#define IXGBE_PHYSICAL_LAYER_10GBASE_LRM 0x0020
#define IXGBE_PHYSICAL_LAYER_10GBASE_SR 0x0040
#define IXGBE_PHYSICAL_LAYER_10GBASE_KX4 0x0080
#define IXGBE_PHYSICAL_LAYER_10GBASE_CX4 0x0100
#define IXGBE_PHYSICAL_LAYER_1000BASE_KX 0x0200
#define IXGBE_PHYSICAL_LAYER_1000BASE_BX 0x0400
#define IXGBE_PHYSICAL_LAYER_10GBASE_KR 0x0800
#define IXGBE_PHYSICAL_LAYER_10GBASE_XAUI 0x1000
#define IXGBE_PHYSICAL_LAYER_SFP_ACTIVE_DA 0x2000
#define IXGBE_PHYSICAL_LAYER_1000BASE_SX 0x4000
/* Flow Control Data Sheet defined values
* Calculation and defines taken from 802.1bb Annex O
*/
/* BitTimes (BT) conversion */
/* Calculate Delay to respond to PFC */
#define IXGBE_PFC_D 672
/* Calculate Cable Delay */
/* Calculate Interface Delay X540 */
/* Calculate Interface Delay 82598, 82599 */
#define IXGBE_PHY_D 12800
#define IXGBE_MAC_D 4096
/* Calculate Delay incurred from higher layer */
#define IXGBE_HD 6144
/* Calculate PCI Bus delay for low thresholds */
#define IXGBE_PCI_DELAY 10000
/* Calculate X540 delay value in bit times */
((36 * \
(IXGBE_B2BT(_max_frame_link) + \
IXGBE_PFC_D + \
(2 * IXGBE_CABLE_DC) + \
(2 * IXGBE_ID_X540) + \
/* Calculate 82599, 82598 delay value in bit times */
((36 * \
(IXGBE_B2BT(_max_frame_link) + \
IXGBE_PFC_D + \
(2 * IXGBE_CABLE_DC) + \
(2 * IXGBE_ID) + \
/* Calculate low threshold delay values */
#define IXGBE_LOW_DV_X540(_max_frame_tc) \
#define IXGBE_LOW_DV(_max_frame_tc) \
/* Software ATR hash keys */
#define IXGBE_ATR_BUCKET_HASH_KEY 0x3DAD14E2
#define IXGBE_ATR_SIGNATURE_HASH_KEY 0x174D3614
/* Software ATR input stream values and masks */
#define IXGBE_ATR_HASH_MASK 0x7fff
#define IXGBE_ATR_L4TYPE_MASK 0x3
#define IXGBE_ATR_L4TYPE_UDP 0x1
#define IXGBE_ATR_L4TYPE_TCP 0x2
#define IXGBE_ATR_L4TYPE_SCTP 0x3
#define IXGBE_ATR_L4TYPE_IPV6_MASK 0x4
enum ixgbe_atr_flow_type {
IXGBE_ATR_FLOW_TYPE_IPV4 = 0x0,
IXGBE_ATR_FLOW_TYPE_UDPV4 = 0x1,
IXGBE_ATR_FLOW_TYPE_TCPV4 = 0x2,
IXGBE_ATR_FLOW_TYPE_SCTPV4 = 0x3,
IXGBE_ATR_FLOW_TYPE_IPV6 = 0x4,
IXGBE_ATR_FLOW_TYPE_UDPV6 = 0x5,
IXGBE_ATR_FLOW_TYPE_TCPV6 = 0x6,
IXGBE_ATR_FLOW_TYPE_SCTPV6 = 0x7,
};
/* Flow Director ATR input struct. */
union ixgbe_atr_input {
/*
* Byte layout in order, all values with MSB first:
*
* vm_pool - 1 byte
* flow_type - 1 byte
* vlan_id - 2 bytes
* src_ip - 16 bytes
* dst_ip - 16 bytes
* src_port - 2 bytes
* dst_port - 2 bytes
* flex_bytes - 2 bytes
* bkt_hash - 2 bytes
*/
struct {
} formatted;
};
/* Flow Director compressed ATR hash input struct */
union ixgbe_atr_hash_dword {
struct {
} formatted;
struct {
} port;
};
/*
* Unavailable: The FCoE Boot Option ROM is not present in the flash.
* Disabled: Present; boot order is not set for any targets on the port.
* Enabled: Present; boot order is set for at least one target on the port.
*/
enum ixgbe_fcoe_boot_status {
ixgbe_fcoe_bootstatus_unavailable = 0xFFFF
};
enum ixgbe_eeprom_type {
ixgbe_eeprom_none /* No NVM support */
};
enum ixgbe_mac_type {
ixgbe_mac_unknown = 0,
};
enum ixgbe_phy_type {
ixgbe_phy_unknown = 0,
ixgbe_phy_sfp_unsupported, /*Enforce bit set with unsupported module*/
};
/*
* SFP+ module type IDs:
*
* ID Module Type
* =============
* 0 SFP_DA_CU
* 1 SFP_SR
* 2 SFP_LR
* 3 SFP_DA_CU_CORE0 - 82599-specific
* 4 SFP_DA_CU_CORE1 - 82599-specific
*/
enum ixgbe_sfp_type {
ixgbe_sfp_type_da_cu = 0,
ixgbe_sfp_type_sr = 1,
ixgbe_sfp_type_lr = 2,
ixgbe_sfp_type_not_present = 0xFFFE,
ixgbe_sfp_type_unknown = 0xFFFF
};
enum ixgbe_media_type {
};
/* Flow Control Settings */
enum ixgbe_fc_mode {
ixgbe_fc_none = 0,
};
/* Smart Speed Settings */
#define IXGBE_SMARTSPEED_MAX_RETRIES 3
enum ixgbe_smart_speed {
};
/* PCI bus types */
enum ixgbe_bus_type {
};
/* PCI bus speeds */
enum ixgbe_bus_speed {
ixgbe_bus_speed_33 = 33,
ixgbe_bus_speed_66 = 66,
ixgbe_bus_speed_100 = 100,
ixgbe_bus_speed_120 = 120,
ixgbe_bus_speed_133 = 133,
ixgbe_bus_speed_2500 = 2500,
ixgbe_bus_speed_5000 = 5000,
ixgbe_bus_speed_8000 = 8000,
};
/* PCI bus widths */
enum ixgbe_bus_width {
ixgbe_bus_width_32 = 32,
ixgbe_bus_width_64 = 64,
};
struct ixgbe_addr_filter_info {
bool user_set_promisc;
};
/* Bus parameters */
struct ixgbe_bus_info {
enum ixgbe_bus_speed speed;
enum ixgbe_bus_width width;
enum ixgbe_bus_type type;
};
/* Flow control parameters */
struct ixgbe_fc_info {
bool send_xon; /* Flow control send XON */
bool strict_ieee; /* Strict IEEE mode */
bool disable_fc_autoneg; /* Do not autonegotiate FC */
bool fc_was_autonegged; /* Is current_mode the result of autonegging? */
};
/* Statistics counters collected by the MAC */
struct ixgbe_hw_stats {
};
/* forward declaration */
struct ixgbe_hw;
/* iterator type for walking multicast address lists */
/* Function pointer table */
struct ixgbe_eeprom_operations {
};
struct ixgbe_mac_operations {
void (*enable_relaxed_ordering)(struct ixgbe_hw *);
void (*set_lan_id)(struct ixgbe_hw *);
/* Link */
void (*disable_tx_laser)(struct ixgbe_hw *);
void (*enable_tx_laser)(struct ixgbe_hw *);
void (*flap_tx_laser)(struct ixgbe_hw *);
bool *);
/* Packet Buffer manipulation */
/* LED */
/* RAR, Multicast, VLAN */
ixgbe_mc_addr_itr, bool clear);
void (*set_mac_anti_spoofing)(struct ixgbe_hw *, bool, int);
void (*set_vlan_anti_spoofing)(struct ixgbe_hw *, bool, int);
/* Flow Control */
/* Manageability interface */
};
struct ixgbe_phy_operations {
bool);
void (*i2c_bus_clear)(struct ixgbe_hw *);
};
struct ixgbe_eeprom_info {
struct ixgbe_eeprom_operations ops;
enum ixgbe_eeprom_type type;
};
#define IXGBE_FLAGS_DOUBLE_RESET_REQUIRED 0x01
struct ixgbe_mac_info {
struct ixgbe_mac_operations ops;
enum ixgbe_mac_type type;
/* prefix for World Wide Node Name (WWNN) */
/* prefix for World Wide Port Name (WWPN) */
#define IXGBE_MAX_MTA 128
bool arc_subsystem_valid;
bool autotry_restart;
};
struct ixgbe_phy_info {
struct ixgbe_phy_operations ops;
enum ixgbe_phy_type type;
enum ixgbe_sfp_type sfp_type;
bool sfp_setup_needed;
enum ixgbe_media_type media_type;
bool reset_disable;
enum ixgbe_smart_speed smart_speed;
bool smart_speed_active;
bool multispeed_fiber;
bool reset_if_overtemp;
};
#include "ixgbe_mbx.h"
struct ixgbe_mbx_operations {
};
struct ixgbe_mbx_stats {
};
struct ixgbe_mbx_info {
struct ixgbe_mbx_operations ops;
struct ixgbe_mbx_stats stats;
};
struct ixgbe_hw {
void *back;
struct ixgbe_mac_info mac;
struct ixgbe_addr_filter_info addr_ctrl;
struct ixgbe_fc_info fc;
struct ixgbe_phy_info phy;
struct ixgbe_eeprom_info eeprom;
struct ixgbe_bus_info bus;
struct ixgbe_mbx_info mbx;
bool adapter_stopped;
bool force_full_reset;
bool allow_unsupported_sfp;
};
/* Error Codes */
#define IXGBE_SUCCESS 0
#define IXGBE_ERR_EEPROM -1
#define IXGBE_ERR_EEPROM_CHECKSUM -2
#define IXGBE_ERR_PHY -3
#define IXGBE_ERR_CONFIG -4
#define IXGBE_ERR_PARAM -5
#define IXGBE_ERR_MAC_TYPE -6
#define IXGBE_ERR_UNKNOWN_PHY -7
#define IXGBE_ERR_LINK_SETUP -8
#define IXGBE_ERR_ADAPTER_STOPPED -9
#define IXGBE_ERR_INVALID_MAC_ADDR -10
#define IXGBE_ERR_DEVICE_NOT_SUPPORTED -11
#define IXGBE_ERR_MASTER_REQUESTS_PENDING -12
#define IXGBE_ERR_INVALID_LINK_SETTINGS -13
#define IXGBE_ERR_AUTONEG_NOT_COMPLETE -14
#define IXGBE_ERR_RESET_FAILED -15
#define IXGBE_ERR_SWFW_SYNC -16
#define IXGBE_ERR_PHY_ADDR_INVALID -17
#define IXGBE_ERR_I2C -18
#define IXGBE_ERR_SFP_NOT_SUPPORTED -19
#define IXGBE_ERR_SFP_NOT_PRESENT -20
#define IXGBE_ERR_SFP_NO_INIT_SEQ_PRESENT -21
#define IXGBE_ERR_NO_SAN_ADDR_PTR -22
#define IXGBE_ERR_FDIR_REINIT_FAILED -23
#define IXGBE_ERR_EEPROM_VERSION -24
#define IXGBE_ERR_NO_SPACE -25
#define IXGBE_ERR_OVERTEMP -26
#define IXGBE_ERR_FC_NOT_NEGOTIATED -27
#define IXGBE_ERR_FC_NOT_SUPPORTED -28
#define IXGBE_ERR_SFP_SETUP_NOT_COMPLETE -30
#define IXGBE_ERR_PBA_SECTION -31
#define IXGBE_ERR_INVALID_ARGUMENT -32
#define IXGBE_ERR_HOST_INTERFACE_COMMAND -33
#define IXGBE_ERR_OUT_OF_MEM -34
#define IXGBE_NOT_IMPLEMENTED 0x7FFFFFFF
#endif /* _IXGBE_TYPE_H_ */