ixgbe_type.h revision 19843f01b1bef3453f717c23c8f89fb9313f6749
1N/A * Copyright(c) 2007-2010 Intel Corporation. All rights reserved. 1N/A * The contents of this file are subject to the terms of the 1N/A * Common Development and Distribution License (the "License"). 1N/A * You may not use this file except in compliance with the License. 1N/A * You can obtain a copy of the license at: 1N/A * See the License for the specific language governing permissions 1N/A * and limitations under the License. 1N/A * When using or redistributing this file, you may do so under the 1N/A * License only. No other modification of this header is permitted. 1N/A * If applicable, add the following below this CDDL HEADER, with the 1N/A * fields enclosed by brackets "[]" replaced with your own identifying 1N/A * information: Portions Copyright [yyyy] [name of copyright owner] 1N/A * Copyright 2010 Sun Microsystems, Inc. All rights reserved. 1N/A * Use is subject to license terms. 1N/A/* IntelVersion: 1.375.4.1 sol_ixgbe_shared_339b */ 1N/A/* General Registers */ 1N/A/* General Receive Control */ 1N/A/* I2CCTL Bit Masks */ 1N/A/* Interrupt Registers */ 1N/A/* 82599 EITR is only 12 bits, with the lower 3 always zero */ 1N/A * 82598 EITR is 16 bits but set the limits based on the max 1N/A * supported by all ixgbe hardware 1N/A (
0x00820 + ((
_i) *
4)) : (
0x012300 + (((
_i) -
24) *
4)))
1N/A/* Flow Control Registers */ 1N/A/* Receive DMA Registers */ 1N/A (
0x01000 + ((
_i) *
0x40)) : (
0x0D000 + ((
_i -
64) *
0x40)))
1N/A (
0x01004 + ((
_i) *
0x40)) : (
0x0D004 + ((
_i -
64) *
0x40)))
1N/A (
0x01008 + ((
_i) *
0x40)) : (
0x0D008 + ((
_i -
64) *
0x40)))
1N/A (
0x01010 + ((
_i) *
0x40)) : (
0x0D010 + ((
_i -
64) *
0x40)))
1N/A (
0x01018 + ((
_i) *
0x40)) : (
0x0D018 + ((
_i -
64) *
0x40)))
1N/A (
0x01028 + ((
_i) *
0x40)) : (
0x0D028 + ((
_i -
64) *
0x40)))
1N/A (
0x0102C + ((
_i) *
0x40)) : (
0x0D02C + ((
_i -
64) *
0x40)))
1N/A * Split and Replication Receive Control Registers 1N/A * 00-15 : 0x02100 + n*4 1N/A * 16-64 : 0x01014 + n*0x40 1N/A * 64-127: 0x0D014 + (n-64)*0x40 1N/A (((
_i) <
64) ? (
0x01014 + ((
_i) *
0x40)) : \
1N/A (
0x0D014 + ((
_i -
64) *
0x40))))
1N/A * Rx DCA Control Register: 1N/A * 00-15 : 0x02200 + n*4 1N/A * 16-64 : 0x0100C + n*0x40 1N/A * 64-127: 0x0D00C + (n-64)*0x40 1N/A (((
_i) <
64) ? (
0x0100C + ((
_i) *
0x40)) : \
1N/A (
0x0D00C + ((
_i -
64) *
0x40))))
1N/A/* 8 of these 0x03C00 - 0x03C1C */ 1N/A/* Receive Registers */ 1N/A/* Multicast Table Array - 128 entries */ 1N/A (
0x05400 + ((
_i) *
8)) : (
0x0A200 + ((
_i) *
8)))
1N/A (
0x05404 + ((
_i) *
8)) : (
0x0A204 + ((
_i) *
8)))
1N/A/* Packet split receive type */ 1N/A (
0x05480 + ((
_i) *
4)) : (
0x0EA00 + ((
_i) *
4)))
1N/A/* array of 4096 1-bit vlan filters */ 1N/A/* array of 4096 4-bit vlan vmdq indices */ 1N/A /* 128 of these (0-127) */ 1N/A/* Flow Director registers */ 1N/A/* Flow Director Stats registers */ 1N/A/* Flow Director Programming registers */ 1N/A/* Transmit DMA registers */ /* Tx DCA Control register : 128 of these (0-127) */ #
define IXGBE_IP4AT 0x05840 /* IPv4 table 0x5840-0x5858 */#
define IXGBE_IP6AT 0x05880 /* IPv6 table 0x5880-0x588F */#
define IXGBE_WUPM 0x05A00 /* wake up pkt memory 0x5A00-0x5A7C */#
define IXGBE_FHFT(
_n) (
0x09000 + (
_n *
0x100))
/* Flex host filter table *//* Ext Flexible Host Filter Table */ /* Each Flexible Filter is at most 128 (0x80) bytes in length */ /* Definitions for power management and wakeup registers */ /* Wake Up Filter Control */ #
define IXGBE_WUFC_EX 0x00000004 /* Directed Exact Wakeup Enable */#
define IXGBE_WUFC_MC 0x00000008 /* Directed Multicast Wakeup Enable */#
define IXGBE_WUFC_ARP 0x00000020 /* ARP Request Packet Wakeup Enable */#
define IXGBE_WUFC_IPV4 0x00000040 /* Directed IPv4 Packet Wakeup Enable */#
define IXGBE_WUFC_IPV6 0x00000080 /* Directed IPv6 Packet Wakeup Enable */#
define IXGBE_WUFC_MNG 0x00000100 /* Directed Mgmt Packet Wakeup Enable *//* Wake Up Packet Length */ /* Security Control Registers */ /* Security Bit Fields and Masks */ /* LinkSec (MacSec) Registers */ /* LinkSec (MacSec) Bit Fields and Masks */ /* FCoE DMA Context Registers */ #
define IXGBE_FCINVST0 0x03FC0 /* FC Invalid DMA Context Status Reg 0 *//* FCoE Filter Context Registers */ /* FCoE Receive Control */ #
define IXGBE_MPC(
_i) (
0x03FA0 + ((
_i) *
4))
/* 8 of these 3FA0-3FBC */#
define IXGBE_RNBC(
_i) (
0x03FC0 + ((
_i) *
4))
/* 8 of these 3FC0-3FDC */ (
0x07300 + ((
_i) *
4)) : (
0x08600 + ((
_i) *
4)))
#
define IXGBE_FCCRC 0x05118 /* Count of Good Eth CRC w/ Bad FC CRC */#
define IXGBE_FCOEPRC 0x02428 /* Number of FCoE Packets Received */#
define IXGBE_FCOEPTC 0x08784 /* Number of FCoE Packets Transmitted */#
define IXGBE_FCOEDWTC 0x08788 /* Number of FCoE DWords Transmitted *//* ARC Subsystem registers */ /* PCI-E registers 82599-Specific */ /* PCI Express Control */ /* Time Sync Registers */ #
define IXGBE_RXSATRL 0x051A0 /* Rx timestamp attribute low - RO */#
define IXGBE_RXSATRH 0x051A8 /* Rx timestamp attribute high - RO */#
define IXGBE_RXMTRL 0x05120 /* RX message type register low - RW */#
define IXGBE_SYSTIML 0x08C0C /* System time register Low - RO */#
define IXGBE_SYSTIMH 0x08C10 /* System time register High - RO */#
define IXGBE_TIMINCA 0x08C14 /* Increment attributes register - RW */#
define IXGBE_RXUDP 0x08C1C /* Time Sync Rx UDP Port - RW *//* Diagnostic Registers */ /* Copper Pond 2 link timeout */ /* RQTC Bit Masks and Shifts */ /* PSRTYPE.RQPL Bit masks and shift */ /* Extended Device Control */ /* Direct Cache Access (DCA) definitions */ /* MDI Address (new protocol) */ /* Device Type (new protocol) */ /* OP CODE 11 (read, auto inc) */ /* ST CODE 00 (new protocol) */ /* ST CODE 01 (old protocol) */ /* Device Type definitions for new protocol MDIO commands */ /* MII clause 22/28 definitions */ /* Special PHY Init Routine */ /* General purpose Interrupt Enable */ /* Transmit Flow Control status */ /* RDHMPN and TDHMPN bitmasks */ /* Receive Checksum Control */ /* Receive Arbitration Control: 0 Round Robin, 1 DFP */ /* Interrupt register bitmasks */ /* Extended Interrupt Cause Read */ /* Extended Interrupt Cause Set */ /* Extended Interrupt Mask Set */ /* Extended Interrupt Mask Clear */ /* Immediate Interrupt Rx (A.K.A. Low Latency Interrupt) */ /* Interrupt clear mask */ /* Interrupt Vector Allocation Registers */ * ETQF filter list: one static filter per filter consumer. This is * to avoid filter collisions later. Add new filters * EAPOL 802.1x (0x888e): Filter 0 * FCoE (0x8906): Filter 2 * 1588 (0x88f7): Filter 3 /* VLAN Control Bit Masks */ /* VLAN pool filtering masks */ /* PCS1GLSTA Bit Masks */ /* PCS1GLCTL Bit Masks */ /* SW Semaphore Register bitmasks */ /* EEPROM Addressing bits based on type (0-small, 1-large) */ /* Checksum and EEPROM pointers */ /* MSI-X capability fields masks */ /* Legacy EEPROM word offsets */ /* EEPROM Commands - SPI */ /* EEPROM reset Write Enable latch */ /* EEPROM Read Register */ * Number of 5 microseconds we wait for EERD read and /* # attempts we wait for flush update to complete */ /* Number of 100 microseconds we wait for PCI Express master disable */ /* Check whether address is multicast. This is little-endian specific check. */ /* Check whether an address is broadcast. */ /* Header split receive */ /* Transmit Config masks */ /* Enable short packet padding to 64 bytes */ /* This allows for 16K packets + 4k for vlan */ /* Receive Config masks */ /* Receive Priority Flow Control Enable */ /* Multiple Receive Queue Control */ /* Descriptor extension (0 = legacy) */ /* Multiple Transmit Queue Command Register */ /* Receive Descriptor bit definitions */ /* PSRTYPE bit definitions */ /* SRRCTL bit definitions */ /* RSS Packet Types as indicated in the receive descriptor. */ /* Security Processing bit Indication */ /* Masks to determine if packets should be dropped due to frame errors */ /* Number of Transmit and Receive Descriptors must be a multiple of 8 */ /* Vlan-specific macros */ /* SR-IOV specific macros */ /* Little Endian defines */ /* Flow Director register values */ /* Transmit Descriptor - Legacy */ u8 cso;
/* Checksum offset */ u8 cmd;
/* Descriptor control */ u8 css;
/* Checksum start */ /* Transmit Descriptor - Advanced */ /* Receive Descriptor - Legacy */ /* Receive Descriptor - Advanced */ /* RSS type, Packet type */ /* Split Header, header len */ /* Context descriptors */ /* Adv Transmit Descriptor Config Masks */ /* 1st&Last TSO-full iSCSI PDU */ /* Autonegotiation advertised speeds */ /* Physical layer type */ /* Software ATR hash keys */ /* Software ATR input stream offsets and masks */ /* Flow Director ATR input struct. */ * Byte layout in order, all values with MSB first: * 3 SFP_DA_CU_CORE0 - 82599-specific * 4 SFP_DA_CU_CORE1 - 82599-specific /* Flow Control Settings */ /* Smart Speed Settings */ /* Flow control parameters */ bool send_xon;
/* Flow control send XON */ /* Statistics counters collected by the MAC */ /* forward declaration */ /* iterator type for walking multicast address lists */ /* Function pointer table */ /* RAR, Multicast, VLAN */ /* prefix for World Wide Node Name (WWNN) */ /* prefix for World Wide Port Name (WWPN) */ #
endif /* _IXGBE_TYPE_H */