ixgbe_sw.h revision f27d3025d908422c3f6e682964b4f1e2b4834e4a
9da57d7b0ddd8d73b676ce12c040362132cdd538bt * CDDL HEADER START
9da57d7b0ddd8d73b676ce12c040362132cdd538bt * Copyright(c) 2007-2008 Intel Corporation. All rights reserved.
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9da57d7b0ddd8d73b676ce12c040362132cdd538bt * You may not use this file except in compliance with the License.
9da57d7b0ddd8d73b676ce12c040362132cdd538bt * You can obtain a copy of the license at:
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9da57d7b0ddd8d73b676ce12c040362132cdd538bt * and limitations under the License.
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9da57d7b0ddd8d73b676ce12c040362132cdd538bt * Copyright 2008 Sun Microsystems, Inc. All rights reserved.
9da57d7b0ddd8d73b676ce12c040362132cdd538bt * Use is subject to license terms of the CDDL.
9da57d7b0ddd8d73b676ce12c040362132cdd538bt#pragma ident "%Z%%M% %I% %E% SMI"
9da57d7b0ddd8d73b676ce12c040362132cdd538btextern "C" {
9da57d7b0ddd8d73b676ce12c040362132cdd538bt * Maximum values for user configurable parameters
9da57d7b0ddd8d73b676ce12c040362132cdd538bt * MAX_xx_QUEUE_NUM values need to be the maximum of all supported
9da57d7b0ddd8d73b676ce12c040362132cdd538bt * silicon types.
9da57d7b0ddd8d73b676ce12c040362132cdd538bt * Minimum values for user configurable parameters
9da57d7b0ddd8d73b676ce12c040362132cdd538bt * Default values for user configurable parameters
9da57d7b0ddd8d73b676ce12c040362132cdd538bt#define DEFAULT_INTR_THROTTLING 200 /* In unit of 256 nsec */
9da57d7b0ddd8d73b676ce12c040362132cdd538bt * limits on msi-x vectors for 82598
9da57d7b0ddd8d73b676ce12c040362132cdd538bt#define IXGBE_MAX_RING_VECTOR (IXGBE_MAX_INTR_VECTOR - IXGBE_MAX_OTHER_VECTOR)
9da57d7b0ddd8d73b676ce12c040362132cdd538bt * Extra register bit masks for 82598
9da57d7b0ddd8d73b676ce12c040362132cdd538bt * Defined for IP header alignment.
9da57d7b0ddd8d73b676ce12c040362132cdd538bt * Bit flags for attach_progress
9da57d7b0ddd8d73b676ce12c040362132cdd538bt#define ATTACH_PROGRESS_PCI_CONFIG 0x0001 /* PCI config setup */
9da57d7b0ddd8d73b676ce12c040362132cdd538bt#define ATTACH_PROGRESS_REGS_MAP 0x0002 /* Registers mapped */
9da57d7b0ddd8d73b676ce12c040362132cdd538bt#define ATTACH_PROGRESS_PROPS 0x0004 /* Properties initialized */
9da57d7b0ddd8d73b676ce12c040362132cdd538bt#define ATTACH_PROGRESS_ALLOC_INTR 0x0008 /* Interrupts allocated */
9da57d7b0ddd8d73b676ce12c040362132cdd538bt#define ATTACH_PROGRESS_ALLOC_RINGS 0x0010 /* Rings allocated */
9da57d7b0ddd8d73b676ce12c040362132cdd538bt#define ATTACH_PROGRESS_ADD_INTR 0x0020 /* Intr handlers added */
9da57d7b0ddd8d73b676ce12c040362132cdd538bt#define ATTACH_PROGRESS_LOCKS 0x0040 /* Locks initialized */
9da57d7b0ddd8d73b676ce12c040362132cdd538bt#define ATTACH_PROGRESS_INIT 0x0080 /* Device initialized */
9da57d7b0ddd8d73b676ce12c040362132cdd538bt#define ATTACH_PROGRESS_INIT_RINGS 0x0100 /* Rings initialized */
9da57d7b0ddd8d73b676ce12c040362132cdd538bt#define ATTACH_PROGRESS_ENABLE_INTR 0x1000 /* DDI interrupts enabled */
9da57d7b0ddd8d73b676ce12c040362132cdd538bt#define ATTACH_PROGRESS_FM_INIT 0x2000 /* FMA initialized */
9da57d7b0ddd8d73b676ce12c040362132cdd538bt#define PROP_TX_OVERLOAD_THRESHOLD "tx_overload_threshold"
9da57d7b0ddd8d73b676ce12c040362132cdd538bt * Shorthand for the NDD parameters
9da57d7b0ddd8d73b676ce12c040362132cdd538bt#define param_autoneg_cap nd_params[PARAM_AUTONEG_CAP].val
9da57d7b0ddd8d73b676ce12c040362132cdd538bt#define param_asym_pause_cap nd_params[PARAM_ASYM_PAUSE_CAP].val
9da57d7b0ddd8d73b676ce12c040362132cdd538bt#define param_10000fdx_cap nd_params[PARAM_10000FDX_CAP].val
9da57d7b0ddd8d73b676ce12c040362132cdd538bt#define param_1000fdx_cap nd_params[PARAM_1000FDX_CAP].val
9da57d7b0ddd8d73b676ce12c040362132cdd538bt#define param_adv_autoneg_cap nd_params[PARAM_ADV_AUTONEG_CAP].val
9da57d7b0ddd8d73b676ce12c040362132cdd538bt#define param_adv_pause_cap nd_params[PARAM_ADV_PAUSE_CAP].val
9da57d7b0ddd8d73b676ce12c040362132cdd538bt#define param_adv_asym_pause_cap nd_params[PARAM_ADV_ASYM_PAUSE_CAP].val
9da57d7b0ddd8d73b676ce12c040362132cdd538bt#define param_adv_10000fdx_cap nd_params[PARAM_ADV_10000FDX_CAP].val
9da57d7b0ddd8d73b676ce12c040362132cdd538bt#define param_adv_1000fdx_cap nd_params[PARAM_ADV_1000FDX_CAP].val
9da57d7b0ddd8d73b676ce12c040362132cdd538bt#define param_adv_100fdx_cap nd_params[PARAM_ADV_1000FDX_CAP].val
9da57d7b0ddd8d73b676ce12c040362132cdd538bt#define param_adv_rem_fault nd_params[PARAM_ADV_REM_FAULT].val
9da57d7b0ddd8d73b676ce12c040362132cdd538bt#define param_lp_autoneg_cap nd_params[PARAM_LP_AUTONEG_CAP].val
9da57d7b0ddd8d73b676ce12c040362132cdd538bt#define param_lp_pause_cap nd_params[PARAM_LP_PAUSE_CAP].val
9da57d7b0ddd8d73b676ce12c040362132cdd538bt#define param_lp_asym_pause_cap nd_params[PARAM_LP_ASYM_PAUSE_CAP].val
9da57d7b0ddd8d73b676ce12c040362132cdd538bt#define param_lp_10000fdx_cap nd_params[PARAM_LP_10000FDX_CAP].val
9da57d7b0ddd8d73b676ce12c040362132cdd538bt#define param_lp_1000fdx_cap nd_params[PARAM_LP_1000FDX_CAP].val
9da57d7b0ddd8d73b676ce12c040362132cdd538bt#define param_lp_100fdx_cap nd_params[PARAM_LP_1000FDX_CAP].val
9da57d7b0ddd8d73b676ce12c040362132cdd538bt#define param_lp_rem_fault nd_params[PARAM_LP_REM_FAULT].val
9da57d7b0ddd8d73b676ce12c040362132cdd538bt#define DMA_SYNC(area, flag) ((void) ddi_dma_sync((area)->dma_handle, \
9da57d7b0ddd8d73b676ce12c040362132cdd538bt * Defined for ring index operations
9da57d7b0ddd8d73b676ce12c040362132cdd538bt * ASSERT(index < limit)
9da57d7b0ddd8d73b676ce12c040362132cdd538bt * ASSERT(step < limit)
9da57d7b0ddd8d73b676ce12c040362132cdd538bt * ASSERT(index1 < limit)
9da57d7b0ddd8d73b676ce12c040362132cdd538bt * ASSERT(index2 < limit)
9da57d7b0ddd8d73b676ce12c040362132cdd538bt#define NEXT_INDEX(index, step, limit) (((index) + (step)) < (limit) ? \
9da57d7b0ddd8d73b676ce12c040362132cdd538bt#define PREV_INDEX(index, step, limit) ((index) >= (step) ? \
9da57d7b0ddd8d73b676ce12c040362132cdd538bt#define OFFSET(index1, index2, limit) ((index1) <= (index2) ? \
9da57d7b0ddd8d73b676ce12c040362132cdd538bt#define LIST_GET_HEAD(_LH) ((single_link_t *)((_LH)->head))
9da57d7b0ddd8d73b676ce12c040362132cdd538bt#define LIST_GET_TAIL(_LH) ((single_link_t *)((_LH)->tail))
9da57d7b0ddd8d73b676ce12c040362132cdd538bt } else { \
9da57d7b0ddd8d73b676ce12c040362132cdd538bttypedef struct single_link {
9da57d7b0ddd8d73b676ce12c040362132cdd538bttypedef struct link_list {
9da57d7b0ddd8d73b676ce12c040362132cdd538bt * Property lookups
9da57d7b0ddd8d73b676ce12c040362132cdd538bt#define IXGBE_PROP_EXISTS(d, n) ddi_prop_exists(DDI_DEV_T_ANY, (d), \
9da57d7b0ddd8d73b676ce12c040362132cdd538bt#define IXGBE_PROP_GET_INT(d, n) ddi_prop_get_int(DDI_DEV_T_ANY, (d), \
9da57d7b0ddd8d73b676ce12c040362132cdd538bt * Named Data (ND) Parameter Management Structure
9da57d7b0ddd8d73b676ce12c040362132cdd538bttypedef struct {
9da57d7b0ddd8d73b676ce12c040362132cdd538bt * NDD parameter indexes, divided into:
9da57d7b0ddd8d73b676ce12c040362132cdd538bt * read-only parameters describing the hardware's capabilities
9da57d7b0ddd8d73b676ce12c040362132cdd538bt * read-write parameters controlling the advertised capabilities
9da57d7b0ddd8d73b676ce12c040362132cdd538bt * read-only parameters describing the partner's capabilities
9da57d7b0ddd8d73b676ce12c040362132cdd538bt * read-write parameters controlling the force speed and duplex
9da57d7b0ddd8d73b676ce12c040362132cdd538bt * read-only parameters describing the link state
9da57d7b0ddd8d73b676ce12c040362132cdd538bt * read-only parameters describing the driver properties
9da57d7b0ddd8d73b676ce12c040362132cdd538bt * read-write parameters controlling the driver properties
9da57d7b0ddd8d73b676ce12c040362132cdd538bttypedef union ixgbe_ether_addr {
9da57d7b0ddd8d73b676ce12c040362132cdd538bttypedef enum {
9da57d7b0ddd8d73b676ce12c040362132cdd538bttypedef enum {
c971fb7ec0a19c6cd00c5614a94c97f953b6e8b1ggtypedef struct ixgbe_tx_context {
9da57d7b0ddd8d73b676ce12c040362132cdd538bt * Hold address/length of each DMA segment
9da57d7b0ddd8d73b676ce12c040362132cdd538bttypedef struct sw_desc {
9da57d7b0ddd8d73b676ce12c040362132cdd538bt * Handles and addresses of DMA buffer
9da57d7b0ddd8d73b676ce12c040362132cdd538bttypedef struct dma_buffer {
9da57d7b0ddd8d73b676ce12c040362132cdd538bt * Tx Control Block
9da57d7b0ddd8d73b676ce12c040362132cdd538bttypedef struct tx_control_block {
9da57d7b0ddd8d73b676ce12c040362132cdd538bt * RX Control Block
9da57d7b0ddd8d73b676ce12c040362132cdd538bttypedef struct rx_control_block {
9da57d7b0ddd8d73b676ce12c040362132cdd538bt * Software Data Structure for Tx Ring
9da57d7b0ddd8d73b676ce12c040362132cdd538bttypedef struct ixgbe_tx_ring {
9da57d7b0ddd8d73b676ce12c040362132cdd538bt * Tx descriptor ring definitions
9da57d7b0ddd8d73b676ce12c040362132cdd538bt * Tx control block list definitions
c971fb7ec0a19c6cd00c5614a94c97f953b6e8b1gg * s/w context structure for TCP/UDP checksum offload
c971fb7ec0a19c6cd00c5614a94c97f953b6e8b1gg * and LSO.
9da57d7b0ddd8d73b676ce12c040362132cdd538bt * Tx ring settings and status
9da57d7b0ddd8d73b676ce12c040362132cdd538bt * Debug statistics
9da57d7b0ddd8d73b676ce12c040362132cdd538bt * Pointer to the ixgbe struct
9da57d7b0ddd8d73b676ce12c040362132cdd538bt * Software Receive Ring
9da57d7b0ddd8d73b676ce12c040362132cdd538bttypedef struct ixgbe_rx_ring {
9da57d7b0ddd8d73b676ce12c040362132cdd538bt * Rx descriptor ring definitions
9da57d7b0ddd8d73b676ce12c040362132cdd538bt * Rx control block list definitions
9da57d7b0ddd8d73b676ce12c040362132cdd538bt * Rx ring settings and status
9da57d7b0ddd8d73b676ce12c040362132cdd538bt * Debug statistics
9da57d7b0ddd8d73b676ce12c040362132cdd538bt * structure to map ring cleanup to msi-x vector
9da57d7b0ddd8d73b676ce12c040362132cdd538bttypedef struct ixgbe_ring_vector {
9da57d7b0ddd8d73b676ce12c040362132cdd538bt ulong_t rx_map[BT_BITOUL(MAX_RX_QUEUE_NUM)]; /* bitmap of rx rings */
9da57d7b0ddd8d73b676ce12c040362132cdd538bt ulong_t tx_map[BT_BITOUL(MAX_TX_QUEUE_NUM)]; /* bitmap of tx rings */
9da57d7b0ddd8d73b676ce12c040362132cdd538bt * Software adapter state
9da57d7b0ddd8d73b676ce12c040362132cdd538bttypedef struct ixgbe {
9da57d7b0ddd8d73b676ce12c040362132cdd538bt * Each msi-x vector: map vector to ring cleanup
9da57d7b0ddd8d73b676ce12c040362132cdd538bt * Receive Rings
9da57d7b0ddd8d73b676ce12c040362132cdd538bt * Transmit Rings
9da57d7b0ddd8d73b676ce12c040362132cdd538bt uint32_t tx_resched_thresh; /* Tx reschedule threshold */
9da57d7b0ddd8d73b676ce12c040362132cdd538bt ixgbe_ether_addr_t unicst_addr[MAX_NUM_UNICAST_ADDRESSES];
9da57d7b0ddd8d73b676ce12c040362132cdd538bt struct ether_addr mcast_table[MAX_NUM_MULTICAST_ADDRESSES];
9da57d7b0ddd8d73b676ce12c040362132cdd538bt * Kstat definitions
9da57d7b0ddd8d73b676ce12c040362132cdd538bt * NDD definitions
9da57d7b0ddd8d73b676ce12c040362132cdd538bttypedef struct ixgbe_stat {
9da57d7b0ddd8d73b676ce12c040362132cdd538bt kstat_named_t rx_exceed_pkt; /* Rx Exceed Max Pkt Count */
9da57d7b0ddd8d73b676ce12c040362132cdd538bt kstat_named_t tx_fail_no_tcb; /* Tx Fail Freelist Empty */
9da57d7b0ddd8d73b676ce12c040362132cdd538bt kstat_named_t tx_fail_no_tbd; /* Tx Fail Desc Ring Empty */
9da57d7b0ddd8d73b676ce12c040362132cdd538bt kstat_named_t prc1023; /* Packets Received - 511-1023b */
9da57d7b0ddd8d73b676ce12c040362132cdd538bt kstat_named_t prc1522; /* Packets Received - 1024-1522b */
9da57d7b0ddd8d73b676ce12c040362132cdd538bt kstat_named_t mspdc; /* MAC Short Packet Discard Count */
9da57d7b0ddd8d73b676ce12c040362132cdd538bt kstat_named_t lxofftxc; /* Link XOFF Transmitted Count */
9da57d7b0ddd8d73b676ce12c040362132cdd538bt * Function prototypes in ixgbe_buf.c
9da57d7b0ddd8d73b676ce12c040362132cdd538btvoid ixgbe_set_fma_flags(int, int);
9da57d7b0ddd8d73b676ce12c040362132cdd538bt * Function prototypes in ixgbe_main.c
9da57d7b0ddd8d73b676ce12c040362132cdd538btint ixgbe_unicst_set(ixgbe_t *, const uint8_t *, mac_addr_slot_t);
9da57d7b0ddd8d73b676ce12c040362132cdd538btenum ioc_reply ixgbe_loopback_ioctl(ixgbe_t *, struct iocblk *, mblk_t *);
9da57d7b0ddd8d73b676ce12c040362132cdd538bt * Function prototypes in ixgbe_gld.c
9da57d7b0ddd8d73b676ce12c040362132cdd538btvoid ixgbe_m_stop(void *);
9da57d7b0ddd8d73b676ce12c040362132cdd538bt * Function prototypes in ixgbe_rx.c
9da57d7b0ddd8d73b676ce12c040362132cdd538bt * Function prototypes in ixgbe_tx.c
9da57d7b0ddd8d73b676ce12c040362132cdd538btvoid ixgbe_put_free_list(ixgbe_tx_ring_t *, link_list_t *);
9da57d7b0ddd8d73b676ce12c040362132cdd538bt * Function prototypes in ixgbe_log.c
9da57d7b0ddd8d73b676ce12c040362132cdd538btvoid ixgbe_notice(void *, const char *, ...);
9da57d7b0ddd8d73b676ce12c040362132cdd538btvoid ixgbe_log(void *, const char *, ...);
9da57d7b0ddd8d73b676ce12c040362132cdd538btvoid ixgbe_error(void *, const char *, ...);
9da57d7b0ddd8d73b676ce12c040362132cdd538bt * Function prototypes in ixgbe_ndd.c
9da57d7b0ddd8d73b676ce12c040362132cdd538btenum ioc_reply ixgbe_nd_ioctl(ixgbe_t *, queue_t *, mblk_t *, struct iocblk *);
9da57d7b0ddd8d73b676ce12c040362132cdd538bt * Function prototypes in ixgbe_stat.c
9da57d7b0ddd8d73b676ce12c040362132cdd538bt#endif /* _IXGBE_SW_H */