ixgbe_phy.c revision 5b6dd21f5401160f9a62ac2e76a858c2bc105370
/*
* CDDL HEADER START
*
* The contents of this file are subject to the terms of the
* Common Development and Distribution License (the "License").
* You may not use this file except in compliance with the License.
*
* You can obtain a copy of the license at:
* See the License for the specific language governing permissions
* and limitations under the License.
*
* When using or redistributing this file, you may do so under the
* License only. No other modification of this header is permitted.
*
* If applicable, add the following below this CDDL HEADER, with the
* fields enclosed by brackets "[]" replaced with your own identifying
* information: Portions Copyright [yyyy] [name of copyright owner]
*
* CDDL HEADER END
*/
/*
* Copyright(c) 2007-2010 Intel Corporation. All rights reserved.
*/
/*
*/
/* IntelVersion: 1.109 scm_061610_003709 */
#include "ixgbe_api.h"
#include "ixgbe_common.h"
#include "ixgbe_phy.h"
/*
* ixgbe_init_phy_ops_generic - Inits PHY function ptrs
* @hw: pointer to the hardware structure
*
* Initialize the function pointers.
*/
{
DEBUGFUNC("ixgbe_init_phy_ops_generic");
/* PHY */
return (IXGBE_SUCCESS);
}
/*
* ixgbe_identify_phy_generic - Get physical layer module
* @hw: pointer to hardware structure
*
* Determines the physical layer module found on the current adapter.
*/
{
u16 ext_ability = 0;
DEBUGFUNC("ixgbe_identify_phy_generic");
(void) ixgbe_get_phy_id(hw);
&ext_ability);
if (ext_ability &
else
}
break;
}
}
if (status != IXGBE_SUCCESS)
} else {
}
return (status);
}
/*
* ixgbe_validate_phy_addr - Determines phy address is valid
* @hw: pointer to hardware structure
*
*/
bool
{
bool valid = false;
DEBUGFUNC("ixgbe_validate_phy_addr");
valid = true;
return (valid);
}
/*
* ixgbe_get_phy_id - Get the phy type
* @hw: pointer to hardware structure
*
*/
{
u16 phy_id_high = 0;
u16 phy_id_low = 0;
DEBUGFUNC("ixgbe_get_phy_id");
&phy_id_high);
if (status == IXGBE_SUCCESS) {
&phy_id_low);
}
return (status);
}
/*
* ixgbe_get_phy_type_from_id - Get the phy type
* @hw: pointer to hardware structure
*
*/
enum ixgbe_phy_type
{
enum ixgbe_phy_type phy_type;
DEBUGFUNC("ixgbe_get_phy_type_from_id");
switch (phy_id) {
case TN1010_PHY_ID:
break;
case AQ1002_PHY_ID:
break;
case QT2022_PHY_ID:
break;
case ATH_PHY_ID:
break;
default:
break;
}
return (phy_type);
}
/*
* ixgbe_reset_phy_generic - Performs a PHY reset
* @hw: pointer to hardware structure
*/
{
u32 i;
DEBUGFUNC("ixgbe_reset_phy_generic");
goto out;
/* Don't reset PHY if it's shut down due to overtemp. */
goto out;
}
/*
* Perform soft PHY reset to the PHY_XS.
* This will cause a soft reset to the PHY
*/
/*
* Poll for reset bit to self-clear indicating reset is complete.
* Some PHYs could take up to 3 seconds to complete and need about
* 1.7 usec delay after the reset is complete.
*/
for (i = 0; i < 30; i++) {
msec_delay(100);
if (!(ctrl & IXGBE_MDIO_PHY_XS_RESET)) {
usec_delay(2);
break;
}
}
if (ctrl & IXGBE_MDIO_PHY_XS_RESET) {
DEBUGOUT("PHY reset polling failed to complete.\n");
}
out:
return (status);
}
/*
* ixgbe_read_phy_reg_generic - Reads a value from a specified PHY register
* @hw: pointer to hardware structure
* @reg_addr: 32 bit address of PHY register to read
* @phy_data: Pointer to read data from PHY register
*/
{
u32 i;
DEBUGFUNC("ixgbe_read_phy_reg_generic");
else
if (status == IXGBE_SUCCESS) {
/* Setup and write the address cycle command */
/*
* Check every 10 usec to see if the address cycle completed.
* The MDI Command bit will clear when the operation is
* complete
*/
for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) {
usec_delay(10);
if ((command & IXGBE_MSCA_MDI_COMMAND) == 0) {
break;
}
}
if ((command & IXGBE_MSCA_MDI_COMMAND) != 0) {
DEBUGOUT("PHY address command did not complete.\n");
}
if (status == IXGBE_SUCCESS) {
/*
* Address cycle complete, setup and write the read
* command
*/
/*
* Check every 10 usec to see if the address cycle
* completed. The MDI Command bit will clear when the
* operation is complete
*/
for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) {
usec_delay(10);
if ((command & IXGBE_MSCA_MDI_COMMAND) == 0)
break;
}
if ((command & IXGBE_MSCA_MDI_COMMAND) != 0) {
DEBUGOUT("PHY read command didn't complete\n");
} else {
/*
* Read operation is complete. Get the data
* from MSRWD
*/
}
}
}
return (status);
}
/*
* ixgbe_write_phy_reg_generic - Writes a value to specified PHY register
* @hw: pointer to hardware structure
* @reg_addr: 32 bit PHY register to write
* @device_type: 5 bit device type
* @phy_data: Data to write to the PHY register
*/
{
u32 i;
DEBUGFUNC("ixgbe_write_phy_reg_generic");
else
if (status == IXGBE_SUCCESS) {
/*
* Put the data in the MDI single read and write data register
*/
/* Setup and write the address cycle command */
/*
* Check every 10 usec to see if the address cycle completed.
* The MDI Command bit will clear when the operation is
* complete
*/
for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) {
usec_delay(10);
if ((command & IXGBE_MSCA_MDI_COMMAND) == 0)
break;
}
if ((command & IXGBE_MSCA_MDI_COMMAND) != 0) {
DEBUGOUT("PHY address cmd didn't complete\n");
}
if (status == IXGBE_SUCCESS) {
/*
* Address cycle complete, setup and write the write
* command
*/
/*
* Check every 10 usec to see if the address cycle
* completed. The MDI Command bit will clear when the
* operation is complete
*/
for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) {
usec_delay(10);
if ((command & IXGBE_MSCA_MDI_COMMAND) == 0)
break;
}
if ((command & IXGBE_MSCA_MDI_COMMAND) != 0) {
DEBUGOUT("PHY address cmd didn't complete\n");
}
}
}
return (status);
}
/*
* ixgbe_setup_phy_link_generic - Set and restart autoneg
* @hw: pointer to hardware structure
*
* Restart autonegotiation and PHY and waits for completion.
*/
{
bool autoneg = false;
DEBUGFUNC("ixgbe_setup_phy_link_generic");
if (speed & IXGBE_LINK_SPEED_10GB_FULL) {
/* Set or unset auto-negotiation 10G advertisement */
&autoneg_reg);
}
if (speed & IXGBE_LINK_SPEED_1GB_FULL) {
/* Set or unset auto-negotiation 1G advertisement */
&autoneg_reg);
}
if (speed & IXGBE_LINK_SPEED_100_FULL) {
/* Set or unset auto-negotiation 100M advertisement */
&autoneg_reg);
}
/* Restart PHY autonegotiation and wait for completion */
/* Wait for autonegotiation to finish */
usec_delay(10);
/* Restart PHY autonegotiation and wait for completion */
&autoneg_reg);
if (autoneg_reg == IXGBE_MII_AUTONEG_COMPLETE) {
break;
}
}
if (time_out == max_time_out) {
DEBUGOUT("ixgbe_setup_phy_link_generic: time out");
}
return (status);
}
/*
* ixgbe_setup_phy_link_speed_generic - Sets the auto advertised capabilities
* @hw: pointer to hardware structure
* @speed: new link speed
* @autoneg: true if autonegotiation enabled
*/
bool autoneg,
bool autoneg_wait_to_complete)
{
DEBUGFUNC("ixgbe_setup_phy_link_speed_generic");
/*
* Clear autoneg_advertised and set new values based on input link
* speed.
*/
if (speed & IXGBE_LINK_SPEED_10GB_FULL) {
}
if (speed & IXGBE_LINK_SPEED_1GB_FULL) {
}
if (speed & IXGBE_LINK_SPEED_100_FULL)
/* Setup link based on the new speed settings */
return (IXGBE_SUCCESS);
}
/*
* ixgbe_get_copper_link_capabilities_generic - Determines link capabilities
* @hw: pointer to hardware structure
* @speed: pointer to link speed
* @autoneg: boolean auto-negotiation value
*
* Determines the link capabilities by reading the AUTOC register.
*/
{
DEBUGFUNC("ixgbe_get_copper_link_capabilities_generic");
*speed = 0;
*autoneg = true;
if (status == IXGBE_SUCCESS) {
}
return (status);
}
/*
* ixgbe_check_phy_link_tnx - Determine link and speed status
* @hw: pointer to hardware structure
*
* Reads the VS1 register to determine if link is up and the current speed for
* the PHY.
*/
bool *link_up)
{
DEBUGFUNC("ixgbe_check_phy_link_tnx");
/* Initialize speed and link to default case */
*link_up = false;
/*
* Check current speed and link status of the PHY register.
* This is a vendor specific register and may have to
* be changed for other copper PHYs.
*/
usec_delay(10);
&phy_data);
*link_up = true;
if (phy_speed ==
break;
}
}
return (status);
}
/*
* ixgbe_setup_phy_link_tnx - Set and restart autoneg
* @hw: pointer to hardware structure
*
* Restart autonegotiation and PHY and waits for completion.
*/
{
bool autoneg = false;
DEBUGFUNC("ixgbe_setup_phy_link_tnx");
if (speed & IXGBE_LINK_SPEED_10GB_FULL) {
/* Set or unset auto-negotiation 10G advertisement */
&autoneg_reg);
}
if (speed & IXGBE_LINK_SPEED_1GB_FULL) {
/* Set or unset auto-negotiation 1G advertisement */
&autoneg_reg);
}
if (speed & IXGBE_LINK_SPEED_100_FULL) {
/* Set or unset auto-negotiation 100M advertisement */
&autoneg_reg);
}
/* Restart PHY autonegotiation and wait for completion */
/* Wait for autonegotiation to finish */
usec_delay(10);
/* Restart PHY autonegotiation and wait for completion */
&autoneg_reg);
if (autoneg_reg == IXGBE_MII_AUTONEG_COMPLETE) {
break;
}
}
if (time_out == max_time_out) {
DEBUGOUT("ixgbe_setup_phy_link_tnx: time out");
}
return (status);
}
/*
* ixgbe_get_phy_firmware_version_tnx - Gets the PHY Firmware Version
* @hw: pointer to hardware structure
* @firmware_version: pointer to the PHY Firmware Version
*/
{
DEBUGFUNC("ixgbe_get_phy_firmware_version_tnx");
return (status);
}
/*
* ixgbe_get_phy_firmware_version_generic - Gets the PHY Firmware Version
* @hw: pointer to hardware structure
* @firmware_version: pointer to the PHY Firmware Version
*/
{
DEBUGFUNC("ixgbe_get_phy_firmware_version_generic");
return (status);
}
/*
* ixgbe_reset_phy_nl - Performs a PHY reset
* @hw: pointer to hardware structure
*/
{
bool end_data = false;
u32 i;
DEBUGFUNC("ixgbe_reset_phy_nl");
/* reset the PHY and poll for completion */
for (i = 0; i < 100; i++) {
if ((phy_data & IXGBE_MDIO_PHY_XS_RESET) == 0)
break;
msec_delay(10);
}
if ((phy_data & IXGBE_MDIO_PHY_XS_RESET) != 0) {
DEBUGOUT("PHY reset did not complete.\n");
goto out;
}
/* Get init offsets */
&data_offset);
if (ret_val != IXGBE_SUCCESS)
goto out;
data_offset++;
while (!end_data) {
/*
* Read control word from PHY init contents offset
*/
switch (control) {
case IXGBE_DELAY_NL:
data_offset++;
break;
case IXGBE_DATA_NL:
DEBUGOUT("DATA: \n");
data_offset++;
for (i = 0; i < edata; i++) {
data_offset++;
phy_offset++;
}
break;
case IXGBE_CONTROL_NL:
data_offset++;
DEBUGOUT("CONTROL: \n");
if (edata == IXGBE_CONTROL_EOL_NL) {
DEBUGOUT("EOL\n");
end_data = true;
} else if (edata == IXGBE_CONTROL_SOL_NL) {
DEBUGOUT("SOL\n");
} else {
DEBUGOUT("Bad control value\n");
goto out;
}
break;
default:
DEBUGOUT("Bad control type\n");
goto out;
}
}
out:
return (ret_val);
}
/*
* ixgbe_identify_sfp_module_generic - Identifies SFP module
* @hw: pointer to hardware structure
*
* Searches for and identifies the SFP module and assigns appropriate PHY type.
*/
{
u32 vendor_oui = 0;
u8 identifier = 0;
u8 comp_codes_1g = 0;
u8 comp_codes_10g = 0;
u8 cable_tech = 0;
u8 cable_spec = 0;
u16 enforce_sfp = 0;
DEBUGFUNC("ixgbe_identify_sfp_module_generic");
goto out;
}
}
goto out;
}
/* LAN ID is needed for sfp_type determination */
if (identifier != IXGBE_SFF_IDENTIFIER_SFP) {
} else {
&cable_tech);
/*
* ID Module
* ============
* 0 SFP_DA_CU
* 1 SFP_SR
* 2 SFP_LR
* 3 SFP_DA_CORE0 - 82599-specific
* 4 SFP_DA_CORE1 - 82599-specific
* 7 SFP_act_lmt_DA_CORE0 - 82599-specific
* 8 SFP_act_lmt_DA_CORE1 - 82599-specific
* 9 SFP_1g_cu_CORE0 - 82599-specific
* 10 SFP_1g_cu_CORE1 - 82599-specific
*/
else if (comp_codes_10g & IXGBE_SFF_10GBASESR_CAPABLE)
else if (comp_codes_10g & IXGBE_SFF_10GBASELR_CAPABLE)
else
if (cable_tech & IXGBE_SFF_DA_PASSIVE_CABLE) {
else
} else if (cable_tech & IXGBE_SFF_DA_ACTIVE_CABLE) {
if (cable_spec &
else
} else
} else if (comp_codes_10g &
else
} else if (comp_codes_1g & IXGBE_SFF_1GBASET_CAPABLE) {
else
} else {
}
}
/* Determine if the SFP+ PHY is dual speed or not. */
if (((comp_codes_1g & IXGBE_SFF_1GBASESX_CAPABLE) &&
/* Determine PHY vendor */
((oui_bytes[0] <<
switch (vendor_oui) {
break;
case IXGBE_SFF_VENDOR_OUI_FTL:
else
break;
break;
break;
default:
else if (cable_tech & IXGBE_SFF_DA_ACTIVE_CABLE)
else
break;
}
}
/* Allow any DA cable vendor */
if (cable_tech & (IXGBE_SFF_DA_PASSIVE_CABLE |
goto out;
}
/* Verify supporteed 1G SFP modules */
if (comp_codes_10g == 0 &&
goto out;
}
/* Anything else 82598-based is supported */
goto out;
}
if (!(enforce_sfp & IXGBE_DEVICE_CAPS_ALLOW_ANY_SFP) &&
/* Make sure we're a supported PHY type */
} else {
DEBUGOUT("SFP+ module not supported\n");
}
} else {
}
}
out:
return (status);
}
/*
* ixgbe_get_sfp_init_sequence_offsets - Provides offset of PHY init sequence
* @hw: pointer to hardware structure
* @list_offset: offset to the SFP ID list
* @data_offset: offset to the SFP data block
*
* Checks the MAC's EEPROM to see if it supports a given SFP+ module type, if
* so it returns the offsets to the phy init sequence block.
*/
{
DEBUGFUNC("ixgbe_get_sfp_init_sequence_offsets");
return (IXGBE_ERR_SFP_NOT_SUPPORTED);
return (IXGBE_ERR_SFP_NOT_PRESENT);
return (IXGBE_ERR_SFP_NOT_SUPPORTED);
/*
* Limiting active cables and 1G Phys must be initialized as
* SR modules
*/
if (sfp_type == ixgbe_sfp_type_da_act_lmt_core0 ||
else if (sfp_type == ixgbe_sfp_type_da_act_lmt_core1 ||
/* Read offset to PHY init contents */
return (IXGBE_ERR_SFP_NO_INIT_SEQ_PRESENT);
/* Shift offset to first ID word */
(*list_offset)++;
/*
* Find the matching SFP ID in the EEPROM
* and program the init sequence
*/
while (sfp_id != IXGBE_PHY_INIT_END_NL) {
(*list_offset)++;
DEBUGOUT("SFP+ module not supported\n");
return (IXGBE_ERR_SFP_NOT_SUPPORTED);
} else {
break;
}
} else {
(*list_offset) += 2;
return (IXGBE_ERR_PHY);
}
}
if (sfp_id == IXGBE_PHY_INIT_END_NL) {
DEBUGOUT("No matching SFP+ module found\n");
return (IXGBE_ERR_SFP_NOT_SUPPORTED);
}
return (IXGBE_SUCCESS);
}
/*
* ixgbe_read_i2c_eeprom_generic - Reads 8 bit EEPROM word over I2C interface
* @hw: pointer to hardware structure
* @byte_offset: EEPROM byte offset to read
* @eeprom_data: value read
*
* Performs byte read operation to SFP module's EEPROM over I2C interface.
*/
{
DEBUGFUNC("ixgbe_read_i2c_eeprom_generic");
}
/*
* ixgbe_write_i2c_eeprom_generic - Writes 8 bit EEPROM word over I2C interface
* @hw: pointer to hardware structure
* @byte_offset: EEPROM byte offset to write
* @eeprom_data: value to write
*
* Performs byte write operation to SFP module's EEPROM over I2C interface.
*/
{
DEBUGFUNC("ixgbe_write_i2c_eeprom_generic");
}
/*
* ixgbe_read_i2c_byte_generic - Reads 8 bit word over I2C
* @hw: pointer to hardware structure
* @byte_offset: byte offset to read
* @data: value read
*
* Performs byte read operation to SFP module's EEPROM over I2C interface at
* a specified deivce address.
*/
{
bool nack = 1;
DEBUGFUNC("ixgbe_read_i2c_byte_generic");
else
do {
goto read_byte_out;
}
/* Device Address and write indication */
if (status != IXGBE_SUCCESS)
goto fail;
if (status != IXGBE_SUCCESS)
goto fail;
if (status != IXGBE_SUCCESS)
goto fail;
if (status != IXGBE_SUCCESS)
goto fail;
/* Device Address and read indication */
if (status != IXGBE_SUCCESS)
goto fail;
if (status != IXGBE_SUCCESS)
goto fail;
if (status != IXGBE_SUCCESS)
goto fail;
if (status != IXGBE_SUCCESS)
goto fail;
break;
fail:
msec_delay(100);
retry++;
DEBUGOUT("I2C byte read error - Retrying.\n");
else
DEBUGOUT("I2C byte read error.\n");
return (status);
}
/*
* ixgbe_write_i2c_byte_generic - Writes 8 bit word over I2C
* @hw: pointer to hardware structure
* @byte_offset: byte offset to write
* @data: value to write
*
* Performs byte write operation to SFP module's EEPROM over I2C interface at
* a specified device address.
*/
{
DEBUGFUNC("ixgbe_write_i2c_byte_generic");
else
goto write_byte_out;
}
do {
if (status != IXGBE_SUCCESS)
goto fail;
if (status != IXGBE_SUCCESS)
goto fail;
if (status != IXGBE_SUCCESS)
goto fail;
if (status != IXGBE_SUCCESS)
goto fail;
if (status != IXGBE_SUCCESS)
goto fail;
if (status != IXGBE_SUCCESS)
goto fail;
break;
fail:
retry++;
DEBUGOUT("I2C byte write error - Retrying.\n");
else
DEBUGOUT("I2C byte write error.\n");
return (status);
}
/*
* ixgbe_i2c_start - Sets I2C start condition
* @hw: pointer to hardware structure
*
* Sets I2C start condition (High -> Low on SDA while SCL is High)
*/
static void
{
DEBUGFUNC("ixgbe_i2c_start");
/* Start condition must begin with data and clock high */
/* Setup time for start condition (4.7us) */
/* Hold time for start condition (4us) */
/* Minimum low period of clock is 4.7 us */
}
/*
* ixgbe_i2c_stop - Sets I2C stop condition
* @hw: pointer to hardware structure
*
* Sets I2C stop condition (Low -> High on SDA while SCL is High)
*/
static void
{
DEBUGFUNC("ixgbe_i2c_stop");
/* Stop condition must begin with data low and clock high */
/* Setup time for stop condition (4us) */
/* bus free time between stop and start (4.7us) */
}
/*
* ixgbe_clock_in_i2c_byte - Clocks in one byte via I2C
* @hw: pointer to hardware structure
* @data: data byte to clock in
*
*/
static s32
{
s32 i;
bool bit = 0;
DEBUGFUNC("ixgbe_clock_in_i2c_byte");
for (i = 7; i >= 0; i--) {
if (status != IXGBE_SUCCESS)
break;
}
return (status);
}
/*
* ixgbe_clock_out_i2c_byte - Clocks out one byte via I2C
* @hw: pointer to hardware structure
* @data: data byte clocked out
*
*/
static s32
{
s32 i;
bool bit = 0;
DEBUGFUNC("ixgbe_clock_out_i2c_byte");
for (i = 7; i >= 0; i--) {
if (status != IXGBE_SUCCESS)
break;
}
/* Release SDA line (set high) */
return (status);
}
/*
* ixgbe_get_i2c_ack - Polls for I2C ACK
* @hw: pointer to hardware structure
*
*/
static s32
{
u32 i = 0;
bool ack = 1;
DEBUGFUNC("ixgbe_get_i2c_ack");
if (status != IXGBE_SUCCESS)
goto out;
/* Minimum high period of clock is 4us */
/*
* Poll for ACK. Note that ACK in I2C spec is
* transition from 1 to 0
*/
for (i = 0; i < timeout; i++) {
usec_delay(1);
if (ack == 0)
break;
}
if (ack == 1) {
DEBUGOUT("I2C ack was not received.\n");
}
/* Minimum low period of clock is 4.7 us */
out:
return (status);
}
/*
* @hw: pointer to hardware structure
* @data: read data value
*
*/
static s32
{
DEBUGFUNC("ixgbe_clock_in_i2c_bit");
/* Minimum high period of clock is 4us */
/* Minimum low period of clock is 4.7 us */
return (status);
}
/*
* @hw: pointer to hardware structure
* @data: data value to write
*
*/
static s32
{
DEBUGFUNC("ixgbe_clock_out_i2c_bit");
if (status == IXGBE_SUCCESS) {
/* Minimum high period of clock is 4us */
/*
* Minimum low period of clock is 4.7 us.
* This also takes care of the data hold time.
*/
} else {
}
return (status);
}
/*
* ixgbe_raise_i2c_clk - Raises the I2C SCL clock
* @hw: pointer to hardware structure
* @i2cctl: Current value of I2CCTL register
*
* Raises the I2C clock line '0'->'1'
*/
static s32
{
DEBUGFUNC("ixgbe_raise_i2c_clk");
*i2cctl |= IXGBE_I2C_CLK_OUT;
/* SCL rise time (1000ns) */
return (status);
}
/*
* ixgbe_lower_i2c_clk - Lowers the I2C SCL clock
* @hw: pointer to hardware structure
* @i2cctl: Current value of I2CCTL register
*
* Lowers the I2C clock line '1'->'0'
*/
static void
{
DEBUGFUNC("ixgbe_lower_i2c_clk");
*i2cctl &= ~IXGBE_I2C_CLK_OUT;
/* SCL fall time (300ns) */
}
/*
* ixgbe_set_i2c_data - Sets the I2C data bit
* @hw: pointer to hardware structure
* @i2cctl: Current value of I2CCTL register
* @data: I2C data value (0 or 1) to set
*
* Sets the I2C data bit
*/
static s32
{
DEBUGFUNC("ixgbe_set_i2c_data");
if (data)
*i2cctl |= IXGBE_I2C_DATA_OUT;
else
*i2cctl &= ~IXGBE_I2C_DATA_OUT;
/* Verify data was set correctly */
}
return (status);
}
/*
* ixgbe_get_i2c_data - Reads the I2C SDA data bit
* @hw: pointer to hardware structure
* @i2cctl: Current value of I2CCTL register
*
* Returns the I2C data bit value
*/
static bool
{
bool data;
DEBUGFUNC("ixgbe_get_i2c_data");
if (*i2cctl & IXGBE_I2C_DATA_IN)
data = 1;
else
data = 0;
return (data);
}
/*
* ixgbe_i2c_bus_clear - Clears the I2C bus
* @hw: pointer to hardware structure
*
* Clears the I2C bus by sending nine clock pulses.
* Used when data line is stuck low.
*/
void
{
u32 i;
DEBUGFUNC("ixgbe_i2c_bus_clear");
for (i = 0; i < 9; i++) {
/* Min high period of clock is 4us */
/* Min low period of clock is 4.7us */
}
/* Put the i2c bus back to default state */
}
/*
* ixgbe_tn_check_overtemp - Checks if an overtemp occured.
* @hw: pointer to hardware structure
*
* Checks if the LASI temp alarm status was triggered due to overtemp
*/
{
DEBUGFUNC("ixgbe_tn_check_overtemp");
goto out;
/* Check that the LASI temp alarm status was triggered */
if (!(phy_data & IXGBE_TN_LASI_STATUS_TEMP_ALARM))
goto out;
out:
return (status);
}