ixgbe_phy.c revision 13740cb230f19fcbf1a6468d1a6a0ba9a0a09c22
/*
* CDDL HEADER START
*
* Copyright(c) 2007-2008 Intel Corporation. All rights reserved.
* The contents of this file are subject to the terms of the
* Common Development and Distribution License (the "License").
* You may not use this file except in compliance with the License.
*
* You can obtain a copy of the license at:
* See the License for the specific language governing permissions
* and limitations under the License.
*
* When using or redistributing this file, you may do so under the
* License only. No other modification of this header is permitted.
*
* If applicable, add the following below this CDDL HEADER, with the
* fields enclosed by brackets "[]" replaced with your own identifying
* information: Portions Copyright [yyyy] [name of copyright owner]
*
* CDDL HEADER END
*/
/*
* Copyright 2009 Sun Microsystems, Inc. All rights reserved.
* Use is subject to license terms of the CDDL.
*/
/* IntelVersion: 1.60 v2008-09-12 */
#include "ixgbe_api.h"
#include "ixgbe_common.h"
#include "ixgbe_phy.h"
#ident "$Id: ixgbe_phy.c,v 1.60 2008/09/15 15:47:02 mrchilak Exp $"
/*
* ixgbe_init_phy_ops_generic - Inits PHY function ptrs
* @hw: pointer to the hardware structure
*
* Initialize the function pointers.
*/
{
/* PHY */
return (IXGBE_SUCCESS);
}
/*
* ixgbe_identify_phy_generic - Get physical layer module
* @hw: pointer to hardware structure
*
* Determines the physical layer module found on the current adapter.
*/
{
(void) ixgbe_get_phy_id(hw);
break;
}
}
} else {
}
return (status);
}
/*
* ixgbe_validate_phy_addr - Determines phy address is valid
* @hw: pointer to hardware structure
*
*/
bool
{
bool valid = false;
valid = true;
return (valid);
}
/*
* ixgbe_get_phy_id - Get the phy type
* @hw: pointer to hardware structure
*
*/
{
u16 phy_id_high = 0;
u16 phy_id_low = 0;
&phy_id_high);
if (status == IXGBE_SUCCESS) {
&phy_id_low);
}
return (status);
}
/*
* ixgbe_get_phy_type_from_id - Get the phy type
* @hw: pointer to hardware structure
*
*/
enum ixgbe_phy_type
{
enum ixgbe_phy_type phy_type;
switch (phy_id) {
case TN1010_PHY_ID:
break;
case QT2022_PHY_ID:
break;
case ATH_PHY_ID:
break;
default:
break;
}
return (phy_type);
}
/*
* ixgbe_reset_phy_generic - Performs a PHY reset
* @hw: pointer to hardware structure
*/
{
/*
* Perform soft PHY reset to the PHY_XS.
* This will cause a soft reset to the PHY
*/
}
/*
* ixgbe_read_phy_reg_generic - Reads a value from a specified PHY register
* @hw: pointer to hardware structure
* @reg_addr: 32 bit address of PHY register to read
* @phy_data: Pointer to read data from PHY register
*/
{
u32 i;
else
if (status == IXGBE_SUCCESS) {
/* Setup and write the address cycle command */
/*
* Check every 10 usec to see if the address cycle completed.
* The MDI Command bit will clear when the operation is
* complete
*/
for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) {
usec_delay(10);
if ((command & IXGBE_MSCA_MDI_COMMAND) == 0) {
break;
}
}
if ((command & IXGBE_MSCA_MDI_COMMAND) != 0) {
DEBUGOUT("PHY address command did not complete.\n");
}
if (status == IXGBE_SUCCESS) {
/*
* Address cycle complete, setup and write the read
* command
*/
/*
* Check every 10 usec to see if the address cycle
* completed. The MDI Command bit will clear when the
* operation is complete
*/
for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) {
usec_delay(10);
if ((command & IXGBE_MSCA_MDI_COMMAND) == 0)
break;
}
if ((command & IXGBE_MSCA_MDI_COMMAND) != 0) {
DEBUGOUT("PHY read command didn't complete\n");
} else {
/*
* Read operation is complete. Get the data
* from MSRWD
*/
}
}
}
return (status);
}
/*
* ixgbe_write_phy_reg_generic - Writes a value to specified PHY register
* @hw: pointer to hardware structure
* @reg_addr: 32 bit PHY register to write
* @device_type: 5 bit device type
* @phy_data: Data to write to the PHY register
*/
{
u32 i;
else
if (status == IXGBE_SUCCESS) {
/*
* Put the data in the MDI single read and write data register
*/
/* Setup and write the address cycle command */
/*
* Check every 10 usec to see if the address cycle completed.
* The MDI Command bit will clear when the operation is
* complete
*/
for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) {
usec_delay(10);
if ((command & IXGBE_MSCA_MDI_COMMAND) == 0)
break;
}
if ((command & IXGBE_MSCA_MDI_COMMAND) != 0) {
DEBUGOUT("PHY address cmd didn't complete\n");
}
if (status == IXGBE_SUCCESS) {
/*
* Address cycle complete, setup and write the write
* command
*/
/*
* Check every 10 usec to see if the address cycle
* completed. The MDI Command bit will clear when the
* operation is complete
*/
for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) {
usec_delay(10);
if ((command & IXGBE_MSCA_MDI_COMMAND) == 0)
break;
}
if ((command & IXGBE_MSCA_MDI_COMMAND) != 0) {
DEBUGOUT("PHY address cmd didn't complete\n");
}
}
}
return (status);
}
/*
* ixgbe_setup_phy_link_generic - Set and restart autoneg
* @hw: pointer to hardware structure
*
* Restart autonegotiation and PHY and waits for completion.
*/
{
/*
* Set advertisement settings in PHY based on autoneg_advertised
* settings. If autoneg_advertised = 0, then advertise default values
* tnx devices cannot be "forced" to a autoneg 10G and fail. But can
* for a 1G.
*/
else
/* Restart PHY autonegotiation and wait for completion */
/* Wait for autonegotiation to finish */
usec_delay(10);
/* Restart PHY autonegotiation and wait for completion */
&autoneg_reg);
if (autoneg_reg == IXGBE_MII_AUTONEG_COMPLETE) {
break;
}
}
if (time_out == max_time_out)
return (status);
}
/*
* ixgbe_setup_phy_link_speed_generic - Sets the auto advertised capabilities
* @hw: pointer to hardware structure
* @speed: new link speed
* @autoneg: true if autonegotiation enabled
*/
bool autoneg,
bool autoneg_wait_to_complete)
{
/*
* Clear autoneg_advertised and set new values based on input link
* speed.
*/
if (speed & IXGBE_LINK_SPEED_10GB_FULL) {
}
if (speed & IXGBE_LINK_SPEED_1GB_FULL) {
}
/* Setup link based on the new speed settings */
return (IXGBE_SUCCESS);
}
/*
* ixgbe_check_phy_link_tnx - Determine link and speed status
* @hw: pointer to hardware structure
*
* Reads the VS1 register to determine if link is up and the current speed for
* the PHY.
*/
bool *link_up)
{
/* Initialize speed and link to default case */
*link_up = false;
/*
* Check current speed and link status of the PHY register.
* This is a vendor specific register and may have to
* be changed for other copper PHYs.
*/
usec_delay(10);
&phy_data);
*link_up = true;
if (phy_speed ==
break;
}
}
return (status);
}
/*
* ixgbe_get_phy_firmware_version_tnx - Gets the PHY Firmware Version
* @hw: pointer to hardware structure
* @firmware_version: pointer to the PHY Firmware Version
*/
{
return (status);
}
/*
* ixgbe_reset_phy_nl - Performs a PHY reset
* @hw: pointer to hardware structure
*/
{
bool end_data = false;
u32 i;
/* reset the PHY and poll for completion */
for (i = 0; i < 100; i++) {
if ((phy_data & IXGBE_MDIO_PHY_XS_RESET) == 0)
break;
msec_delay(10);
}
if ((phy_data & IXGBE_MDIO_PHY_XS_RESET) != 0) {
DEBUGOUT("PHY reset did not complete.\n");
goto out;
}
/* Get init offsets */
&data_offset);
if (ret_val != IXGBE_SUCCESS)
goto out;
data_offset++;
while (!end_data) {
/*
* Read control word from PHY init contents offset
*/
switch (control) {
case IXGBE_DELAY_NL:
data_offset++;
break;
case IXGBE_DATA_NL:
DEBUGOUT("DATA: \n");
data_offset++;
for (i = 0; i < edata; i++) {
data_offset++;
phy_offset++;
}
break;
case IXGBE_CONTROL_NL:
data_offset++;
DEBUGOUT("CONTROL: \n");
if (edata == IXGBE_CONTROL_EOL_NL) {
DEBUGOUT("EOL\n");
end_data = true;
} else if (edata == IXGBE_CONTROL_SOL_NL) {
DEBUGOUT("SOL\n");
} else {
DEBUGOUT("Bad control value\n");
goto out;
}
break;
default:
DEBUGOUT("Bad control type\n");
goto out;
}
}
out:
return (ret_val);
}
/*
* ixgbe_identify_sfp_module_generic - Identifies SFP module and assigns
* the PHY type.
* @hw: pointer to hardware structure
*
* Searches for and identifies the SFP module. Assigns appropriate PHY type.
*/
{
u32 vendor_oui = 0;
u8 identifier = 0;
u8 comp_codes_1g = 0;
u8 comp_codes_10g = 0;
u8 transmission_media = 0;
if (status == IXGBE_ERR_SFP_NOT_PRESENT) {
goto out;
}
if (identifier == IXGBE_SFF_IDENTIFIER_SFP) {
/*
* ID Module
* ============
* 0 SFP_DA_CU
* 1 SFP_SR
* 2 SFP_LR
*/
else if (comp_codes_10g & IXGBE_SFF_10GBASESR_CAPABLE)
else if (comp_codes_10g & IXGBE_SFF_10GBASELR_CAPABLE)
else
/* Determine PHY vendor */
((oui_bytes[0] <<
switch (vendor_oui) {
if (transmission_media &
break;
case IXGBE_SFF_VENDOR_OUI_FTL:
break;
break;
default:
if (transmission_media &
else
break;
}
}
}
out:
return (status);
}
/*
* ixgbe_get_sfp_init_sequence_offsets - Checks the MAC's EEPROM to see
* if it supports a given SFP+ module type, if so it returns the offsets to the
* phy init sequence block.
* @hw: pointer to hardware structure
* @list_offset: offset to the SFP ID list
* @data_offset: offset to the SFP data block
*/
{
return (IXGBE_ERR_SFP_NOT_SUPPORTED);
return (IXGBE_ERR_SFP_NOT_PRESENT);
return (IXGBE_ERR_SFP_NOT_SUPPORTED);
/* Read offset to PHY init contents */
return (IXGBE_ERR_PHY);
/* Shift offset to first ID word */
(*list_offset)++;
/*
* Find the matching SFP ID in the EEPROM
* and program the init sequence
*/
while (sfp_id != IXGBE_PHY_INIT_END_NL) {
(*list_offset)++;
DEBUGOUT("SFP+ module not supported\n");
return (IXGBE_ERR_SFP_NOT_SUPPORTED);
} else {
break;
}
} else {
(*list_offset) += 2;
return (IXGBE_ERR_PHY);
}
}
if (sfp_id == IXGBE_PHY_INIT_END_NL) {
DEBUGOUT("No matching SFP+ module found\n");
return (IXGBE_ERR_SFP_NOT_SUPPORTED);
}
return (IXGBE_SUCCESS);
}