ixgbe_main.c revision 837c1ac4e72b7d86278cca88b1075af557f7d161
/*
* CDDL HEADER START
*
* Copyright(c) 2007-2009 Intel Corporation. All rights reserved.
* The contents of this file are subject to the terms of the
* Common Development and Distribution License (the "License").
* You may not use this file except in compliance with the License.
*
* You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
* See the License for the specific language governing permissions
* and limitations under the License.
*
* When distributing Covered Code, include this CDDL HEADER in each
* file and include the License file at usr/src/OPENSOLARIS.LICENSE.
* If applicable, add the following below this CDDL HEADER, with the
* fields enclosed by brackets "[]" replaced with your own identifying
* information: Portions Copyright [yyyy] [name of copyright owner]
*
* CDDL HEADER END
*/
/*
* Copyright 2009 Sun Microsystems, Inc. All rights reserved.
* Use is subject to license terms.
*/
#include "ixgbe_sw.h"
static char ident[] = "Intel 10Gb Ethernet";
static char ixgbe_version[] = "ixgbe 1.1.3";
/*
* Local function protoypes
*/
static int ixgbe_register_mac(ixgbe_t *);
static int ixgbe_identify_hardware(ixgbe_t *);
static int ixgbe_regs_map(ixgbe_t *);
static void ixgbe_init_properties(ixgbe_t *);
static int ixgbe_init_driver_settings(ixgbe_t *);
static void ixgbe_init_locks(ixgbe_t *);
static void ixgbe_destroy_locks(ixgbe_t *);
static int ixgbe_init(ixgbe_t *);
static int ixgbe_chip_start(ixgbe_t *);
static void ixgbe_chip_stop(ixgbe_t *);
static int ixgbe_reset(ixgbe_t *);
static void ixgbe_tx_clean(ixgbe_t *);
static int ixgbe_alloc_rings(ixgbe_t *);
static void ixgbe_free_rings(ixgbe_t *);
static int ixgbe_alloc_rx_data(ixgbe_t *);
static void ixgbe_free_rx_data(ixgbe_t *);
static void ixgbe_setup_rings(ixgbe_t *);
static void ixgbe_setup_rx(ixgbe_t *);
static void ixgbe_setup_tx(ixgbe_t *);
static void ixgbe_setup_rx_ring(ixgbe_rx_ring_t *);
static void ixgbe_setup_tx_ring(ixgbe_tx_ring_t *);
static void ixgbe_setup_rss(ixgbe_t *);
static void ixgbe_init_unicst(ixgbe_t *);
static void ixgbe_setup_multicst(ixgbe_t *);
static void ixgbe_get_hw_state(ixgbe_t *);
static void ixgbe_get_conf(ixgbe_t *);
static void ixgbe_init_params(ixgbe_t *);
static int ixgbe_get_prop(ixgbe_t *, char *, int, int, int);
static void ixgbe_driver_link_check(ixgbe_t *);
static void ixgbe_sfp_check(void *);
static void ixgbe_link_timer(void *);
static void ixgbe_local_timer(void *);
static void ixgbe_arm_watchdog_timer(ixgbe_t *);
static void ixgbe_restart_watchdog_timer(ixgbe_t *);
static void ixgbe_disable_adapter_interrupts(ixgbe_t *);
static void ixgbe_enable_adapter_interrupts(ixgbe_t *);
static void ixgbe_set_internal_mac_loopback(ixgbe_t *);
static int ixgbe_alloc_intrs(ixgbe_t *);
static int ixgbe_alloc_intr_handles(ixgbe_t *, int);
static int ixgbe_add_intr_handlers(ixgbe_t *);
static void ixgbe_map_rxring_to_vector(ixgbe_t *, int, int);
static void ixgbe_map_txring_to_vector(ixgbe_t *, int, int);
static int ixgbe_map_intrs_to_vectors(ixgbe_t *);
static void ixgbe_setup_adapter_vector(ixgbe_t *);
static void ixgbe_rem_intr_handlers(ixgbe_t *);
static void ixgbe_rem_intrs(ixgbe_t *);
static int ixgbe_enable_intrs(ixgbe_t *);
static int ixgbe_disable_intrs(ixgbe_t *);
static uint_t ixgbe_intr_legacy(void *, void *);
static uint_t ixgbe_intr_msi(void *, void *);
static uint_t ixgbe_intr_msix(void *, void *);
static void ixgbe_intr_rx_work(ixgbe_rx_ring_t *);
static void ixgbe_intr_tx_work(ixgbe_tx_ring_t *);
static void ixgbe_get_driver_control(struct ixgbe_hw *);
static int ixgbe_addmac(void *, const uint8_t *);
static int ixgbe_remmac(void *, const uint8_t *);
static void ixgbe_release_driver_control(struct ixgbe_hw *);
static int ixgbe_resume(dev_info_t *);
static int ixgbe_suspend(dev_info_t *);
const void *impl_data);
static void ixgbe_fm_init(ixgbe_t *);
static void ixgbe_fm_fini(ixgbe_t *);
{"_tx_copy_thresh", MAC_PROP_PERM_RW},
{"_tx_recycle_thresh", MAC_PROP_PERM_RW},
{"_tx_overload_thresh", MAC_PROP_PERM_RW},
{"_tx_resched_thresh", MAC_PROP_PERM_RW},
{"_rx_copy_thresh", MAC_PROP_PERM_RW},
{"_rx_limit_per_intr", MAC_PROP_PERM_RW},
{"_intr_throttling", MAC_PROP_PERM_RW},
{"_adv_pause_cap", MAC_PROP_PERM_READ},
{"_adv_asym_pause_cap", MAC_PROP_PERM_READ}
};
#define IXGBE_MAX_PRIV_PROPS \
(sizeof (ixgbe_priv_props) / sizeof (mac_priv_prop_t))
static struct cb_ops ixgbe_cb_ops = {
nulldev, /* cb_open */
nulldev, /* cb_close */
nodev, /* cb_strategy */
nodev, /* cb_print */
nodev, /* cb_dump */
nodev, /* cb_read */
nodev, /* cb_write */
nodev, /* cb_ioctl */
nodev, /* cb_devmap */
nodev, /* cb_mmap */
nodev, /* cb_segmap */
nochpoll, /* cb_chpoll */
ddi_prop_op, /* cb_prop_op */
NULL, /* cb_stream */
CB_REV, /* cb_rev */
nodev, /* cb_aread */
nodev /* cb_awrite */
};
static struct dev_ops ixgbe_dev_ops = {
DEVO_REV, /* devo_rev */
0, /* devo_refcnt */
NULL, /* devo_getinfo */
nulldev, /* devo_identify */
nulldev, /* devo_probe */
ixgbe_attach, /* devo_attach */
ixgbe_detach, /* devo_detach */
nodev, /* devo_reset */
&ixgbe_cb_ops, /* devo_cb_ops */
NULL, /* devo_bus_ops */
ddi_power, /* devo_power */
ddi_quiesce_not_supported, /* devo_quiesce */
};
static struct modldrv ixgbe_modldrv = {
&mod_driverops, /* Type of module. This one is a driver */
ident, /* Discription string */
&ixgbe_dev_ops /* driver ops */
};
static struct modlinkage ixgbe_modlinkage = {
};
/*
* Access attributes for register mapping
*/
};
/*
* Loopback property
*/
static lb_property_t lb_normal = {
};
static lb_property_t lb_mac = {
};
static lb_property_t lb_external = {
};
#define IXGBE_M_CALLBACK_FLAGS \
static mac_callbacks_t ixgbe_m_callbacks = {
NULL,
NULL,
NULL,
NULL,
};
/*
* Initialize capabilities of each supported adapter type
*/
static adapter_info_t ixgbe_82598eb_cap = {
64, /* maximum number of rx queues */
1, /* minimum number of rx queues */
8, /* default number of rx queues */
32, /* maximum number of tx queues */
1, /* minimum number of tx queues */
8, /* default number of tx queues */
16366, /* maximum MTU size */
0xFFFF, /* maximum interrupt throttle rate */
0, /* minimum interrupt throttle rate */
200, /* default interrupt throttle rate */
18, /* maximum total msix vectors */
16, /* maximum number of ring vectors */
2, /* maximum number of other vectors */
IXGBE_EICR_LSC, /* "other" interrupt types handled */
(IXGBE_FLAG_DCA_CAPABLE /* capability flags */
};
static adapter_info_t ixgbe_82599eb_cap = {
128, /* maximum number of rx queues */
1, /* minimum number of rx queues */
8, /* default number of rx queues */
128, /* maximum number of tx queues */
1, /* minimum number of tx queues */
8, /* default number of tx queues */
15500, /* maximum MTU size */
0xFF8, /* maximum interrupt throttle rate */
0, /* minimum interrupt throttle rate */
200, /* default interrupt throttle rate */
64, /* maximum total msix vectors */
16, /* maximum number of ring vectors */
2, /* maximum number of other vectors */
IXGBE_EICR_LSC, /* "other" interrupt types handled */
(IXGBE_FLAG_DCA_CAPABLE /* capability flags */
};
/*
* Module Initialization Functions.
*/
int
_init(void)
{
int status;
if (status != DDI_SUCCESS) {
}
return (status);
}
int
_fini(void)
{
int status;
if (status == DDI_SUCCESS) {
}
return (status);
}
int
{
int status;
return (status);
}
/*
* ixgbe_attach - Driver attach.
*
* This function is the device specific initialization entry
* point. This entry point is required and must be written.
* The DDI_ATTACH command must be provided in the attach entry
* point. When attach() is called with cmd set to DDI_ATTACH,
* all normal kernel services (such as kmem_alloc(9F)) are
* available for use by the driver.
*
* The attach() function will be called once for each instance
* of the device on the system with cmd set to DDI_ATTACH.
* Until attach() succeeds, the only driver entry points which
* may be called are open(9E) and getinfo(9E).
*/
static int
{
struct ixgbe_osdep *osdep;
int instance;
char taskqname[32];
/*
* Check the command and perform corresponding operations
*/
switch (cmd) {
default:
return (DDI_FAILURE);
case DDI_RESUME:
return (ixgbe_resume(devinfo));
case DDI_ATTACH:
break;
}
/* Get the device instance */
/* Allocate memory for the instance data structure */
/* Attach the instance pointer to the dev_info data structure */
/*
* Initialize for fma support
*/
/*
* Map PCI config space registers
*/
goto attach_fail;
}
/*
* Identify the chipset family
*/
goto attach_fail;
}
/*
* Map device registers
*/
goto attach_fail;
}
/*
* Initialize driver parameters
*/
/*
* Allocate interrupts
*/
goto attach_fail;
}
/*
* allocated interrupt vectors, so we should allocate the rings after
* interrupts are allocated.
*/
goto attach_fail;
}
/*
* Map rings to interrupt vectors
*/
goto attach_fail;
}
/*
* Add interrupt handlers
*/
goto attach_fail;
}
/*
* Create a taskq for sfp-change
*/
goto attach_fail;
}
/*
* Initialize driver parameters
*/
goto attach_fail;
}
/*
* Initialize mutexes for this device.
* Do this before enabling the interrupt handler and
* register the softint to avoid the condition where
* interrupt handler can try using uninitialized mutex.
*/
/*
* Initialize chipset hardware
*/
goto attach_fail;
}
(IXGBE_LINK_UP_TIME * 100000000ULL);
goto attach_fail;
}
/*
* Initialize statistics
*/
goto attach_fail;
}
/*
* Register the driver to the MAC
*/
goto attach_fail;
}
if (ixgbe->periodic_id == 0) {
goto attach_fail;
}
/*
* Now that mutex locks are initialized, and the chip is also
* initialized, enable interrupts.
*/
goto attach_fail;
}
return (DDI_SUCCESS);
return (DDI_FAILURE);
}
/*
* ixgbe_detach - Driver detach.
*
* The detach() function is the complement of the attach routine.
* If cmd is set to DDI_DETACH, detach() is used to remove the
* state associated with a given instance of a device node
* prior to the removal of that instance from the system.
*
* The detach() function will be called once for each instance
* of the device for which there has been a successful attach()
* once there are no longer any opens on the device.
*
* Interrupts routine are disabled, All memory allocated by this
* driver are freed.
*/
static int
{
/*
* Check detach command
*/
switch (cmd) {
default:
return (DDI_FAILURE);
case DDI_SUSPEND:
return (ixgbe_suspend(devinfo));
case DDI_DETACH:
break;
}
/*
* Get the pointer to the driver private data structure
*/
return (DDI_FAILURE);
/*
* If the device is still running, it needs to be stopped first.
* This check is necessary because under some specific circumstances,
* the detach routine can be called without stopping the interface
* first.
*/
/* Disable and stop the watchdog timer */
}
/*
* Check if there are still rx buffers held by the upper layer.
* If so, fail the detach.
*/
if (!ixgbe_rx_drain(ixgbe))
return (DDI_FAILURE);
/*
* Do the remaining unconfigure routines
*/
return (DDI_SUCCESS);
}
static void
{
/*
* Disable interrupt
*/
(void) ixgbe_disable_intrs(ixgbe);
}
/*
* remove the link check timer
*/
}
}
/*
* Unregister MAC
*/
}
/*
* Free statistics
*/
}
/*
* Remove interrupt handlers
*/
}
/*
* Remove taskq for sfp-status-change
*/
}
/*
* Remove interrupts
*/
}
/*
* Remove driver properties
*/
(void) ddi_prop_remove_all(devinfo);
}
/*
* Stop the chipset
*/
}
/*
* Free register handle
*/
}
/*
* Free PCI config handle
*/
}
/*
* Free locks
*/
}
/*
*/
}
/*
* Unregister FMA capabilities
*/
}
/*
* Free the driver data structure
*/
}
/*
* ixgbe_register_mac - Register the driver and its function pointers with
* the GLD interface.
*/
static int
{
int status;
return (IXGBE_FAILURE);
}
/*
* ixgbe_identify_hardware - Identify the type of the chipset.
*/
static int
{
/*
* Get the device id
*/
hw->revision_id =
/*
* Set the mac type of the adapter based on the device id
*/
return (IXGBE_FAILURE);
}
/*
* Install adapter capabilities
*/
case ixgbe_mac_82598EB:
}
break;
case ixgbe_mac_82599EB:
break;
default:
"adapter not supported in ixgbe_identify_hardware(): %d\n",
return (IXGBE_FAILURE);
}
return (IXGBE_SUCCESS);
}
/*
* ixgbe_regs_map - Map the device registers.
*
*/
static int
{
/*
* First get the size of device registers to be mapped.
*/
!= DDI_SUCCESS) {
return (IXGBE_FAILURE);
}
/*
* Call ddi_regs_map_setup() to map registers
*/
return (IXGBE_FAILURE);
}
return (IXGBE_SUCCESS);
}
/*
* ixgbe_init_properties - Initialize driver properties.
*/
static void
{
/*
* Get conf file properties, including link settings
* jumbo frames, ring number, descriptor number, etc.
*/
}
/*
* ixgbe_init_driver_settings - Initialize driver settings.
*
* The settings include hardware function pointers, bus information,
* need to be setup during driver initialization.
*/
static int
{
int i;
/*
* Initialize chipset specific hardware function pointers
*/
return (IXGBE_FAILURE);
}
/*
* Get the system page size
*/
/*
* Set rx buffer size
*
* The IP header alignment room is counted in the calculation.
* The rx buffer size is in unit of 1K that is required by the
* chipset hardware.
*/
/*
* Set tx buffer size
*/
/*
*/
for (i = 0; i < ixgbe->num_rx_rings; i++) {
}
for (i = 0; i < ixgbe->num_tx_rings; i++) {
if (ixgbe->tx_head_wb_enable)
else
}
/*
* Initialize values of interrupt throttling rate
*/
for (i = 1; i < MAX_INTR_VECTOR; i++)
/*
* The initial link state should be "unknown"
*/
return (IXGBE_SUCCESS);
}
/*
* ixgbe_init_locks - Initialize locks.
*/
static void
{
int i;
for (i = 0; i < ixgbe->num_rx_rings; i++) {
}
for (i = 0; i < ixgbe->num_tx_rings; i++) {
}
}
/*
* ixgbe_destroy_locks - Destroy locks.
*/
static void
{
int i;
for (i = 0; i < ixgbe->num_rx_rings; i++) {
}
for (i = 0; i < ixgbe->num_tx_rings; i++) {
}
}
static int
{
int i;
return (DDI_FAILURE);
return (DDI_FAILURE);
}
/*
* Enable and start the watchdog timer
*/
}
for (i = 0; i < ixgbe->num_tx_rings; i++) {
}
}
return (DDI_SUCCESS);
}
static int
{
return (DDI_FAILURE);
return (DDI_SUCCESS);
}
/*
* Disable and stop the watchdog timer
*/
return (DDI_SUCCESS);
}
/*
* ixgbe_init - Initialize the device.
*/
static int
{
/*
* Reset chipset to put the hardware in a known state
* before we try to do anything with the eeprom.
*/
goto init_fail;
}
/*
* Need to init eeprom before validating the checksum.
*/
if (ixgbe_init_eeprom_params(hw) < 0) {
"Unable to intitialize the eeprom interface.");
goto init_fail;
}
/*
* NVM validation
*/
/*
* Some PCI-E parts fail the first check due to
* the link being in sleep state. Call it again,
* if it fails a second time it's a real issue.
*/
"Invalid NVM checksum. Please contact "
"the vendor to update the NVM.");
goto init_fail;
}
}
/*
* & flow control type is controlled by ixgbe.conf
*/
/*
* Initialize link settings
*/
/*
* Initialize the chipset hardware
*/
goto init_fail;
}
goto init_fail;
}
return (IXGBE_SUCCESS);
/*
* Reset PHY
*/
(void) ixgbe_reset_phy(hw);
return (IXGBE_FAILURE);
}
/*
* ixgbe_chip_start - Initialize and start the chipset hardware.
*/
static int
{
int ret_val, i;
/*
* Get the mac address
* This function should handle SPARC case correctly.
*/
if (!ixgbe_find_mac_address(ixgbe)) {
return (IXGBE_FAILURE);
}
/*
* Validate the mac address
*/
(void) ixgbe_init_rx_addrs(hw);
return (IXGBE_FAILURE);
}
/*
* Configure/Initialize hardware
*/
if (ret_val != IXGBE_SUCCESS) {
if (ret_val == IXGBE_ERR_EEPROM_VERSION) {
"This 82599 device is pre-release and contains"
" outdated firmware, please contact your hardware"
" vendor for a replacement.");
} else {
return (IXGBE_FAILURE);
}
}
/*
* Setup adapter interrupt vectors
*/
/*
* Initialize unicast addresses.
*/
/*
* Setup and initialize the mctable structures.
*/
/*
* Set interrupt throttling rate
*/
}
/*
* Save the state of the phy
*/
/*
* Make sure driver has control
*/
return (IXGBE_SUCCESS);
}
/*
* ixgbe_chip_stop - Stop the chipset hardware
*/
static void
{
/*
* Tell firmware driver is no longer in control
*/
/*
* Reset the chipset
*/
(void) ixgbe_reset_hw(hw);
/*
* Reset PHY
*/
(void) ixgbe_reset_phy(hw);
}
/*
* ixgbe_reset - Reset the chipset and re-start the driver.
*
* It involves stopping and re-starting the chipset,
*/
static int
{
int i;
/*
* Disable and stop the watchdog timer
*/
return (IXGBE_FAILURE);
}
/*
* After resetting, need to recheck the link status.
*/
(IXGBE_LINK_UP_TIME * 100000000ULL);
for (i = 0; i < ixgbe->num_tx_rings; i++) {
}
}
/*
* Enable and start the watchdog timer
*/
return (IXGBE_SUCCESS);
}
/*
* ixgbe_tx_clean - Clean the pending transmit packets and DMA resources.
*/
static void
{
int i, j;
for (i = 0; i < ixgbe->num_tx_rings; i++) {
/*
* Clean the pending tx data - the pending packets in the
* work_list that have no chances to be transmitted again.
*
* We must ensure the chipset is stopped or the link is down
* before cleaning the transmit packets.
*/
desc_num = 0;
}
}
if (desc_num > 0) {
/*
* Reset the head and tail pointers of the tbd ring;
* Reset the writeback head if it's enable.
*/
if (ixgbe->tx_head_wb_enable)
*tx_ring->tbd_head_wb = 0;
}
/*
* Add the tx control blocks in the pending list to
* the free list.
*/
}
}
/*
* ixgbe_tx_drain - Drain the tx rings to allow pending packets to be
* transmitted.
*/
static boolean_t
{
int i, j;
/*
* Wait for a specific time to allow pending tx packets
* to be transmitted.
*
* Check the counter tbd_free to see if transmission is done.
* No lock protection is needed here.
*
* Return B_TRUE if all pending packets have been transmitted;
* Otherwise return B_FALSE;
*/
for (i = 0; i < TX_DRAIN_TIME; i++) {
for (j = 0; j < ixgbe->num_tx_rings; j++) {
}
if (done)
break;
msec_delay(1);
}
return (done);
}
/*
* ixgbe_rx_drain - Wait for all rx buffers to be released by upper layer.
*/
static boolean_t
{
int i;
/*
* Polling the rx free list to check if those rx buffers held by
* the upper layer are released.
*
* Check the counter rcb_free to see if all pending buffers are
* released. No lock protection is needed here.
*
* Return B_TRUE if all pending buffers have been released;
* Otherwise return B_FALSE;
*/
for (i = 0; i < RX_DRAIN_TIME; i++) {
if (done)
break;
msec_delay(1);
}
return (done);
}
/*
*/
int
{
int i;
if (alloc_buffer) {
"Failed to allocate software receive rings");
return (IXGBE_FAILURE);
}
return (IXGBE_FAILURE);
}
} else {
}
for (i = 0; i < ixgbe->num_rx_rings; i++)
for (i = 0; i < ixgbe->num_tx_rings; i++)
/*
* Start the chipset hardware
*/
goto start_failure;
}
goto start_failure;
}
/*
*/
/*
* ixgbe_start() will be called when resetting, however if reset
* happens, we need to clear the ERROR and STALL flags before
* enabling the interrupts.
*/
/*
* Enable adapter interrupts
* The interrupts must be enabled after the driver state is START
*/
return (IXGBE_SUCCESS);
return (IXGBE_FAILURE);
}
/*
*/
void
{
int i;
/*
* Disable the adapter interrupts
*/
/*
* Drain the pending tx packets
*/
(void) ixgbe_tx_drain(ixgbe);
for (i = 0; i < ixgbe->num_rx_rings; i++)
for (i = 0; i < ixgbe->num_tx_rings; i++)
/*
* Stop the chipset hardware
*/
}
/*
*/
}
if (free_buffer) {
/*
*/
}
}
/*
*/
static int
{
/*
* Allocate memory space for rx rings
*/
return (IXGBE_FAILURE);
}
/*
* Allocate memory space for tx rings
*/
return (IXGBE_FAILURE);
}
/*
* Allocate memory space for rx ring groups
*/
return (IXGBE_FAILURE);
}
return (IXGBE_SUCCESS);
}
/*
*/
static void
{
}
}
}
}
static int
{
int i;
for (i = 0; i < ixgbe->num_rx_rings; i++) {
goto alloc_rx_rings_failure;
}
return (IXGBE_SUCCESS);
return (IXGBE_FAILURE);
}
static void
{
int i;
for (i = 0; i < ixgbe->num_rx_rings; i++) {
if (rx_data->rcb_pending == 0) {
}
}
}
}
/*
*/
static void
{
/*
*
* 1. Setup the descriptor ring and the control block buffers;
* 3. Initialize software pointers/parameters for receive/transmit;
*/
}
static void
{
union ixgbe_adv_rx_desc *rbd;
int i;
for (i = 0; i < ixgbe->rx_ring_size; i++) {
}
/*
* Initialize the length register
*/
/*
* Initialize the base address registers
*/
/*
* Setup head & tail pointers
*/
/*
* Setup the Receive Descriptor Control Register (RXDCTL)
* PTHRESH=32 descriptors (half the internal cache)
* HTHRESH=0 descriptors (to minimize latency on fetch)
* WTHRESH defaults to 1 (writeback each descriptor)
*/
/* Not a valid value for 82599 */
}
}
/*
* Setup the Split and Replication Receive Control Register.
* Set the rx buffer size and the advanced descriptor type.
*/
}
static void
{
int i;
/* PSRTYPE must be configured for 82599 */
#define IXGBE_PSRTYPE_L2_PKT 0x00001000
reg_val |= 0xE0000000;
/*
* Set filter control in FCTRL to accept broadcast packets and do
* not pass pause frames to host. Flow control settings are already
* in this register, so preserve them.
*/
/*
* Enable the receive unit. This must be done after filter
* control is set in FCTRL.
*/
| IXGBE_RXCTRL_DMBYPS); /* descriptor monitor bypass */
/*
* ixgbe_setup_rx_ring must be called after configuring RXCTRL
*/
for (i = 0; i < ixgbe->num_rx_rings; i++) {
}
/*
* Setup rx groups.
*/
for (i = 0; i < ixgbe->num_rx_groups; i++) {
}
/*
* Setup the per-ring statistics mapping.
*/
ring_mapping = 0;
for (i = 0; i < ixgbe->num_rx_rings; i++) {
if ((i & 0x3) == 0x3) {
ring_mapping = 0;
}
}
if ((i & 0x3) != 0x3)
/*
* by four bytes if the packet has a VLAN field, so includes MTU,
* ethernet header and frame check sequence.
* Register is MAXFRS in 82599.
*/
+ ETHERFCSL) << IXGBE_MHADD_MFS_SHIFT;
/*
* Setup Jumbo Frame enable bit
*/
}
/*
* Hardware checksum settings
*/
if (ixgbe->rx_hcksum_enable) {
}
/*
* Setup RSS for multiple receive queues
*/
}
static void
{
/*
* Initialize the length register
*/
/*
* Initialize the base address registers
*/
/*
* Setup head & tail pointers
*/
/*
* Setup head write-back
*/
if (ixgbe->tx_head_wb_enable) {
/*
* The memory of the head write-back is allocated using
* the extra tbd beyond the tail of the tbd ring.
*/
*tx_ring->tbd_head_wb = 0;
/* Set the head write-back enable bit */
/*
* Turn off relaxed ordering for head write back or it will
* cause problems with the tx recycling
*/
} else {
}
}
/*
* Initialize the s/w context structure
*/
}
static void
{
int i;
for (i = 0; i < ixgbe->num_tx_rings; i++) {
}
/*
* Setup the per-ring statistics mapping.
*/
ring_mapping = 0;
for (i = 0; i < ixgbe->num_tx_rings; i++) {
if ((i & 0x3) == 0x3) {
} else {
}
ring_mapping = 0;
}
}
if ((i & 0x3) != 0x3)
} else {
}
/*
* Enable CRC appending and TX padding (for short tx frames)
*/
/*
* enable DMA for 82599 parts
*/
/* DMATXCTL.TE must be set after all Tx config is complete */
}
/*
* Enabling tx queues ..
* For 82599 must be done after DMATXCTL.TE is set
*/
for (i = 0; i < ixgbe->num_tx_rings; i++) {
}
}
/*
* ixgbe_setup_rss - Setup receive-side scaling feature.
*/
static void
{
/*
* Fill out redirection table
*/
reta = 0;
for (i = 0; i < 128; i++) {
if ((i & 3) == 3)
}
/*
* Fill out hash function seeds with a random constant
*/
for (i = 0; i < 10; i++) {
sizeof (uint32_t));
}
/*
* Enable RSS & perform hash on these packet types
*/
mrqc = IXGBE_MRQC_RSSEN |
/*
* Disable Packet Checksum to enable RSS for multiple receive queues.
* It is an adapter hardware limitation that Packet Checksum is
* mutually exclusive with RSS.
*/
}
/*
* ixgbe_init_unicst - Initialize the unicast addresses.
*/
static void
{
int slot;
/*
* Here we should consider two situations:
*
* 1. Chipset is initialized at the first time,
* Clear all the multiple unicast addresses.
*
* 2. Chipset is reset
* Recover the multiple unicast addresses from the
* software data structure to the RAR registers.
*/
if (!ixgbe->unicst_init) {
/*
* Initialize the multiple unicast addresses
*/
}
} else {
/* Re-configure the RAR registers */
NULL, IXGBE_RAH_AV);
} else {
}
}
}
}
/*
* ixgbe_unicst_set - Set the unicast address to the specified slot.
*/
int
int slot)
{
/*
* Save the unicast address in the software data structure
*/
/*
* Set the unicast address to the RAR register
*/
return (EIO);
}
return (0);
}
/*
* ixgbe_unicst_find - Find the slot for the specified unicast address
*/
int
{
int slot;
mac_addr, ETHERADDRL) == 0)
return (slot);
}
return (-1);
}
/*
* ixgbe_multicst_add - Add a multicst address.
*/
int
{
if ((multiaddr[0] & 01) == 0) {
return (EINVAL);
}
return (ENOENT);
}
ixgbe->mcast_count++;
/*
* Update the multicast table in the hardware
*/
return (EIO);
}
return (0);
}
/*
* ixgbe_multicst_remove - Remove a multicst address.
*/
int
{
int i;
for (i = 0; i < ixgbe->mcast_count; i++) {
ETHERADDRL) == 0) {
for (i++; i < ixgbe->mcast_count; i++) {
ixgbe->mcast_table[i];
}
ixgbe->mcast_count--;
break;
}
}
/*
* Update the multicast table in the hardware
*/
return (EIO);
}
return (0);
}
/*
* ixgbe_setup_multicast - Setup multicast data structures.
*
* This routine initializes all of the multicast related structures
* and save them in the hardware registers.
*/
static void
{
/*
* Update the multicast addresses to the MTA registers
*/
}
/*
* ixgbe_get_conf - Get driver configurations set in driver.conf.
*
* This routine gets user-configured values out of the configuration
* file ixgbe.conf.
*
* For each configurable value, there is a minimum, a maximum, and a
* default.
* If user does not configure a value, use the default.
* If user configures below the minimum, use the minumum.
* If user configures above the maximum, use the maxumum.
*/
static void
{
/*
* ixgbe driver supports the following user configurations:
*
* Jumbo frame configuration:
* default_mtu
*
* Ethernet flow control configuration:
* flow_control
*
* Multiple rings configurations:
* tx_queue_number
* tx_ring_size
* rx_queue_number
* rx_ring_size
*
* Call ixgbe_get_prop() to get the value for a specific
* configuration parameter.
*/
/*
* Jumbo frame configuration - max_frame_size controls host buffer
* allocation, so includes MTU, ethernet header, vlan tag and
* frame check sequence.
*/
sizeof (struct ether_vlan_header) + ETHERFCSL;
/*
* Ethernet flow control configuration
*/
if (flow_control == 3)
/*
* fc.requested mode is what the user requests. After autoneg,
* fc.current_mode will be the flow_control mode that was negotiated.
*/
/*
* Multiple rings configurations
*/
/*
* Multiple groups configuration
*/
0, 1, DEFAULT_MR_ENABLE);
}
/*
* Tunable used to force an interrupt type. The only use is
* for testing of the lesser interrupt types.
* 0 = don't force interrupt type
* 1 = force interrupt type MSI-X
* 2 = force interrupt type MSI
* 3 = force interrupt type Legacy
*/
0, 1, DEFAULT_TX_HCKSUM_ENABLE);
0, 1, DEFAULT_RX_HCKSUM_ENABLE);
0, 1, DEFAULT_LSO_ENABLE);
0, 1, DEFAULT_TX_HEAD_WB_ENABLE);
/* Head Write Back not recommended for 82599 */
}
/*
* ixgbe LSO needs the tx h/w checksum support.
* LSO will be disabled if tx h/w checksum is not
* enabled.
*/
}
/*
* 82599 requires the interupt throttling rate is
* a multiple of 8. This is enforced by the register
* definiton.
*/
}
static void
{
ixgbe->param_rem_fault = 0;
ixgbe->param_adv_rem_fault = 0;
ixgbe->param_lp_10000fdx_cap = 0;
ixgbe->param_lp_1000fdx_cap = 0;
ixgbe->param_lp_100fdx_cap = 0;
ixgbe->param_lp_autoneg_cap = 0;
ixgbe->param_lp_pause_cap = 0;
ixgbe->param_lp_asym_pause_cap = 0;
ixgbe->param_lp_rem_fault = 0;
}
/*
* ixgbe_get_prop - Get a property value out of the configuration file
* ixgbe.conf.
*
* Caller provides the name of the property, a default value, a minimum
* value, and a maximum value.
*
* Return configured value of the property, with default, minimum and
* maximum properly applied.
*/
static int
char *propname, /* name of the property */
int minval, /* minimum acceptable value */
int maxval, /* maximim acceptable value */
int defval) /* default value */
{
int value;
/*
* Call ddi_prop_get_int() to read the conf settings
*/
return (value);
}
/*
* ixgbe_driver_setup_link - Using the link properties to setup the link.
*/
int
{
u32 autoneg_advertised = 0;
/*
* No half duplex support with 10Gb parts
*/
"to autonegotiation with full link capabilities.");
}
if (setup_hw) {
"device.");
return (IXGBE_FAILURE);
}
}
return (IXGBE_SUCCESS);
}
/*
* ixgbe_driver_link_check - Link status processing.
*
* This function can be called in both kernel context and interrupt context
*/
static void
{
if (link_up) {
/* Link is up, enable flow control settings */
(void) ixgbe_fc_enable(hw, 0);
/*
* The Link is up, check whether it was marked as down earlier
*/
switch (speed) {
break;
break;
}
ixgbe->link_down_timeout = 0;
}
} else {
/*
* The link is really down
*/
ixgbe->link_speed = 0;
}
if (ixgbe->link_down_timeout <
} else if (ixgbe->link_down_timeout ==
}
}
}
}
/*
* this is only reached after a link-status-change interrupt
* so always get new phy state
*/
/*
* If we are in an interrupt context, need to re-enable the
* interrupt, which was automasked
*/
if (servicing_interrupt() != 0) {
}
if (link_changed) {
}
}
/*
* ixgbe_sfp_check - sfp module processing done in taskq only for 82599.
*/
static void
ixgbe_sfp_check(void *arg)
{
if (eicr & IXGBE_EICR_GPI_SDP1) {
/* clear the interrupt */
/* if link up, do multispeed fiber setup */
} else if (eicr & IXGBE_EICR_GPI_SDP2) {
/* clear the interrupt */
/* if link up, do sfp module setup */
/* do multispeed fiber setup */
}
}
/*
* ixgbe_link_timer - timer for link status detection
*/
static void
ixgbe_link_timer(void *arg)
{
}
/*
* ixgbe_local_timer - Driver watchdog function.
*
* This function will handle the transmit stall check and other routines.
*/
static void
ixgbe_local_timer(void *arg)
{
ixgbe->reset_count++;
return;
}
if (ixgbe_stall_check(ixgbe)) {
ixgbe->reset_count++;
}
}
/*
* ixgbe_stall_check - Check for transmit stall.
*
* This function checks if the adapter is stalled (in transmit).
*
* It is called each time the watchdog timeout is invoked.
* If the transmit descriptor reclaim continuously fails,
* the watchdog value will increment by 1. If the watchdog
* value exceeds the threshold, the ixgbe is assumed to
* have stalled and need to be reset.
*/
static boolean_t
{
int i;
return (B_FALSE);
/*
* If any tx ring is stalled, we'll reset the chipset
*/
for (i = 0; i < ixgbe->num_tx_rings; i++) {
}
if (tx_ring->recycle_fail > 0)
else
tx_ring->stall_watchdog = 0;
break;
}
}
if (result) {
tx_ring->stall_watchdog = 0;
tx_ring->recycle_fail = 0;
}
return (result);
}
/*
* is_valid_mac_addr - Check if the mac address is valid.
*/
static boolean_t
{
{ 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF };
return (B_FALSE);
return (B_TRUE);
}
static boolean_t
{
#ifdef __sparc
struct ether_addr sysaddr;
int err;
/*
* The "vendor's factory-set address" may already have
* been extracted from the chip, but if the property
* "local-mac-address" is set we use that instead.
*
* We check whether it looks like an array of 6
* bytes (which it should, if OBP set it). If we can't
* make sense of it this way, we'll ignore it.
*/
if (err == DDI_PROP_SUCCESS) {
if (nelts == ETHERADDRL) {
while (nelts--)
}
}
/*
* Look up the OBP property "local-mac-address?". If the user has set
* 'local-mac-address? = false', use "the system address" instead.
*/
}
}
}
/*
* Finally(!), if there's a valid "mac-address" property (created
* if we netbooted from this interface), we must use this instead
* get confused by the address changing as Solaris takes over!
*/
if (err == DDI_PROP_SUCCESS) {
if (nelts == ETHERADDRL) {
while (nelts--)
}
}
if (found) {
return (B_TRUE);
}
#else
#endif
return (B_TRUE);
}
#pragma inline(ixgbe_arm_watchdog_timer)
static void
{
/*
* Fire a watchdog timer
*/
}
/*
* ixgbe_enable_watchdog_timer - Enable and start the driver watchdog timer.
*/
void
{
if (!ixgbe->watchdog_enable) {
}
}
/*
* ixgbe_disable_watchdog_timer - Disable and stop the driver watchdog timer.
*/
void
{
ixgbe->watchdog_tid = 0;
if (tid != 0)
}
/*
* ixgbe_start_watchdog_timer - Start the driver watchdog timer.
*/
void
{
if (ixgbe->watchdog_enable) {
if (!ixgbe->watchdog_start) {
}
}
}
/*
* ixgbe_restart_watchdog_timer - Restart the driver watchdog timer.
*/
static void
{
if (ixgbe->watchdog_start)
}
/*
* ixgbe_stop_watchdog_timer - Stop the driver watchdog timer.
*/
void
{
ixgbe->watchdog_tid = 0;
if (tid != 0)
}
/*
* ixgbe_disable_adapter_interrupts - Disable all adapter interrupts.
*/
static void
{
/*
* mask all interrupts off
*/
/*
* for MSI-X, also disable autoclear
*/
}
}
/*
* ixgbe_enable_adapter_interrupts - Enable all hardware interrupts.
*/
static void
{
/* interrupt types to enable */
/* enable automask on "other" causes that this adapter can generate */
/*
* msi-x mode
*/
/* enable autoclear but not on bits 29:20 */
/* general purpose interrupt enable */
| IXGBE_GPIE_EIAME);
/*
* non-msi-x mode
*/
} else {
/* disable autoclear, leave gpie at default */
eiac = 0;
/*
* General purpose interrupt enable.
* For 82599, extended interrupt automask enable
* only in MSI or MSI-X mode
*/
gpie |= IXGBE_GPIE_EIAME;
}
}
/* Enable specific interrupts for 82599 */
}
/* write to interrupt control registers */
}
/*
* ixgbe_loopback_ioctl - Loopback support.
*/
enum ioc_reply
{
return (IOC_INVAL);
default:
return (IOC_INVAL);
case LB_GET_INFO_SIZE:
size = sizeof (lb_info_sz_t);
return (IOC_INVAL);
value += sizeof (lb_external);
break;
case LB_GET_INFO:
value += sizeof (lb_external);
return (IOC_INVAL);
value = 0;
break;
case LB_GET_MODE:
return (IOC_INVAL);
break;
case LB_SET_MODE:
size = 0;
return (IOC_INVAL);
return (IOC_INVAL);
break;
}
return (IOC_INVAL);
}
return (IOC_REPLY);
}
/*
* ixgbe_set_loopback_mode - Setup loopback based on the loopback mode.
*/
static boolean_t
{
return (B_TRUE);
if (mode == IXGBE_LB_NONE) {
/*
* Reset the chip
*/
(void) ixgbe_reset(ixgbe);
return (B_TRUE);
}
switch (mode) {
default:
return (B_FALSE);
case IXGBE_LB_EXTERNAL:
break;
case IXGBE_LB_INTERNAL_MAC:
break;
}
return (B_TRUE);
}
/*
* ixgbe_set_internal_mac_loopback - Set the internal MAC loopback mode.
*/
static void
{
/*
* Setup MAC loopback
*/
reg |= IXGBE_HLREG0_LPBK;
reg &= ~IXGBE_AUTOC_LMS_MASK;
/*
* Disable Atlas Tx lanes to keep packets in loopback and not on wire
*/
&atlas);
atlas);
&atlas);
atlas);
&atlas);
atlas);
&atlas);
atlas);
}
}
#pragma inline(ixgbe_intr_rx_work)
/*
* ixgbe_intr_rx_work - RX processing of ISR.
*/
static void
{
}
#pragma inline(ixgbe_intr_tx_work)
/*
* ixgbe_intr_tx_work - TX processing of ISR.
*/
static void
{
/*
* Recycle the tx descriptors
*/
/*
* Schedule the re-transmit
*/
if (tx_ring->reschedule &&
}
}
#pragma inline(ixgbe_intr_other_work)
/*
*/
static void
{
/*
* handle link status change
*/
if (eicr & IXGBE_EICR_LSC) {
}
/*
* check for fan failure on adapters with fans
*/
(eicr & IXGBE_EICR_GPI_SDP1)) {
"Fan has stopped, replace the adapter\n");
/* re-enable the interrupt, which was automasked */
}
}
/*
* Do SFP check for 82599
*/
ixgbe_sfp_check, (void *)ixgbe,
DDI_NOSLEEP)) != DDI_SUCCESS) {
"taskq for SFP check");
}
/*
* We need to fully re-check the link later.
*/
(IXGBE_LINK_UP_TIME * 100000000ULL);
}
}
/*
* ixgbe_intr_legacy - Interrupt handler for legacy interrupts.
*/
static uint_t
{
return (DDI_INTR_UNCLAIMED);
}
/*
* Any bit set in eicr: claim this interrupt
*/
return (DDI_INTR_CLAIMED);
}
if (eicr) {
/*
* For legacy interrupt, we have only one interrupt,
* so we have only one rx ring and one tx ring enabled.
*/
/*
* For legacy interrupt, rx rings[0] will use RTxQ[0].
*/
if (eicr & 0x1) {
/*
* Clean the rx descriptors
*/
}
/*
* For legacy interrupt, tx rings[0] will use RTxQ[1].
*/
if (eicr & 0x2) {
/*
* Recycle the tx descriptors
*/
/*
* Schedule the re-transmit
*/
}
}
}
}
} else {
/*
* No interrupt cause bits set: don't claim this interrupt.
*/
}
/* re-enable the interrupts which were automasked */
/*
* Do the following work outside of the gen_lock
*/
}
if (tx_reschedule) {
}
return (result);
}
/*
* ixgbe_intr_msi - Interrupt handler for MSI.
*/
static uint_t
{
return (DDI_INTR_CLAIMED);
}
/*
* For MSI interrupt, we have only one vector,
* so we have only one rx ring and one tx ring enabled.
*/
/*
* For MSI interrupt, rx rings[0] will use RTxQ[0].
*/
if (eicr & 0x1) {
}
/*
* For MSI interrupt, tx rings[0] will use RTxQ[1].
*/
if (eicr & 0x2) {
}
}
}
}
/* re-enable the interrupts which were automasked */
return (DDI_INTR_CLAIMED);
}
/*
* ixgbe_intr_msix - Interrupt handler for MSI-X.
*/
static uint_t
{
int r_idx = 0;
/*
* Clean each rx ring that has its bit set in the map
*/
while (r_idx >= 0) {
}
/*
* Clean each tx ring that has its bit set in the map
*/
while (r_idx >= 0) {
}
/*
* Clean other interrupt (link change) that has its bit set in the map
*/
DDI_FM_OK) {
return (DDI_INTR_CLAIMED);
}
/*
* Need check cause bits and only other causes will
* be processed
*/
} else {
}
}
}
/* re-enable the interrupts which were automasked */
}
return (DDI_INTR_CLAIMED);
}
/*
* ixgbe_alloc_intrs - Allocate interrupts for the driver.
*
* Normal sequence is to try MSI-X; if not sucessful, try MSI;
* if not successful, try Legacy.
* ixgbe->intr_force can be used to force sequence to start with
* any of the 3 types.
*/
static int
{
int intr_types;
int rc;
/*
* Get supported interrupt types
*/
if (rc != DDI_SUCCESS) {
"Get supported interrupt types failed: %d", rc);
return (IXGBE_FAILURE);
}
/*
* Install MSI-X interrupts
*/
if ((intr_types & DDI_INTR_TYPE_MSIX) &&
if (rc == IXGBE_SUCCESS)
return (IXGBE_SUCCESS);
"Allocate MSI-X failed, trying MSI interrupts...");
}
/*
* MSI-X not used, force rings and groups to 1
*/
"MSI-X not used, force rings and groups number to 1");
/*
* Install MSI interrupts
*/
if ((intr_types & DDI_INTR_TYPE_MSI) &&
if (rc == IXGBE_SUCCESS)
return (IXGBE_SUCCESS);
"Allocate MSI failed, trying Legacy interrupts...");
}
/*
* Install legacy interrupts
*/
if (intr_types & DDI_INTR_TYPE_FIXED) {
if (rc == IXGBE_SUCCESS)
return (IXGBE_SUCCESS);
"Allocate Legacy interrupts failed");
}
/*
* If none of the 3 types succeeded, return failure
*/
return (IXGBE_FAILURE);
}
/*
* ixgbe_alloc_intr_handles - Allocate interrupt handles.
*
* For legacy and MSI, only 1 handle is needed. For MSI-X,
* if fewer than 2 handles are available, return failure.
* Upon success, this maps the vectors to rx and tx rings for
* interrupts.
*/
static int
{
int minimum;
int rc;
switch (intr_type) {
case DDI_INTR_TYPE_FIXED:
minimum = 1;
break;
case DDI_INTR_TYPE_MSI:
minimum = 1;
break;
case DDI_INTR_TYPE_MSIX:
/*
* Best number of vectors for the adapter is
* # rx rings + # tx rings.
*/
minimum = 2;
break;
default:
"invalid call to ixgbe_alloc_intr_handles(): %d\n",
return (IXGBE_FAILURE);
}
/*
* Get number of supported interrupts
*/
"Get interrupt number failed. Return: %d, count: %d",
return (IXGBE_FAILURE);
}
/*
* Get number of available interrupts
*/
"Get interrupt available number failed. "
return (IXGBE_FAILURE);
}
}
actual = 0;
/*
* Allocate an array of interrupt handles
*/
if (rc != DDI_SUCCESS) {
"return: %d, request: %d, actual: %d",
goto alloc_handle_fail;
}
/*
* Now we know the actual number of vectors. Here we map the vector
* to other, rx rings and tx ring.
*/
actual);
goto alloc_handle_fail;
}
/*
* Get priority for first vector, assume remaining are all the same
*/
if (rc != DDI_SUCCESS) {
"Get interrupt priority failed: %d", rc);
goto alloc_handle_fail;
}
if (rc != DDI_SUCCESS) {
"Get interrupt cap failed: %d", rc);
goto alloc_handle_fail;
}
return (IXGBE_SUCCESS);
return (IXGBE_FAILURE);
}
/*
* ixgbe_add_intr_handlers - Add interrupt handlers based on the interrupt type.
*
* Before adding the interrupt handlers, the interrupt vectors have
*/
static int
{
int vector = 0;
int rc;
case DDI_INTR_TYPE_MSIX:
/*
* Add interrupt handler for all vectors
*/
/*
* install pointer to vect_map[vector]
*/
if (rc != DDI_SUCCESS) {
"Add rx interrupt handler failed. "
(void) ddi_intr_remove_handler(
}
return (IXGBE_FAILURE);
}
}
break;
case DDI_INTR_TYPE_MSI:
/*
* Add interrupt handlers for the only vector
*/
if (rc != DDI_SUCCESS) {
"Add MSI interrupt handler failed: %d", rc);
return (IXGBE_FAILURE);
}
break;
case DDI_INTR_TYPE_FIXED:
/*
* Add interrupt handlers for the only vector
*/
if (rc != DDI_SUCCESS) {
"Add legacy interrupt handler failed: %d", rc);
return (IXGBE_FAILURE);
}
break;
default:
return (IXGBE_FAILURE);
}
return (IXGBE_SUCCESS);
}
#pragma inline(ixgbe_map_rxring_to_vector)
/*
* ixgbe_map_rxring_to_vector - Map given rx ring to given interrupt vector.
*/
static void
{
/*
* Set bit in map
*/
/*
* Count bits set
*/
/*
* Remember bit position
*/
}
#pragma inline(ixgbe_map_txring_to_vector)
/*
* ixgbe_map_txring_to_vector - Map given tx ring to given interrupt vector.
*/
static void
{
/*
* Set bit in map
*/
/*
* Count bits set
*/
/*
* Remember bit position
*/
}
/*
* ixgbe_setup_ivar - Set the given entry in the given interrupt vector
* allocation register (IVAR).
* cause:
* -1 : other cause
* 0 : rx
* 1 : tx
*/
static void
{
case ixgbe_mac_82598EB:
if (cause == -1) {
cause = 0;
}
break;
case ixgbe_mac_82599EB:
if (cause == -1) {
/* other causes */
} else {
/* tx or rx causes */
ivar);
}
break;
default:
break;
}
}
/*
* ixgbe_enable_ivar - Enable the given entry by setting the VAL bit of
* given interrupt vector allocation register (IVAR).
* cause:
* -1 : other cause
* 0 : rx
* 1 : tx
*/
static void
{
case ixgbe_mac_82598EB:
if (cause == -1) {
cause = 0;
}
(intr_alloc_entry & 0x3)));
break;
case ixgbe_mac_82599EB:
if (cause == -1) {
/* other causes */
} else {
/* tx or rx causes */
ivar);
}
break;
default:
break;
}
}
/*
* ixgbe_disable_ivar - Disble the given entry by clearing the VAL bit of
* given interrupt vector allocation register (IVAR).
* cause:
* -1 : other cause
* 0 : rx
* 1 : tx
*/
static void
{
case ixgbe_mac_82598EB:
if (cause == -1) {
cause = 0;
}
(intr_alloc_entry & 0x3)));
break;
case ixgbe_mac_82599EB:
if (cause == -1) {
/* other causes */
} else {
/* tx or rx causes */
ivar);
}
break;
default:
break;
}
}
/*
* ixgbe_map_intrs_to_vectors - Map different interrupts to MSI-X vectors.
*
* For MSI-X, here will map rx interrupt, tx interrupt and other interrupt
* to vector[0 - (intr_cnt -1)].
*/
static int
{
int i, vector = 0;
/* initialize vector map */
}
/*
* non-MSI-X case is very simple: rx rings[0] on RTxQ[0],
* tx rings[0] on RTxQ[1].
*/
ixgbe_map_rxring_to_vector(ixgbe, 0, 0);
return (IXGBE_SUCCESS);
}
/*
* Interrupts/vectors mapping for MSI-X
*/
/*
* Map other interrupt to vector 0,
* Set bit in map and count the bits set.
*/
vector++;
/*
* Map rx ring interrupts to vectors
*/
for (i = 0; i < ixgbe->num_rx_rings; i++) {
}
/*
* Map tx ring interrupts to vectors
*/
for (i = 0; i < ixgbe->num_tx_rings; i++) {
}
return (IXGBE_SUCCESS);
}
/*
* ixgbe_setup_adapter_vector - Setup the adapter interrupt vector(s).
*
* vect_map[] structures
*/
static void
{
int r_idx; /* ring index */
int v_idx; /* vector index */
/*
* Clear any previous entries
*/
case ixgbe_mac_82598EB:
break;
case ixgbe_mac_82599EB:
break;
default:
break;
}
/*
* For non MSI-X interrupt, rx rings[0] will use RTxQ[0], and
* tx rings[0] will use RTxQ[1].
*/
ixgbe_setup_ivar(ixgbe, 0, 0, 0);
return;
}
/*
* For MSI-X interrupt, "Other" is always on vector[0].
*/
/*
* For each interrupt vector, populate the IVAR table
*/
/*
* For each rx ring bit set
*/
while (r_idx >= 0) {
}
/*
* For each tx ring bit set
*/
while (r_idx >= 0) {
}
}
}
/*
* ixgbe_rem_intr_handlers - Remove the interrupt handlers.
*/
static void
{
int i;
int rc;
if (rc != DDI_SUCCESS) {
"Remove intr handler failed: %d", rc);
}
}
}
/*
* ixgbe_rem_intrs - Remove the allocated interrupts.
*/
static void
{
int i;
int rc;
if (rc != DDI_SUCCESS) {
"Free intr failed: %d", rc);
}
}
}
/*
* ixgbe_enable_intrs - Enable all the ddi interrupts.
*/
static int
{
int i;
int rc;
/*
* Enable interrupts
*/
/*
* Call ddi_intr_block_enable() for MSI
*/
if (rc != DDI_SUCCESS) {
"Enable block intr failed: %d", rc);
return (IXGBE_FAILURE);
}
} else {
/*
*/
if (rc != DDI_SUCCESS) {
"Enable intr failed: %d", rc);
return (IXGBE_FAILURE);
}
}
}
return (IXGBE_SUCCESS);
}
/*
* ixgbe_disable_intrs - Disable all the interrupts.
*/
static int
{
int i;
int rc;
/*
* Disable all interrupts
*/
if (rc != DDI_SUCCESS) {
"Disable block intr failed: %d", rc);
return (IXGBE_FAILURE);
}
} else {
if (rc != DDI_SUCCESS) {
"Disable intr failed: %d", rc);
return (IXGBE_FAILURE);
}
}
}
return (IXGBE_SUCCESS);
}
/*
* ixgbe_get_hw_state - Get and save parameters related to adapter hardware.
*/
static void
{
uint32_t pcs1g_anlp = 0;
ixgbe->param_lp_1000fdx_cap = 0;
ixgbe->param_lp_100fdx_cap = 0;
/* check for link, don't wait */
if (link_up) {
}
}
/*
* ixgbe_get_driver_control - Notify that driver is in control of device.
*/
static void
{
/*
* Notify firmware that driver is in control of device
*/
}
/*
* ixgbe_release_driver_control - Notify that driver is no longer in control
* of device.
*/
static void
{
/*
* Notify firmware that driver is no longer in control of device
*/
}
/*
* ixgbe_atomic_reserve - Atomic decrease operation.
*/
int
{
/*
* ATOMICALLY
*/
do {
if (oldval < n)
return (-1);
return (newval);
}
/*
* ixgbe_mc_table_itr - Traverse the entries in the multicast table.
*/
static uint8_t *
{
return (addr);
}
/*
* FMA support
*/
int
{
return (de.fme_status);
}
int
{
return (de.fme_status);
}
/*
* ixgbe_fm_error_cb - The IO fault service error handling callback function.
*/
static int
{
/*
* as the driver can always deal with an error in any dma or
* access handle, we can just return the fme_status value.
*/
return (err->fme_status);
}
static void
{
int fma_dma_flag;
/*
* Only register with IO Fault Services if we have some capability
*/
} else {
}
fma_dma_flag = 1;
} else {
fma_dma_flag = 0;
}
if (ixgbe->fm_capabilities) {
/*
* Register capabilities with IO Fault Services
*/
/*
* Initialize pci ereport capabilities if ereport capable
*/
/*
* Register error callback if error callback capable
*/
ixgbe_fm_error_cb, (void*) ixgbe);
}
}
static void
{
/*
* Only unregister FMA capabilities if they are registered
*/
if (ixgbe->fm_capabilities) {
/*
* Release any resources allocated by pci_ereport_setup()
*/
/*
* Un-register error callback if error callback capable
*/
/*
* Unregister from IO Fault Service
*/
}
}
void
{
char buf[FM_MAX_CLASS];
}
}
static int
{
return (0);
}
/*
* Callback funtion for MAC layer to register all rings.
*/
/* ARGSUSED */
void
{
switch (rtype) {
case MAC_RING_TYPE_RX: {
break;
}
case MAC_RING_TYPE_TX: {
break;
}
default:
break;
}
}
/*
* Callback funtion for MAC layer to register all groups.
*/
void
{
switch (rtype) {
case MAC_RING_TYPE_RX: {
break;
}
case MAC_RING_TYPE_TX:
break;
default:
break;
}
}
/*
* Enable interrupt on the specificed rx ring.
*/
int
{
/*
* To enable interrupt by setting the VAL bit of given interrupt
* vector allocation register (IVAR).
*/
/*
* To trigger a Rx interrupt to on this ring
*/
return (0);
}
/*
* Disable interrupt on the specificed rx ring.
*/
int
{
/*
* To disable interrupt by clearing the VAL bit of given interrupt
* vector allocation register (IVAR).
*/
return (0);
}
/*
* Add a mac address.
*/
static int
{
int slot;
int err;
return (ECANCELED);
}
if (ixgbe->unicst_avail == 0) {
/* no slots available */
return (ENOSPC);
}
break;
}
ixgbe->unicst_avail--;
}
return (err);
}
/*
* Remove a mac address.
*/
static int
{
int slot;
int err;
return (ECANCELED);
}
if (slot == -1) {
return (EINVAL);
}
return (EINVAL);
}
ixgbe->unicst_avail++;
}
return (err);
}