ixgbe_gld.c revision c971fb7ec0a19c6cd00c5614a94c97f953b6e8b1
/*
* CDDL HEADER START
*
* Copyright(c) 2007-2008 Intel Corporation. All rights reserved.
* The contents of this file are subject to the terms of the
* Common Development and Distribution License (the "License").
* You may not use this file except in compliance with the License.
*
* You can obtain a copy of the license at:
* See the License for the specific language governing permissions
* and limitations under the License.
*
* When using or redistributing this file, you may do so under the
* License only. No other modification of this header is permitted.
*
* If applicable, add the following below this CDDL HEADER, with the
* fields enclosed by brackets "[]" replaced with your own identifying
* information: Portions Copyright [yyyy] [name of copyright owner]
*
* CDDL HEADER END
*/
/*
* Copyright 2008 Sun Microsystems, Inc. All rights reserved.
* Use is subject to license terms of the CDDL.
*/
#pragma ident "%Z%%M% %I% %E% SMI"
#include "ixgbe_sw.h"
/*
* Retrieve a value for one of the statistics.
*/
int
{
int i;
return (ECANCELED);
}
switch (stat) {
case MAC_STAT_IFSPEED:
break;
case MAC_STAT_MULTIRCV:
break;
case MAC_STAT_BRDCSTRCV:
break;
case MAC_STAT_MULTIXMT:
break;
case MAC_STAT_BRDCSTXMT:
break;
case MAC_STAT_NORCVBUF:
for (i = 0; i < 8; i++) {
}
break;
case MAC_STAT_IERRORS:
break;
case MAC_STAT_RBYTES:
for (i = 0; i < 16; i++)
break;
case MAC_STAT_IPACKETS:
break;
case MAC_STAT_OPACKETS:
break;
/* RFC 1643 stats */
case ETHER_STAT_FCS_ERRORS:
break;
break;
case ETHER_STAT_MACRCV_ERRORS:
break;
case ETHER_STAT_XCVR_ADDR:
/* The Internal PHY's MDI address for each MAC is 1 */
*val = 1;
break;
case ETHER_STAT_XCVR_ID:
break;
case ETHER_STAT_XCVR_INUSE:
switch (ixgbe->link_speed) {
*val =
break;
break;
default:
break;
}
break;
case ETHER_STAT_CAP_1000FDX:
break;
case ETHER_STAT_CAP_100FDX:
break;
case ETHER_STAT_CAP_ASMPAUSE:
break;
case ETHER_STAT_CAP_PAUSE:
break;
case ETHER_STAT_CAP_AUTONEG:
break;
break;
break;
break;
case ETHER_STAT_ADV_CAP_PAUSE:
break;
break;
break;
case ETHER_STAT_LP_CAP_100FDX:
break;
break;
case ETHER_STAT_LP_CAP_PAUSE:
break;
break;
case ETHER_STAT_LINK_ASMPAUSE:
break;
case ETHER_STAT_LINK_PAUSE:
break;
case ETHER_STAT_LINK_AUTONEG:
break;
case ETHER_STAT_LINK_DUPLEX:
*val = LINK_DUPLEX_FULL;
break;
break;
case ETHER_STAT_CAP_REMFAULT:
break;
case ETHER_STAT_ADV_REMFAULT:
break;
case ETHER_STAT_LP_REMFAULT:
break;
case ETHER_STAT_JABBER_ERRORS:
break;
default:
return (ENOTSUP);
}
return (0);
}
/*
* was in when the interface was registered.
*/
int
ixgbe_m_start(void *arg)
{
return (ECANCELED);
}
return (EIO);
}
/*
* Enable and start the watchdog timer
*/
return (0);
}
/*
* that the interface can be unregistered.
*/
void
ixgbe_m_stop(void *arg)
{
return;
}
/*
* Disable and stop the watchdog timer
*/
}
/*
* Set the promiscuity of the device.
*/
int
{
return (ECANCELED);
}
if (on)
else
return (0);
}
/*
* addresses for which the device will receive packets.
*/
int
{
int result;
return (ECANCELED);
}
return (result);
}
/*
* Set a new device unicast address.
*/
int
{
int result;
return (ECANCELED);
}
/*
* Store the new MAC address.
*/
/*
* Set MAC address in address slot 0, which is the default address.
*/
return (result);
}
/*
* Pass on M_IOCTL messages passed to the DLD, and support
* private IOCTLs for debugging and ndd.
*/
void
{
case LB_GET_INFO_SIZE:
case LB_GET_INFO:
case LB_GET_MODE:
case LB_SET_MODE:
break;
case ND_GET:
case ND_SET:
break;
default:
break;
}
/*
* Decide how to reply
*/
switch (status) {
default:
case IOC_INVAL:
/*
* Error, reply with a NAK and EINVAL or the specified error
*/
break;
case IOC_DONE:
/*
* OK, reply already sent
*/
break;
case IOC_ACK:
/*
* OK, reply with an ACK
*/
break;
case IOC_REPLY:
/*
* OK, send prepared reply as ACK or NAK
*/
break;
}
}
/*
* Find an unused address slot, set the address to it, reserve
* this slot and enable the device to start filtering on the
* new address.
*/
int
{
int err;
return (ECANCELED);
}
return (EINVAL);
}
if (ixgbe->unicst_avail == 0) {
/* no slots available */
return (ENOSPC);
}
/*
* are the multiple MAC addresses. So multiple MAC address 0
* is in slot 1, 1 in slot 2, and so on. So the first multiple
* MAC address resides in slot 1.
*/
break;
}
ixgbe->unicst_avail--;
}
return (err);
}
/*
* Removes a MAC address that was added before.
*/
int
{
int err;
return (ECANCELED);
}
return (EINVAL);
}
/*
* Copy the default address to the passed slot
*/
ixgbe->unicst_avail++;
}
return (err);
}
return (EINVAL);
}
/*
* Modifies the value of an address that has been added before.
* The new address length and the slot number that was returned
* in the call to add should be passed in. mma_flags should be
* set to 0.
* Returns 0 on success.
*/
int
{
int err;
return (ECANCELED);
}
return (EINVAL);
}
return (EINVAL);
}
return (err);
}
return (EINVAL);
}
/*
* Get the MAC address and all other information related to
* the address slot passed in mac_multi_addr_t.
* mma_flags should be set to 0 in the call.
* On return, mma_flags can take the following values:
* 1) MMAC_SLOT_UNUSED
* 2) MMAC_SLOT_USED | MMAC_VENDOR_ADDR
* 3) MMAC_SLOT_UNUSED | MMAC_VENDOR_ADDR
* 4) MMAC_SLOT_USED
*/
int
{
return (ECANCELED);
}
return (EINVAL);
}
} else {
}
return (0);
}
/*
* Obtain the MAC's capabilities and associated data from
* the driver.
*/
{
switch (cap) {
case MAC_CAPAB_HCKSUM: {
/*
* We advertise our capabilities only if tx hcksum offload is
* enabled. On receive, the stack will accept checksummed
* packets anyway, even if we haven't said we can deliver
* them.
*/
if (!ixgbe->tx_hcksum_enable)
return (B_FALSE);
break;
}
case MAC_CAPAB_LSO: {
if (ixgbe->lso_enable) {
break;
} else {
return (B_FALSE);
}
}
case MAC_CAPAB_MULTIADDRESS: {
/*
* The number of MAC addresses made available by
* this capability is one less than the total as
* the primary address in slot 0 is counted in
* the total.
*/
/* No multiple factory addresses, set mma_flag to 0 */
mmacp->maddr_flag = 0;
break;
}
default:
return (B_FALSE);
}
return (B_TRUE);
}