ixgbe_gld.c revision 62e6e1adfc8d795f477410703cc7a88dc5b82622
/*
* CDDL HEADER START
*
* Copyright(c) 2007-2009 Intel Corporation. All rights reserved.
* The contents of this file are subject to the terms of the
* Common Development and Distribution License (the "License").
* You may not use this file except in compliance with the License.
*
* You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
* See the License for the specific language governing permissions
* and limitations under the License.
*
* When distributing Covered Code, include this CDDL HEADER in each
* file and include the License file at usr/src/OPENSOLARIS.LICENSE.
* If applicable, add the following below this CDDL HEADER, with the
* fields enclosed by brackets "[]" replaced with your own identifying
* information: Portions Copyright [yyyy] [name of copyright owner]
*
* CDDL HEADER END
*/
/*
* Copyright 2009 Sun Microsystems, Inc. All rights reserved.
* Use is subject to license terms.
*/
#include "ixgbe_sw.h"
/*
* Retrieve a value for one of the statistics.
*/
int
{
int i;
return (ECANCELED);
}
switch (stat) {
case MAC_STAT_IFSPEED:
break;
case MAC_STAT_MULTIRCV:
break;
case MAC_STAT_BRDCSTRCV:
break;
case MAC_STAT_MULTIXMT:
break;
case MAC_STAT_BRDCSTXMT:
break;
case MAC_STAT_NORCVBUF:
for (i = 0; i < 8; i++) {
}
break;
case MAC_STAT_IERRORS:
break;
case MAC_STAT_RBYTES:
for (i = 0; i < 16; i++) {
}
break;
case MAC_STAT_OBYTES:
for (i = 0; i < 16; i++) {
} else {
}
}
break;
case MAC_STAT_IPACKETS:
break;
case MAC_STAT_OPACKETS:
break;
/* RFC 1643 stats */
case ETHER_STAT_FCS_ERRORS:
break;
break;
case ETHER_STAT_MACRCV_ERRORS:
break;
case ETHER_STAT_XCVR_ADDR:
/* The Internal PHY's MDI address for each MAC is 1 */
*val = 1;
break;
case ETHER_STAT_XCVR_ID:
break;
case ETHER_STAT_XCVR_INUSE:
switch (ixgbe->link_speed) {
*val =
break;
break;
default:
break;
}
break;
case ETHER_STAT_CAP_10GFDX:
*val = 1;
break;
case ETHER_STAT_CAP_1000FDX:
*val = 1;
break;
case ETHER_STAT_CAP_100FDX:
*val = 1;
break;
case ETHER_STAT_CAP_ASMPAUSE:
break;
case ETHER_STAT_CAP_PAUSE:
break;
case ETHER_STAT_CAP_AUTONEG:
*val = 1;
break;
break;
break;
break;
break;
case ETHER_STAT_ADV_CAP_PAUSE:
break;
break;
case ETHER_STAT_LP_CAP_10GFDX:
break;
break;
case ETHER_STAT_LP_CAP_100FDX:
break;
break;
case ETHER_STAT_LP_CAP_PAUSE:
break;
break;
case ETHER_STAT_LINK_ASMPAUSE:
break;
case ETHER_STAT_LINK_PAUSE:
break;
case ETHER_STAT_LINK_AUTONEG:
break;
case ETHER_STAT_LINK_DUPLEX:
break;
break;
case ETHER_STAT_CAP_REMFAULT:
break;
case ETHER_STAT_ADV_REMFAULT:
break;
case ETHER_STAT_LP_REMFAULT:
break;
case ETHER_STAT_JABBER_ERRORS:
break;
default:
return (ENOTSUP);
}
return (EIO);
}
return (0);
}
/*
* was in when the interface was registered.
*/
int
ixgbe_m_start(void *arg)
{
return (ECANCELED);
}
return (EIO);
}
/*
* Enable and start the watchdog timer
*/
return (0);
}
/*
* that the interface can be unregistered.
*/
void
ixgbe_m_stop(void *arg)
{
return;
}
/*
* Disable and stop the watchdog timer
*/
}
/*
* Set the promiscuity of the device.
*/
int
{
return (ECANCELED);
}
if (on)
else
return (0);
}
/*
* addresses for which the device will receive packets.
*/
int
{
int result;
return (ECANCELED);
}
return (result);
}
/*
* Pass on M_IOCTL messages passed to the DLD, and support
* private IOCTLs for debugging and ndd.
*/
void
{
return;
}
case LB_GET_INFO_SIZE:
case LB_GET_INFO:
case LB_GET_MODE:
case LB_SET_MODE:
break;
default:
break;
}
/*
* Decide how to reply
*/
switch (status) {
default:
case IOC_INVAL:
/*
* Error, reply with a NAK and EINVAL or the specified error
*/
break;
case IOC_DONE:
/*
* OK, reply already sent
*/
break;
case IOC_ACK:
/*
* OK, reply with an ACK
*/
break;
case IOC_REPLY:
/*
* OK, send prepared reply as ACK or NAK
*/
break;
}
}
/*
* Obtain the MAC's capabilities and associated data from
* the driver.
*/
{
switch (cap) {
case MAC_CAPAB_HCKSUM: {
/*
* We advertise our capabilities only if tx hcksum offload is
* enabled. On receive, the stack will accept checksummed
* packets anyway, even if we haven't said we can deliver
* them.
*/
if (!ixgbe->tx_hcksum_enable)
return (B_FALSE);
break;
}
case MAC_CAPAB_LSO: {
if (ixgbe->lso_enable) {
break;
} else {
return (B_FALSE);
}
}
case MAC_CAPAB_RINGS: {
case MAC_RING_TYPE_RX:
break;
case MAC_RING_TYPE_TX:
break;
default:
break;
}
break;
}
default:
return (B_FALSE);
}
return (B_TRUE);
}
int
{
int err = 0;
return (ECANCELED);
}
/*
* All en_* parameters are locked (read-only)
* while the device is in any sort of loopback mode.
*/
return (EBUSY);
}
switch (pr_num) {
case MAC_PROP_EN_10GFDX_CAP:
break;
} else {
goto setup_link;
}
case MAC_PROP_EN_1000FDX_CAP:
break;
} else {
goto setup_link;
}
case MAC_PROP_EN_100FDX_CAP:
break;
} else {
goto setup_link;
}
case MAC_PROP_AUTONEG:
break;
} else {
goto setup_link;
}
case MAC_PROP_FLOWCTRL:
switch (flow_control) {
default:
break;
case LINK_FLOWCTRL_NONE:
break;
case LINK_FLOWCTRL_RX:
break;
case LINK_FLOWCTRL_TX:
break;
case LINK_FLOWCTRL_BI:
break;
}
if (err == 0) {
}
break;
case MAC_PROP_ADV_10GFDX_CAP:
case MAC_PROP_ADV_1000FDX_CAP:
case MAC_PROP_ADV_100FDX_CAP:
case MAC_PROP_STATUS:
case MAC_PROP_SPEED:
case MAC_PROP_DUPLEX:
break;
case MAC_PROP_MTU:
err = 0;
break;
}
break;
}
break;
}
if (err == 0) {
sizeof (struct ether_vlan_header) + ETHERFCSL;
/*
* Set rx buffer size
*/
/*
* Set tx buffer size
*/
}
break;
case MAC_PROP_PRIVATE:
break;
default:
break;
}
return (err);
}
int
{
int err = 0;
if (pr_valsize == 0)
return (EINVAL);
switch (pr_num) {
case MAC_PROP_DUPLEX:
if (pr_valsize >= sizeof (link_duplex_t)) {
sizeof (link_duplex_t));
} else
break;
case MAC_PROP_SPEED:
if (pr_valsize >= sizeof (uint64_t)) {
} else
break;
case MAC_PROP_AUTONEG:
*perm = MAC_PROP_PERM_RW;
break;
case MAC_PROP_FLOWCTRL:
*perm = MAC_PROP_PERM_RW;
if (pr_valsize >= sizeof (uint32_t)) {
if (is_default) {
sizeof (flow_control));
break;
}
case ixgbe_fc_none:
break;
case ixgbe_fc_rx_pause:
break;
case ixgbe_fc_tx_pause:
break;
case ixgbe_fc_full:
break;
}
} else
break;
case MAC_PROP_ADV_10GFDX_CAP:
break;
case MAC_PROP_EN_10GFDX_CAP:
*perm = MAC_PROP_PERM_RW;
break;
case MAC_PROP_ADV_1000FDX_CAP:
break;
case MAC_PROP_EN_1000FDX_CAP:
*perm = MAC_PROP_PERM_RW;
break;
case MAC_PROP_ADV_100FDX_CAP:
break;
case MAC_PROP_EN_100FDX_CAP:
*perm = MAC_PROP_PERM_RW;
break;
case MAC_PROP_PRIVATE:
break;
case MAC_PROP_MTU:
if (!(pr_flags & MAC_PROP_POSSIBLE))
return (ENOTSUP);
if (pr_valsize < sizeof (mac_propval_range_t))
return (EINVAL);
break;
default:
break;
}
return (err);
}
{
/*
* All en_* parameters are locked (read-only) while
* the device is in any sort of loopback mode ...
*/
switch (pr_num) {
case MAC_PROP_EN_10GFDX_CAP:
case MAC_PROP_EN_1000FDX_CAP:
case MAC_PROP_EN_100FDX_CAP:
case MAC_PROP_AUTONEG:
case MAC_PROP_FLOWCTRL:
return (B_TRUE);
}
return (B_FALSE);
}
/* ARGSUSED */
int
{
int err = 0;
long result;
int i;
return (err);
}
if (result < MIN_TX_COPY_THRESHOLD ||
else {
}
return (err);
}
return (err);
}
if (result < MIN_TX_RECYCLE_THRESHOLD ||
else {
}
return (err);
}
return (err);
}
if (result < MIN_TX_OVERLOAD_THRESHOLD ||
else {
}
return (err);
}
return (err);
}
if (result < MIN_TX_RESCHED_THRESHOLD ||
else {
}
return (err);
}
return (err);
}
if (result < MIN_RX_COPY_THRESHOLD ||
else {
}
return (err);
}
return (err);
}
if (result < MIN_RX_LIMIT_PER_INTR ||
else {
}
return (err);
}
return (err);
}
else {
/*
* 82599 requires the interupt throttling rate is
* a multiple of 8. This is enforced by the register
* definiton.
*/
ixgbe->intr_throttling[0] =
for (i = 0; i < MAX_INTR_VECTOR; i++)
ixgbe->intr_throttling[i] =
ixgbe->intr_throttling[0];
/* Set interrupt throttling rate */
ixgbe->intr_throttling[i]);
}
return (err);
}
return (ENOTSUP);
}
int
{
int value;
*perm = MAC_PROP_PERM_RW;
err = 0;
goto done;
}
err = 0;
goto done;
}
err = 0;
goto done;
}
err = 0;
goto done;
}
err = 0;
goto done;
}
err = 0;
goto done;
}
err = 0;
goto done;
}
err = 0;
goto done;
}
ixgbe->intr_throttling[0]);
err = 0;
goto done;
}
done:
if (err == 0) {
}
return (err);
}