ixgbe_82599.c revision 19843f01b1bef3453f717c23c8f89fb9313f6749
/*
* CDDL HEADER START
*
* Copyright(c) 2007-2010 Intel Corporation. All rights reserved.
* The contents of this file are subject to the terms of the
* Common Development and Distribution License (the "License").
* You may not use this file except in compliance with the License.
*
* You can obtain a copy of the license at:
* See the License for the specific language governing permissions
* and limitations under the License.
*
* When using or redistributing this file, you may do so under the
* License only. No other modification of this header is permitted.
*
* If applicable, add the following below this CDDL HEADER, with the
* fields enclosed by brackets "[]" replaced with your own identifying
* information: Portions Copyright [yyyy] [name of copyright owner]
*
* CDDL HEADER END
*/
/*
* Copyright 2010 Sun Microsystems, Inc. All rights reserved.
* Use is subject to license terms.
*/
/* IntelVersion: 1.202 sol_ixgbe_shared_339b */
#include "ixgbe_type.h"
#include "ixgbe_api.h"
#include "ixgbe_common.h"
#include "ixgbe_phy.h"
bool autoneg_wait_to_complete);
bool autoneg_wait_to_complete);
bool autoneg_wait_to_complete);
void
{
DEBUGFUNC("ixgbe_init_mac_link_ops_82599");
/* Set up dual speed SFP+ support */
} else {
else
}
}
/*
* @hw: pointer to hardware structure
*
* Initialize any function pointers that were not able to be
* not known. Perform the SFP init if necessary.
*
*/
{
DEBUGFUNC("ixgbe_init_phy_ops_82599");
/* Identify the PHY or SFP module */
if (ret_val == IXGBE_ERR_SFP_NOT_SUPPORTED)
goto init_phy_ops_out;
/* Setup function pointers based on detected SFP module and speeds */
/* If copper media, overwrite with copper function pointers */
}
/* Set necessary function pointers based on phy type */
case ixgbe_phy_tn:
break;
case ixgbe_phy_aq:
break;
default:
break;
}
return (ret_val);
}
{
DEBUGFUNC("ixgbe_setup_sfp_modules_82599");
&data_offset);
if (ret_val != IXGBE_SUCCESS)
goto setup_sfp_out;
/* PHY config will finish before releasing the semaphore */
if (ret_val != IXGBE_SUCCESS) {
goto setup_sfp_out;
}
while (data_value != 0xffff) {
}
/* Now restart DSP by setting Restart_AN */
/* Release the semaphore */
/* Delay obtaining semaphore again to allow FW access */
}
return (ret_val);
}
/*
* ixgbe_init_ops_82599 - Inits func ptrs and MAC type
* @hw: pointer to hardware structure
*
* Initialize the function pointers and assign the MAC type for 82599.
* Does not touch the hardware.
*/
{
DEBUGFUNC("ixgbe_init_ops_82599");
/* PHY */
/* MAC */
/* RAR, Multicast, VLAN */
/* Link */
return (ret_val);
}
/*
* ixgbe_get_link_capabilities_82599 - Determines link capabilities
* @hw: pointer to hardware structure
* @speed: pointer to link speed
* @negotiation: true when autoneg or autotry is enabled
*
* Determines the link capabilities by reading the AUTOC register.
*/
{
DEBUGFUNC("ixgbe_get_link_capabilities_82599");
/*
* Determine link capabilities based on the stored value of AUTOC,
* which represents EEPROM defaults. If AUTOC value has not
* been stored, use the current register values.
*/
else
switch (autoc & IXGBE_AUTOC_LMS_MASK) {
*negotiation = false;
break;
*negotiation = false;
break;
case IXGBE_AUTOC_LMS_1G_AN:
*negotiation = true;
break;
*negotiation = false;
break;
if (autoc & IXGBE_AUTOC_KR_SUPP)
if (autoc & IXGBE_AUTOC_KX4_SUPP)
if (autoc & IXGBE_AUTOC_KX_SUPP)
*negotiation = true;
break;
if (autoc & IXGBE_AUTOC_KR_SUPP)
if (autoc & IXGBE_AUTOC_KX4_SUPP)
if (autoc & IXGBE_AUTOC_KX_SUPP)
*negotiation = true;
break;
*negotiation = false;
break;
default:
goto out;
}
*negotiation = true;
}
out:
return (status);
}
/*
* ixgbe_get_media_type_82599 - Get media type
* @hw: pointer to hardware structure
*
* Returns the media type (fiber, copper, backplane)
*/
enum ixgbe_media_type
{
enum ixgbe_media_type media_type;
DEBUGFUNC("ixgbe_get_media_type_82599");
/* Detect if there is a copper PHY attached. */
goto out;
}
case IXGBE_DEV_ID_82599_KX4:
case IXGBE_DEV_ID_82599_KR:
break;
case IXGBE_DEV_ID_82599_SFP:
break;
case IXGBE_DEV_ID_82599_CX4:
break;
case IXGBE_DEV_ID_82599_T:
break;
default:
break;
}
out:
return (media_type);
}
/*
* ixgbe_start_mac_link_82599 - Setup MAC link settings
* @hw: pointer to hardware structure
*
* Configures link settings based on values in the ixgbe_hw struct.
* Restarts the link. Performs autonegotiation if needed.
*/
{
u32 i;
DEBUGFUNC("ixgbe_start_mac_link_82599");
/* Restart link */
/* Only poll for autoneg to complete if specified to do so */
if (autoneg_wait_to_complete) {
if ((autoc_reg & IXGBE_AUTOC_LMS_MASK) ==
(autoc_reg & IXGBE_AUTOC_LMS_MASK) ==
(autoc_reg & IXGBE_AUTOC_LMS_MASK) ==
links_reg = 0; /* Just in case Autoneg time = 0 */
for (i = 0; i < IXGBE_AUTO_NEG_TIME; i++) {
if (links_reg & IXGBE_LINKS_KX_AN_COMP)
break;
msec_delay(100);
}
if (!(links_reg & IXGBE_LINKS_KX_AN_COMP)) {
DEBUGOUT("Autoneg did not complete.\n");
}
}
}
/* Add delay to filter out noises during initial link setup */
msec_delay(50);
return (status);
}
/*
* ixgbe_setup_mac_link_multispeed_fiber - Set MAC link speed
* @hw: pointer to hardware structure
* @speed: new link speed
* @autoneg: true if autonegotiation enabled
* @autoneg_wait_to_complete: true when waiting for completion is needed
*
* Set the link speed in the AUTOC register and restarts link.
*/
{
u32 i = 0;
bool link_up = false;
bool negotiation;
DEBUGFUNC("ixgbe_setup_mac_link_multispeed_fiber");
/* Mask off requested but non-supported speeds */
if (status != IXGBE_SUCCESS)
return (status);
speed &= link_speed;
/*
* When the driver changes the link speeds that it can support,
* it sets autotry_restart to true to indicate that we need to
* initiate a new autotry session with the link partner. To do
* so, we set the speed then disable and re-enable the tx laser, to
* alert the link partner that it also needs to restart autotry on its
* end. This is consistent with true clause 37 autoneg, which also
* involves a loss of signal.
*/
/*
* Try each speed one by one, highest priority first. We do this in
* software because 10gb fiber doesn't support speed autonegotiation.
*/
if (speed & IXGBE_LINK_SPEED_10GB_FULL) {
speedcnt++;
/* If we already have link at this speed, just jump out */
if (status != IXGBE_SUCCESS)
return (status);
goto out;
/* Set the module link speed */
/* Allow module to change analog characteristics (1G->10G) */
msec_delay(40);
if (status != IXGBE_SUCCESS)
return (status);
/* Flap the tx laser if it has not already been done */
/* Disable tx laser; allow 100us to go dark per spec */
usec_delay(100);
/* Enable tx laser; allow 2ms to light up per spec */
esdp_reg &= ~IXGBE_ESDP_SDP3;
msec_delay(2);
}
/*
* Wait for the controller to acquire link. Per IEEE 802.3ap,
* Section 73.10.2, we may have to wait up to 500ms if KR is
* attempted. 82599 uses the same timing for 10g SFI.
*/
for (i = 0; i < 5; i++) {
/* Wait for the link partner to also set speed */
msec_delay(100);
/* If we have link, just jump out */
&link_up, false);
if (status != IXGBE_SUCCESS)
return (status);
if (link_up)
goto out;
}
}
if (speed & IXGBE_LINK_SPEED_1GB_FULL) {
speedcnt++;
/* If we already have link at this speed, just jump out */
if (status != IXGBE_SUCCESS)
return (status);
goto out;
/* Set the module link speed */
esdp_reg &= ~IXGBE_ESDP_SDP5;
/* Allow module to change analog characteristics (10G->1G) */
msec_delay(40);
if (status != IXGBE_SUCCESS)
return (status);
/* Flap the tx laser if it has not already been done */
/* Disable tx laser; allow 100us to go dark per spec */
usec_delay(100);
/* Enable tx laser; allow 2ms to light up per spec */
esdp_reg &= ~IXGBE_ESDP_SDP3;
msec_delay(2);
}
/* Wait for the link partner to also set speed */
msec_delay(100);
/* If we have link, just jump out */
if (status != IXGBE_SUCCESS)
return (status);
if (link_up)
goto out;
}
/*
* We didn't get link. Configure back to the highest speed we tried,
* (if there was more than one). We call ourselves back with just the
* single highest speed that the user requested.
*/
if (speedcnt > 1)
out:
/* Set autoneg_advertised value based on input link speed */
if (speed & IXGBE_LINK_SPEED_10GB_FULL)
if (speed & IXGBE_LINK_SPEED_1GB_FULL)
return (status);
}
/*
* ixgbe_setup_mac_link_smartspeed - Set MAC link speed using SmartSpeed
* @hw: pointer to hardware structure
* @speed: new link speed
* @autoneg: true if autonegotiation enabled
* @autoneg_wait_to_complete: true when waiting for completion is needed
*
* Implements the Intel SmartSpeed algorithm.
*/
{
s32 i, j;
bool link_up = false;
DEBUGFUNC("ixgbe_setup_mac_link_smartspeed");
/* Set autoneg_advertised value based on input link speed */
if (speed & IXGBE_LINK_SPEED_10GB_FULL)
if (speed & IXGBE_LINK_SPEED_1GB_FULL)
if (speed & IXGBE_LINK_SPEED_100_FULL)
/*
* Implement Intel SmartSpeed algorithm. SmartSpeed will reduce the
* autoneg advertisement if link is unable to be established at the
* highest negotiated rate. This can sometimes happen due to integrity
* issues with the physical media connection.
*/
/* First, try to get link with full advertisement */
for (j = 0; j < IXGBE_SMARTSPEED_MAX_RETRIES; j++) {
if (status != IXGBE_SUCCESS)
goto out;
/*
* Wait for the controller to acquire link. Per IEEE 802.3ap,
* Section 73.10.2, we may have to wait up to 500ms if KR is
* Table 9 in the AN MAS.
*/
for (i = 0; i < 5; i++) {
msec_delay(100);
/* If we have link, just jump out */
false);
if (status != IXGBE_SUCCESS)
goto out;
if (link_up)
goto out;
}
}
/*
*/
if (((autoc_reg & IXGBE_AUTOC_KR_SUPP) == 0) ||
((autoc_reg & IXGBE_AUTOC_KX4_KX_SUPP_MASK) == 0))
goto out;
/* Turn SmartSpeed on to disable KR support */
if (status != IXGBE_SUCCESS)
goto out;
/*
* Wait for the controller to acquire link. 600ms will allow for
* the AN link_fail_inhibit_timer as well for multiple cycles of
* parallel detect, both 10g and 1g. This allows for the maximum
* connect attempts as defined in the AN MAS table 73-7.
*/
for (i = 0; i < 6; i++) {
msec_delay(100);
/* If we have link, just jump out */
if (status != IXGBE_SUCCESS)
goto out;
if (link_up)
goto out;
}
/* We didn't get link. Turn SmartSpeed back off. */
out:
return (status);
}
/*
* ixgbe_setup_mac_link_82599 - Set MAC link speed
* @hw: pointer to hardware structure
* @speed: new link speed
* @autoneg: true if autonegotiation enabled
* @autoneg_wait_to_complete: true when waiting for completion is needed
*
* Set the link speed in the AUTOC register and restarts link.
*/
{
u32 orig_autoc = 0;
u32 i;
DEBUGFUNC("ixgbe_setup_mac_link_82599");
/* Check to see if speed passed in is supported. */
if (status != IXGBE_SUCCESS)
goto out;
if (speed == IXGBE_LINK_SPEED_UNKNOWN) {
goto out;
}
/*
*/
else
orig_autoc = autoc;
if (link_mode == IXGBE_AUTOC_LMS_KX4_KX_KR ||
if (speed & IXGBE_LINK_SPEED_10GB_FULL)
if (orig_autoc & IXGBE_AUTOC_KX4_SUPP)
if ((orig_autoc & IXGBE_AUTOC_KR_SUPP) &&
if (speed & IXGBE_LINK_SPEED_1GB_FULL)
} else if ((pma_pmd_1g == IXGBE_AUTOC_1G_SFI) &&
link_mode == IXGBE_AUTOC_LMS_1G_AN)) {
/* Switch from 1G SFI to 10G SFI if requested */
if ((speed == IXGBE_LINK_SPEED_10GB_FULL) &&
}
} else if ((pma_pmd_10g_serial == IXGBE_AUTOC2_10G_SFI) &&
(link_mode == IXGBE_AUTOC_LMS_10G_SERIAL)) {
/* Switch from 10G SFI to 1G SFI if requested */
if ((speed == IXGBE_LINK_SPEED_1GB_FULL) &&
(pma_pmd_1g == IXGBE_AUTOC_1G_SFI)) {
if (autoneg)
else
}
}
if (autoc != start_autoc) {
/* Restart link */
/* Only poll for autoneg to complete if specified to do so */
if (autoneg_wait_to_complete) {
if (link_mode == IXGBE_AUTOC_LMS_KX4_KX_KR ||
links_reg = 0; /* Just in case Autoneg time=0 */
for (i = 0; i < IXGBE_AUTO_NEG_TIME; i++) {
if (links_reg & IXGBE_LINKS_KX_AN_COMP)
break;
msec_delay(100);
}
if (!(links_reg & IXGBE_LINKS_KX_AN_COMP)) {
status =
DEBUGOUT("Autoneg did not complete.\n");
}
}
}
/* Add delay to filter out noises during initial link setup */
msec_delay(50);
}
out:
return (status);
}
/*
* ixgbe_setup_copper_link_82599 - Set the PHY autoneg advertised field
* @hw: pointer to hardware structure
* @speed: new link speed
* @autoneg: true if autonegotiation enabled
* @autoneg_wait_to_complete: true if waiting is needed to complete
*
* Restarts link on PHY and MAC based on settings passed in.
*/
static s32
{
DEBUGFUNC("ixgbe_setup_copper_link_82599");
/* Setup the PHY according to input speed */
/* Set up MAC */
return (status);
}
/*
* ixgbe_reset_hw_82599 - Perform hardware reset
* @hw: pointer to hardware structure
*
* Resets the hardware by resetting the transmit and receive units, masks
* and clears all interrupts, perform a PHY reset, and perform a link (MAC)
* reset.
*/
{
u32 i;
DEBUGFUNC("ixgbe_reset_hw_82599");
/* PHY ops must be identified and initialized prior to reset */
/* Identify PHY and related function pointers */
if (status == IXGBE_ERR_SFP_NOT_SUPPORTED)
goto reset_hw_out;
/* Setup SFP module if there is one present. */
}
if (status == IXGBE_ERR_SFP_NOT_SUPPORTED)
goto reset_hw_out;
/* Reset PHY */
/*
* Prevent the PCI-E bus from from hanging by disabling PCI-E master
* access and verify no pending requests before reset
*/
(void) ixgbe_disable_pcie_master(hw);
/*
* Issue global reset to the MAC. This needs to be a SW reset.
* If link reset is used, it might reset the MAC when mng is using it
*/
/* Poll for reset bit to self-clear indicating reset is complete */
for (i = 0; i < 10; i++) {
usec_delay(1);
if (!(ctrl & IXGBE_CTRL_RST)) {
break;
}
}
if (ctrl & IXGBE_CTRL_RST) {
DEBUGOUT("Reset polling failed to complete.\n");
}
/*
* Double resets are required for recovery from certain error
* conditions. Between resets, it is necessary to stall to allow time
* for any pending HW events to complete. We use 1usec since that is
* what is needed for ixgbe_disable_pcie_master(). The second reset
* then clears out any effects of those events.
*/
usec_delay(1);
goto mac_reset_top;
}
msec_delay(50);
/*
* stored off yet. Otherwise restore the stored original
* values since the reset operation sets back to defaults.
*/
} else {
}
if ((autoc2 & IXGBE_AUTOC2_UPPER_MASK) !=
}
}
/* Store the permanent mac address */
/*
* Store MAC address from RAR0, clear receive address registers, and
* clear the multicast table. Also reset num_rar_entries to 128,
* since we modify this value when programming the SAN MAC address.
*/
/* Store the permanent SAN mac address */
/* Add the SAN MAC address to the RAR only if it's a valid address */
/* Reserve the last RAR for the SAN MAC address */
}
return (status);
}
/*
* ixgbe_reinit_fdir_tables_82599 - Reinitialize Flow Director tables.
* @hw: pointer to hardware structure
*/
{
int i;
DEBUGFUNC("ixgbe_reinit_fdir_tables_82599");
/*
* Before starting reinitialization process,
* FDIRCMD.CMD must be zero.
*/
for (i = 0; i < IXGBE_FDIRCMD_CMD_POLL; i++) {
break;
usec_delay(10);
}
if (i >= IXGBE_FDIRCMD_CMD_POLL) {
DEBUGOUT("Flow Director previous command isn't complete, "
"aborting table re-initialization. \n");
return (IXGBE_ERR_FDIR_REINIT_FAILED);
}
/*
* 82599 adapters flow director init flow cannot be restarted,
* Workaround 82599 silicon errata by performing the following steps
* before re-writing the FDIRCTRL control register with the same value.
* - write 1 to bit 8 of FDIRCMD register &
* - write 0 to bit 8 of FDIRCMD register
*/
/*
* Clear FDIR Hash register to clear any leftover hashes
* waiting to be programmed.
*/
/* Poll init-done after we write FDIRCTRL register */
for (i = 0; i < IXGBE_FDIR_INIT_DONE_POLL; i++) {
break;
usec_delay(10);
}
if (i >= IXGBE_FDIR_INIT_DONE_POLL) {
DEBUGOUT("Flow Director Signature poll time exceeded!\n");
return (IXGBE_ERR_FDIR_REINIT_FAILED);
}
/* Clear FDIR statistics registers (read to clear) */
return (IXGBE_SUCCESS);
}
/*
* ixgbe_init_fdir_signature_82599 - Initialize Flow Director signature filters
* @hw: pointer to hardware structure
* @pballoc: which mode to allocate filters with
*/
{
int i;
DEBUGFUNC("ixgbe_init_fdir_signature_82599");
/*
* Before enabling Flow Director, the Rx Packet Buffer size
* must be reduced. The new value is the current size minus
* flow director memory usage size.
*/
/*
* The defaults in the HW for RX PB 1-7 are not zero and so should be
* intialized to zero for non DCB mode otherwise actual total RX PB
* would be bigger than programmed and filter space would run into
* the PB 0 region.
*/
for (i = 1; i < 8; i++)
/* Send interrupt when 64 filters are left */
/* Set the maximum length per hash bucket to 0xA filters */
switch (pballoc) {
case IXGBE_FDIR_PBALLOC_64K:
/* 8k - 1 signature filters */
break;
case IXGBE_FDIR_PBALLOC_128K:
/* 16k - 1 signature filters */
break;
case IXGBE_FDIR_PBALLOC_256K:
/* 32k - 1 signature filters */
break;
default:
/* bad value */
return (IXGBE_ERR_CONFIG);
};
/* Move the flexible bytes to use the ethertype - shift 6 words */
/* Prime the keys for hashing */
/*
* Poll init-done after we write the register. Estimated times:
* 10G: PBALLOC = 11b, timing is 60us
* 1G: PBALLOC = 11b, timing is 600us
* 100M: PBALLOC = 11b, timing is 6ms
*
* Multiple these timings by 4 if under full Rx load
*
* So we'll poll for IXGBE_FDIR_INIT_DONE_POLL times, sleeping for
* 1 msec per poll time. If we're at line rate and drop to 100M, then
* this might not finish in our poll time, but we can live with that
* for now.
*/
for (i = 0; i < IXGBE_FDIR_INIT_DONE_POLL; i++) {
break;
msec_delay(1);
}
if (i >= IXGBE_FDIR_INIT_DONE_POLL) {
DEBUGOUT("Flow Director Signature poll time exceeded!\n");
}
return (IXGBE_SUCCESS);
}
/*
* ixgbe_init_fdir_perfect_82599 - Initialize Flow Director perfect filters
* @hw: pointer to hardware structure
* @pballoc: which mode to allocate filters with
*/
{
int i;
DEBUGFUNC("ixgbe_init_fdir_perfect_82599");
/*
* Before enabling Flow Director, the Rx Packet Buffer size
* must be reduced. The new value is the current size minus
* flow director memory usage size.
*/
/*
* The defaults in the HW for RX PB 1-7 are not zero and so should be
* intialized to zero for non DCB mode otherwise actual total RX PB
* would be bigger than programmed and filter space would run into
* the PB 0 region.
*/
for (i = 1; i < 8; i++)
/* Send interrupt when 64 filters are left */
switch (pballoc) {
case IXGBE_FDIR_PBALLOC_64K:
/* 2k - 1 perfect filters */
break;
case IXGBE_FDIR_PBALLOC_128K:
/* 4k - 1 perfect filters */
break;
case IXGBE_FDIR_PBALLOC_256K:
/* 8k - 1 perfect filters */
break;
default:
/* bad value */
return (IXGBE_ERR_CONFIG);
};
/* Turn perfect match filtering on */
/* Move the flexible bytes to use the ethertype - shift 6 words */
/* Prime the keys for hashing */
/*
* Poll init-done after we write the register. Estimated times:
* 10G: PBALLOC = 11b, timing is 60us
* 1G: PBALLOC = 11b, timing is 600us
* 100M: PBALLOC = 11b, timing is 6ms
*
* Multiple these timings by 4 if under full Rx load
*
* So we'll poll for IXGBE_FDIR_INIT_DONE_POLL times, sleeping for
* 1 msec per poll time. If we're at line rate and drop to 100M, then
* this might not finish in our poll time, but we can live with that
* for now.
*/
/* Set the maximum length per hash bucket to 0xA filters */
for (i = 0; i < IXGBE_FDIR_INIT_DONE_POLL; i++) {
break;
msec_delay(1);
}
if (i >= IXGBE_FDIR_INIT_DONE_POLL) {
DEBUGOUT("Flow Director Perfect poll time exceeded!\n");
}
return (IXGBE_SUCCESS);
}
/*
* ixgbe_atr_compute_hash_82599 - Compute the hashes for SW ATR
* @stream: input bitstream to compute the hash on
* @key: 32-bit hash key
*/
{
/*
* The algorithm is as follows:
* Hash[15:0] = Sum { S[n] x K[n+16] }, n = 0...350
* where Sum {A[n]}, n = 0...n is bitwise XOR of A[0], A[1]...A[n]
* and A[n] x B[n] is bitwise AND between same length strings
*
* K[n] is 16 bits, defined as:
* for n modulo 32 >= 15, K[n] = K[n % 32 : (n % 32) - 15]
* for n modulo 32 < 15, K[n] =
* K[(n % 32:0) | (31:31 - (14 - (n % 32)))]
*
* S[n] is 16 bits, defined as:
* for n >= 15, S[n] = S[n:n - 15]
* for n < 15, S[n] = S[(n:0) | (350:350 - (14 - n))]
*
* To simplify for programming, the algorithm is implemented
* in software this way:
*
* Key[31:0], Stream[335:0]
*
* tmp_key[11 * 32 - 1:0] = 11{Key[31:0] = key concatenated 11 times
* int_key[350:0] = tmp_key[351:1]
* int_stream[365:0] = Stream[14:0] | Stream[335:0] | Stream[335:321]
*
* hash[15:0] = 0;
* for (i = 0; i < 351; i++) {
* if (int_key[i])
* hash ^= int_stream[(i + 15):i];
* }
*/
union {
} tmp_key;
u16 hash_result = 0;
int i, j, k, h;
DEBUGFUNC("ixgbe_atr_compute_hash_82599");
/*
* Initialize the fill member to prevent warnings
* on some compilers
*/
/* First load the temporary key stream */
for (i = 0; i < 6; i++) {
}
/*
* Set the interim key for the hashing. Bit 352 is unused, so we must
* shift and compensate when building the key.
*/
for (i = 1, j = 0; i < 44; i++) {
j++;
}
/*
* Set the interim bit string for the hashing. Bits 368 and 367 are
* unused, so shift and compensate when building the string.
*/
for (i = 1, j = 40; i < 46; i++) {
j++;
if (j > 41)
j = 0;
}
/*
* Now compute the hash. i is the index into hash_str, j is into our
* key stream, k is counting the number of bits, and h interates within
* each byte.
*/
for (i = 45, j = 43, k = 0; k < 351 && i >= 2 && j >= 0; i--, j--) {
for (h = 0; h < 8 && k < 351; h++, k++) {
if (int_key[j] & (1 << h)) {
/*
* Key bit is set, XOR in the current 16-bit
* string. Example of processing:
* h = 0,
* tmp = (hash_str[i - 2] & 0 << 16) |
* (hash_str[i - 1] & 0xff << 8) |
* (hash_str[i] & 0xff >> 0)
* So tmp = hash_str[15 + k:k], since the
* i + 2 clause rolls off the 16-bit value
* h = 7,
* tmp = (hash_str[i - 2] & 0x7f << 9) |
* (hash_str[i - 1] & 0xff << 1) |
* (hash_str[i] & 0x80 >> 7)
*/
<< (16 - h);
}
}
}
return (hash_result);
}
/*
* ixgbe_atr_set_vlan_id_82599 - Sets the VLAN id in the ATR input stream
* @input: input stream to modify
* @vlan: the VLAN id to load
*/
{
DEBUGFUNC("ixgbe_atr_set_vlan_id_82599");
return (IXGBE_SUCCESS);
}
/*
* ixgbe_atr_set_src_ipv4_82599 - Sets the source IPv4 address
* @input: input stream to modify
* @src_addr: the IP address to load
*/
{
DEBUGFUNC("ixgbe_atr_set_src_ipv4_82599");
return (IXGBE_SUCCESS);
}
/*
* ixgbe_atr_set_dst_ipv4_82599 - Sets the destination IPv4 address
* @input: input stream to modify
* @dst_addr: the IP address to load
*/
{
DEBUGFUNC("ixgbe_atr_set_dst_ipv4_82599");
return (IXGBE_SUCCESS);
}
/*
* ixgbe_atr_set_src_ipv6_82599 - Sets the source IPv6 address
* @input: input stream to modify
* @src_addr_1: the first 4 bytes of the IP address to load
* @src_addr_2: the second 4 bytes of the IP address to load
* @src_addr_3: the third 4 bytes of the IP address to load
* @src_addr_4: the fourth 4 bytes of the IP address to load
*/
{
DEBUGFUNC("ixgbe_atr_set_src_ipv6_82599");
return (IXGBE_SUCCESS);
}
/*
* ixgbe_atr_set_dst_ipv6_82599 - Sets the destination IPv6 address
* @input: input stream to modify
* @dst_addr_1: the first 4 bytes of the IP address to load
* @dst_addr_2: the second 4 bytes of the IP address to load
* @dst_addr_3: the third 4 bytes of the IP address to load
* @dst_addr_4: the fourth 4 bytes of the IP address to load
*/
{
DEBUGFUNC("ixgbe_atr_set_dst_ipv6_82599");
return (IXGBE_SUCCESS);
}
/*
* ixgbe_atr_set_src_port_82599 - Sets the source port
* @input: input stream to modify
* @src_port: the source port to load
*/
{
DEBUGFUNC("ixgbe_atr_set_src_port_82599");
return (IXGBE_SUCCESS);
}
/*
* ixgbe_atr_set_dst_port_82599 - Sets the destination port
* @input: input stream to modify
* @dst_port: the destination port to load
*/
{
DEBUGFUNC("ixgbe_atr_set_dst_port_82599");
return (IXGBE_SUCCESS);
}
/*
* ixgbe_atr_set_flex_byte_82599 - Sets the flexible bytes
* @input: input stream to modify
* @flex_bytes: the flexible bytes to load
*/
{
DEBUGFUNC("ixgbe_atr_set_flex_byte_82599");
return (IXGBE_SUCCESS);
}
/*
* ixgbe_atr_set_vm_pool_82599 - Sets the Virtual Machine pool
* @input: input stream to modify
* @vm_pool: the Virtual Machine pool to load
*/
{
DEBUGFUNC("ixgbe_atr_set_vm_pool_82599");
return (IXGBE_SUCCESS);
}
/*
* ixgbe_atr_set_l4type_82599 - Sets the layer 4 packet type
* @input: input stream to modify
* @l4type: the layer 4 type value to load
*/
{
DEBUGFUNC("ixgbe_atr_set_l4type_82599");
return (IXGBE_SUCCESS);
}
/*
* ixgbe_atr_get_vlan_id_82599 - Gets the VLAN id from the ATR input stream
* @input: input stream to search
* @vlan: the VLAN id to load
*/
{
DEBUGFUNC("ixgbe_atr_get_vlan_id_82599");
return (IXGBE_SUCCESS);
}
/*
* ixgbe_atr_get_src_ipv4_82599 - Gets the source IPv4 address
* @input: input stream to search
* @src_addr: the IP address to load
*/
{
DEBUGFUNC("ixgbe_atr_get_src_ipv4_82599");
return (IXGBE_SUCCESS);
}
/*
* ixgbe_atr_get_dst_ipv4_82599 - Gets the destination IPv4 address
* @input: input stream to search
* @dst_addr: the IP address to load
*/
{
DEBUGFUNC("ixgbe_atr_get_dst_ipv4_82599");
return (IXGBE_SUCCESS);
}
/*
* ixgbe_atr_get_src_ipv6_82599 - Gets the source IPv6 address
* @input: input stream to search
* @src_addr_1: the first 4 bytes of the IP address to load
* @src_addr_2: the second 4 bytes of the IP address to load
* @src_addr_3: the third 4 bytes of the IP address to load
* @src_addr_4: the fourth 4 bytes of the IP address to load
*/
{
DEBUGFUNC("ixgbe_atr_get_src_ipv6_82599");
return (IXGBE_SUCCESS);
}
/*
* ixgbe_atr_get_dst_ipv6_82599 - Gets the destination IPv6 address
* @input: input stream to search
* @dst_addr_1: the first 4 bytes of the IP address to load
* @dst_addr_2: the second 4 bytes of the IP address to load
* @dst_addr_3: the third 4 bytes of the IP address to load
* @dst_addr_4: the fourth 4 bytes of the IP address to load
*/
{
DEBUGFUNC("ixgbe_atr_get_dst_ipv6_82599");
return (IXGBE_SUCCESS);
}
/*
* ixgbe_atr_get_src_port_82599 - Gets the source port
* @input: input stream to modify
* @src_port: the source port to load
*
* Even though the input is given in big-endian, the FDIRPORT registers
* expect the ports to be programmed in little-endian. Hence the need to swap
* endianness when retrieving the data. This can be confusing since the
* internal hash engine expects it to be big-endian.
*/
{
DEBUGFUNC("ixgbe_atr_get_src_port_82599");
return (IXGBE_SUCCESS);
}
/*
* ixgbe_atr_get_dst_port_82599 - Gets the destination port
* @input: input stream to modify
* @dst_port: the destination port to load
*
* Even though the input is given in big-endian, the FDIRPORT registers
* expect the ports to be programmed in little-endian. Hence the need to swap
* endianness when retrieving the data. This can be confusing since the
* internal hash engine expects it to be big-endian.
*/
{
DEBUGFUNC("ixgbe_atr_get_dst_port_82599");
return (IXGBE_SUCCESS);
}
/*
* ixgbe_atr_get_flex_byte_82599 - Gets the flexible bytes
* @input: input stream to modify
* @flex_bytes: the flexible bytes to load
*/
{
DEBUGFUNC("ixgbe_atr_get_flex_byte_82599");
return (IXGBE_SUCCESS);
}
/*
* ixgbe_atr_get_vm_pool_82599 - Gets the Virtual Machine pool
* @input: input stream to modify
* @vm_pool: the Virtual Machine pool to load
*/
{
DEBUGFUNC("ixgbe_atr_get_vm_pool_82599");
return (IXGBE_SUCCESS);
}
/*
* ixgbe_atr_get_l4type_82599 - Gets the layer 4 packet type
* @input: input stream to modify
* @l4type: the layer 4 type value to load
*/
{
DEBUGFUNC("ixgbe_atr_get_l4type__82599");
return (IXGBE_SUCCESS);
}
/*
* ixgbe_atr_add_signature_filter_82599 - Adds a signature hash filter
* @hw: pointer to hardware structure
* @stream: input bitstream
* @queue: queue index to direct traffic to
*/
{
DEBUGFUNC("ixgbe_fdir_add_signature_filter_82599");
/* bucket_hash is only 15 bits */
/* Get the l4type in order to program FDIRCMD properly */
/* lowest 2 bits are FDIRCMD.L4TYPE, third lowest bit is FDIRCMD.IPV6 */
/*
* The lower 32-bits of fdirhashcmd is for FDIRHASH, the upper 32-bits
* is for FDIRCMD. Then do a 64-bit register write from FDIRHASH.
*/
switch (l4type & IXGBE_ATR_L4TYPE_MASK) {
case IXGBE_ATR_L4TYPE_TCP:
break;
case IXGBE_ATR_L4TYPE_UDP:
break;
case IXGBE_ATR_L4TYPE_SCTP:
break;
default:
DEBUGOUT(" Error on l4type input\n");
return (IXGBE_ERR_CONFIG);
}
if (l4type & IXGBE_ATR_L4TYPE_IPV6_MASK)
return (IXGBE_SUCCESS);
}
/*
* ixgbe_fdir_add_perfect_filter_82599 - Adds a perfect filter
* @hw: pointer to hardware structure
* @input: input bitstream
* @queue: queue index to direct traffic to
*
* Note that the caller to this function must lock before calling, since the
* hardware writes must be protected from one another.
*/
{
DEBUGFUNC("ixgbe_fdir_add_perfect_filter_82599");
/* Get our input values */
/*
* Check l4type formatting, and bail out before we touch the hardware
* if there's a configuration issue
*/
switch (l4type & IXGBE_ATR_L4TYPE_MASK) {
case IXGBE_ATR_L4TYPE_TCP:
break;
case IXGBE_ATR_L4TYPE_UDP:
break;
case IXGBE_ATR_L4TYPE_SCTP:
break;
default:
DEBUGOUT(" Error on l4type input\n");
return (IXGBE_ERR_CONFIG);
}
/* bucket_hash is only 15 bits */
/* Now figure out if we're IPv4 or IPv6 */
if (l4type & IXGBE_ATR_L4TYPE_IPV6_MASK) {
/* IPv6 */
/* The last 4 bytes is the same register as IPv4 */
} else {
/* IPv4 */
}
(flex_bytes << IXGBE_FDIRVLAN_FLEX_SHIFT)));
return (IXGBE_SUCCESS);
}
/*
* ixgbe_read_analog_reg8_82599 - Reads 8 bit Omer analog register
* @hw: pointer to hardware structure
* @reg: analog register to read
* @val: read value
*
* Performs read operation to Omer analog register specified.
*/
{
DEBUGFUNC("ixgbe_read_analog_reg8_82599");
(reg << 8));
usec_delay(10);
return (IXGBE_SUCCESS);
}
/*
* ixgbe_write_analog_reg8_82599 - Writes 8 bit Omer analog register
* @hw: pointer to hardware structure
* @reg: atlas register to write
* @val: value to write
*
* Performs write operation to Omer analog register specified.
*/
{
DEBUGFUNC("ixgbe_write_analog_reg8_82599");
usec_delay(10);
return (IXGBE_SUCCESS);
}
/*
* @hw: pointer to hardware structure
*
* Starts the hardware using the generic start_hw function.
* Then performs revision-specific operations:
* Clears the rate limiter registers.
*/
{
u32 i;
DEBUGFUNC("ixgbe_start_hw_rev_1__82599");
/* Clear the rate limiters */
}
/* Disable relaxed ordering */
}
}
/* We need to run link autotry after the driver loads */
if (ret_val == IXGBE_SUCCESS)
return (ret_val);
}
/*
* ixgbe_identify_phy_82599 - Get physical layer module
* @hw: pointer to hardware structure
*
* Determines the physical layer module found on the current adapter.
* If PHY already detected, maintains current PHY type in hw struct,
* otherwise executes the PHY detection routine.
*/
{
DEBUGFUNC("ixgbe_identify_phy_82599");
/* Detect PHY if not unknown - returns success if already detected. */
if (status != IXGBE_SUCCESS)
/* Set PHY type none if no PHY detected */
}
/* Return error if SFP module has been detected but is not supported */
return (status);
}
/*
* ixgbe_get_supported_physical_layer_82599 - Returns physical layer type
* @hw: pointer to hardware structure
*
* Determines physical layer capabilities of the current configuration.
*/
{
u16 ext_ability = 0;
u8 comp_codes_10g = 0;
DEBUGFUNC("ixgbe_get_support_physical_layer_82599");
goto out;
}
switch (autoc & IXGBE_AUTOC_LMS_MASK) {
case IXGBE_AUTOC_LMS_1G_AN:
if (pma_pmd_1g == IXGBE_AUTOC_1G_KX_BX) {
goto out;
} else {
/* SFI mode so read SFP module */
goto sfp_check;
}
else if (pma_pmd_10g_parallel == IXGBE_AUTOC_10G_KX4)
else if (pma_pmd_10g_parallel == IXGBE_AUTOC_10G_XAUI)
goto out;
if (pma_pmd_10g_serial == IXGBE_AUTOC2_10G_KR) {
goto out;
} else if (pma_pmd_10g_serial == IXGBE_AUTOC2_10G_SFI)
goto sfp_check;
break;
if (autoc & IXGBE_AUTOC_KX_SUPP)
if (autoc & IXGBE_AUTOC_KX4_SUPP)
if (autoc & IXGBE_AUTOC_KR_SUPP)
goto out;
default:
goto out;
}
/*
* SFP check must be done last since DA modules are sometimes used to
* test KR mode - we need to id KR mode correctly before SFP module.
* Call identify_sfp because the pluggable module may have changed
*/
goto out;
case ixgbe_phy_tw_tyco:
case ixgbe_phy_tw_unknown:
break;
case ixgbe_phy_sfp_avago:
case ixgbe_phy_sfp_ftl:
case ixgbe_phy_sfp_intel:
case ixgbe_phy_sfp_unknown:
else if (comp_codes_10g & IXGBE_SFF_10GBASELR_CAPABLE)
break;
default:
break;
}
out:
return (physical_layer);
}
/*
* ixgbe_enable_rx_dma_82599 - Enable the Rx DMA unit on 82599
* @hw: pointer to hardware structure
* @regval: register value to write to RXCTRL
*
* Enables the Rx DMA unit for 82599
*/
{
#define IXGBE_MAX_SECRX_POLL 30
int i;
int secrxreg;
DEBUGFUNC("ixgbe_enable_rx_dma_82599");
/*
* Workaround for 82599 silicon errata when enabling the Rx datapath.
* If traffic is incoming before we enable the Rx unit, it could hang
* the Rx DMA unit. Therefore, make sure the security engine is
* completely disabled prior to enabling the Rx unit.
*/
for (i = 0; i < IXGBE_MAX_SECRX_POLL; i++) {
break;
else
/* Use interrupt-safe sleep just in case */
usec_delay(10);
}
/* For informational purposes only */
if (i >= IXGBE_MAX_SECRX_POLL)
DEBUGOUT("Rx unit being enabled before security "
"path fully disabled. Continuing with init.\n");
return (IXGBE_SUCCESS);
}
/*
* ixgbe_get_device_caps_82599 - Get additional device capabilities
* @hw: pointer to hardware structure
* @device_caps: the EEPROM word with the extra device capabilities
*
* This function will read the EEPROM location for the device capabilities,
* and return the word through device_caps.
*/
{
DEBUGFUNC("ixgbe_get_device_caps_82599");
return (IXGBE_SUCCESS);
}
/*
* ixgbe_verify_fw_version_82599 - verify fw version for 82599
* @hw: pointer to hardware structure
*
* Verifies that installed the firmware version is 0.6 or higher
* for SFI devices. All 82599 SFI devices should have version 0.6 or higher.
*
* Returns IXGBE_ERR_EEPROM_VERSION if the FW is not present or
* if the FW version is not supported.
*/
static s32
{
u16 fw_version = 0;
DEBUGFUNC("ixgbe_verify_fw_version_82599");
/* firmware check is only necessary for SFI devices */
goto fw_version_out;
}
/* get the offset to the Firmware Module block */
goto fw_version_out;
/* get the offset to the Pass Through Patch Configuration block */
goto fw_version_out;
/* get the firmware version */
&fw_version);
if (fw_version > 0x5)
return (status);
}
/*
* ixgbe_enable_relaxed_ordering_82599 - Enable relaxed ordering
* @hw: pointer to hardware structure
*/
void
{
u32 i;
DEBUGFUNC("ixgbe_enable_relaxed_ordering_82599");
/* Enable relaxed ordering */
}
}
}