ixgbe_type.h revision dc0cb1cda72a989d92d813e487cdff59f629aa3f
1N/A/****************************************************************************** 1N/A Copyright (c) 2001-2015, Intel Corporation 1N/A All rights reserved. 1N/A Redistribution and use in source and binary forms, with or without 1N/A modification, are permitted provided that the following conditions are met: 1N/A 1. Redistributions of source code must retain the above copyright notice, 1N/A this list of conditions and the following disclaimer. 1N/A 2. Redistributions in binary form must reproduce the above copyright 1N/A notice, this list of conditions and the following disclaimer in the 1N/A documentation and/or other materials provided with the distribution. 1N/A 3. Neither the name of the Intel Corporation nor the names of its 1N/A contributors may be used to endorse or promote products derived from 1N/A this software without specific prior written permission. 1N/A THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 1N/A AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 1N/A IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 1N/A ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 1N/A LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 1N/A CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 1N/A SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 1N/A INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 1N/A CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 1N/A ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 1N/A POSSIBILITY OF SUCH DAMAGE. 1N/A******************************************************************************/ 1N/A * The following is a brief description of the error categories used by the 1N/A * ERROR_REPORT* macros. 1N/A * - IXGBE_ERROR_INVALID_STATE 1N/A * This category is for errors which represent a serious failure state that is 1N/A * unexpected, and could be potentially harmful to device operation. It should * not be used for errors relating to issues that can be worked around or * This category is for errors related to polling/timeout issues and should be * used in any case where the timeout occurred, or a failure to obtain a lock, or * failure to receive data within the time limit. * This category should be used for reporting issues that may be the cause of * other errors, such as temperature warnings. It should indicate an event which * could be serious, but hasn't necessarily caused problems yet. * This category is intended for errors due to software state preventing * something. The category is not intended for errors due to bad arguments, or * due to unsupported features. It should be used when a state occurs which * prevents action but is not a serious issue. * This category is for when a bad or invalid argument is passed. It should be * used whenever a function is called and error checking has detected the * argument is wrong or incorrect. * - IXGBE_ERROR_UNSUPPORTED * This category is for errors which are due to unsupported circumstances or * configuration issues. It should not be used when the issue is due to an * invalid argument, but for when something has occurred that is unsupported * (Ex: Flow control autonegotiation or an unsupported SFP+ module.) /* Override this by setting IOMEM in your ixgbe_osdep.h header */ /* General Receive Control */ /* Interrupt Registers */ /* 82599 EITR is only 12 bits, with the lower 3 always zero */ * 82598 EITR is 16 bits but set the limits based on the max * supported by all ixgbe hardware (
0x012300 + (((
_i) -
24) *
4)))
#
define IXGBE_MSIXT 0x00000 /* MSI-X Table. 0x0000 - 0x01C *//* Flow Control Registers */ /* Receive DMA Registers */ (
0x0D000 + (((
_i) -
64) *
0x40)))
(
0x0D004 + (((
_i) -
64) *
0x40)))
(
0x0D008 + (((
_i) -
64) *
0x40)))
(
0x0D010 + (((
_i) -
64) *
0x40)))
(
0x0D018 + (((
_i) -
64) *
0x40)))
(
0x0D028 + (((
_i) -
64) *
0x40)))
(
0x0D02C + (((
_i) -
64) *
0x40)))
* Split and Replication Receive Control Registers * 16-64 : 0x01014 + n*0x40 * 64-127: 0x0D014 + (n-64)*0x40 (((
_i) <
64) ? (
0x01014 + ((
_i) *
0x40)) : \
(
0x0D014 + (((
_i) -
64) *
0x40))))
* Rx DCA Control Register: * 16-64 : 0x0100C + n*0x40 * 64-127: 0x0D00C + (n-64)*0x40 (((
_i) <
64) ? (
0x0100C + ((
_i) *
0x40)) : \
(
0x0D00C + (((
_i) -
64) *
0x40))))
/* 8 of these 0x03C00 - 0x03C1C */ /* Multicast Table Array - 128 entries */ /* Packet split receive type */ /* array of 4096 1-bit vlan filters */ /*array of 4096 4-bit vlan vmdq indices */ #
define IXGBE_SAQF(
_i) (
0x0E000 + ((
_i) *
4))
/* Source Address Queue Filter */#
define IXGBE_DAQF(
_i) (
0x0E200 + ((
_i) *
4))
/* Dest. Address Queue Filter */#
define IXGBE_SDPQF(
_i) (
0x0E400 + ((
_i) *
4))
/* Src Dest. Addr Queue Filter */#
define IXGBE_FTQF(
_i) (
0x0E600 + ((
_i) *
4))
/* Five Tuple Queue Filter */#
define IXGBE_ETQF(
_i) (
0x05128 + ((
_i) *
4))
/* EType Queue Filter */#
define IXGBE_ETQS(
_i) (
0x0EC00 + ((
_i) *
4))
/* EType Queue Select */#
define IXGBE_SYNQF 0x0EC30 /* SYN Packet Queue Filter */#
define IXGBE_VLVF(
_i) (
0x0F100 + ((
_i) *
4))
/* 64 of these (0-63) *//* 64 Mailboxes, 16 DW each */ #
define IXGBE_RETA(
_i) (
0x05C00 + ((
_i) *
4))
/* 32 of these (0-31) *//* Registers for setting up RSS on X550 with SRIOV * _p - pool number (0..63) * _i - index (0..10 for PFVFRSSRK, 0..15 for PFVFRETA) /* Flow Director registers */ /* Flow Director Stats registers */ /* Flow Director Programming registers */ /* Transmit DMA registers */ /* Anti-spoofing defines */ /* Tx DCA Control register : 128 of these (0-127) */ #
define IXGBE_IP4AT 0x05840 /* IPv4 table 0x5840-0x5858 */#
define IXGBE_IP6AT 0x05880 /* IPv6 table 0x5880-0x588F */#
define IXGBE_WUPM 0x05A00 /* wake up pkt memory 0x5A00-0x5A7C */#
define IXGBE_PROXYFC 0x05F64 /* Proxying Filter Control Register */#
define IXGBE_FHFT(
_n) (
0x09000 + ((
_n) *
0x100))
/* Flex host filter table *//* Ext Flexible Host Filter Table */ /* Four Flexible Filters are supported */ /* Six Flexible Filters are supported */ /* Eight Flexible Filters are supported */ /* Each Flexible Filter is at most 128 (0x80) bytes in length */ /* Definitions for power management and wakeup registers */ #
define IXGBE_WUC_WKEN 0x00000010 /* Enable PE_WAKE_N pin assertion *//* Wake Up Filter Control */ #
define IXGBE_WUFC_EX 0x00000004 /* Directed Exact Wakeup Enable */#
define IXGBE_WUFC_MC 0x00000008 /* Directed Multicast Wakeup Enable */#
define IXGBE_WUFC_ARP 0x00000020 /* ARP Request Packet Wakeup Enable */#
define IXGBE_WUFC_IPV4 0x00000040 /* Directed IPv4 Packet Wakeup Enable */#
define IXGBE_WUFC_IPV6 0x00000080 /* Directed IPv6 Packet Wakeup Enable */#
define IXGBE_WUFC_MNG 0x00000100 /* Directed Mgmt Packet Wakeup Enable *//* Mask for Ext. flex filters */ /* Proxying Filter Control */ /* DMA Coalescing configuration */ * DMA Coalescing threshold Rx PB TC[n] value in Kilobyte by link speed. * DMACRXT = 10Gbps = 10,000 bits / usec = 1250 bytes / usec 70 * 1250 == /* DMA Coalescing registers */ /* DMA Coalescing register fields */ /* EEE register fields */ /* Security Control Registers */ /* Security Bit Fields and Masks */ /* LinkSec (MacSec) Registers */ /* LinkSec (MacSec) Bit Fields and Masks */ /* BCN (for DCB) Registers */ /* FCoE DMA Context Registers */ /* FCoE Direct DMA Context */ /* FCoE Filter Context Registers */ /* FCoE Direct Filter Context */ /* FCoE Receive Control */ /* Higher 7 bits for the queue index */ #
define IXGBE_MPC(
_i) (
0x03FA0 + ((
_i) *
4))
/* 8 of these 3FA0-3FBC*/#
define IXGBE_RNBC(
_i) (
0x03FC0 + ((
_i) *
4))
/* 8 of these 3FC0-3FDC*/#
define IXGBE_FCCRC 0x05118 /* Num of Good Eth CRC w/ Bad FC CRC */#
define IXGBE_FCOEPRC 0x02428 /* Number of FCoE Packets Received */#
define IXGBE_FCOEPTC 0x08784 /* Number of FCoE Packets Transmitted */#
define IXGBE_FCOEDWTC 0x08788 /* Number of FCoE DWords Transmitted *//* Management Bit Fields and Masks */ /* Firmware Semaphore Register */ /* ARC Subsystem registers */ /* Driver sets this bit when done to put command in RAM */ /* PCI-E registers 82599-Specific */ /* PCI Express Control */ /* Time Sync Registers */ #
define IXGBE_RXSATRL 0x051A0 /* Rx timestamp attribute low - RO */#
define IXGBE_RXSATRH 0x051A8 /* Rx timestamp attribute high - RO */#
define IXGBE_RXMTRL 0x05120 /* RX message type register low - RW */#
define IXGBE_SYSTIML 0x08C0C /* System time register Low - RO */#
define IXGBE_SYSTIMH 0x08C10 /* System time register High - RO */#
define IXGBE_SYSTIMR 0x08C58 /* System time register Residue - RO */#
define IXGBE_TIMINCA 0x08C14 /* Increment attributes register - RW */#
define IXGBE_TIMADJL 0x08C18 /* Time Adjustment Offset register Low - RW */#
define IXGBE_TIMADJH 0x08C1C /* Time Adjustment Offset register High - RW */#
define IXGBE_TSAUXC 0x08C20 /* TimeSync Auxiliary Control register - RW */#
define IXGBE_CLKTIML 0x08C34 /* Clock Out Time Register Low - RW */#
define IXGBE_CLKTIMH 0x08C38 /* Clock Out Time Register High - RW */#
define IXGBE_FREQOUT0 0x08C34 /* Frequency Out 0 Control register - RW */#
define IXGBE_FREQOUT1 0x08C38 /* Frequency Out 1 Control register - RW */#
define IXGBE_AUXSTMPL0 0x08C3C /* Auxiliary Time Stamp 0 register Low - RO */#
define IXGBE_AUXSTMPH0 0x08C40 /* Auxiliary Time Stamp 0 register High - RO */#
define IXGBE_AUXSTMPL1 0x08C44 /* Auxiliary Time Stamp 1 register Low - RO */#
define IXGBE_AUXSTMPH1 0x08C48 /* Auxiliary Time Stamp 1 register High - RO */#
define IXGBE_TSIM 0x08C68 /* TimeSync Interrupt Mask Register - RW */#
define IXGBE_TSICR 0x08C60 /* TimeSync Interrupt Cause Register - WO */#
define IXGBE_TSSDP 0x0003C /* TimeSync SDP Configuration Register - RW *//* Diagnostic Registers */ /* Statistics Registers */ /* Copper Pond 2 link timeout */ /* RQTC Bit Masks and Shifts */ /* PSRTYPE.RQPL Bit masks and shift */ /* Extended Device Control */ /* Direct Cache Access (DCA) definitions */ /* Device Type definitions for new protocol MDIO commands */ #
define IXGBE_LDPCECL 0x0E820 /* PCR Uncorrected Error Count Lo */#
define IXGBE_LDPCECH 0x0E821 /* PCR Uncorrected Error Count Hi *//* MII clause 22/28 definitions */ /* Special PHY Init Routine */ /* General purpose Interrupt Enable */ /* Packet Buffer Initialization */ /* Packet buffer allocation strategies */ /* Transmit Flow Control status */ /* RDHMPN and TDHMPN bitmasks */ /* Receive Checksum Control */ /* Receive Arbitration Control: 0 Round Robin, 1 DFP */ /* Deficit Fixed Prio ena */ /* Interrupt register bitmasks */ /* Extended Interrupt Cause Read */ /* Extended Interrupt Cause Set */ /* Extended Interrupt Mask Set */ /* Extended Interrupt Mask Clear */ /* Immediate Interrupt Rx (A.K.A. Low Latency Interrupt) */ /* Interrupt clear mask */ /* Interrupt Vector Allocation Registers */ * ETQF filter list: one static filter per filter consumer. This is * to avoid filter collisions later. Add new filters * EAPOL 802.1x (0x888e): Filter 0 * FCoE (0x8906): Filter 2 * 1588 (0x88f7): Filter 3 * LLDP (0x88CC): Filter 5 * LACP (0x8809): Filter 6 /* VLAN Control Bit Masks */ /* VLAN pool filtering masks */ /* Per VF Port VLAN insertion rules */ /* Veto Bit definition */ /* PCS1GLSTA Bit Masks */ /* PCS1GLCTL Bit Masks */ /* SW Semaphore Register bitmasks */ /* FW Status register bitmask */ /* EEPROM Addressing bits based on type (0-small, 1-large) */ /* Part Number String Length */ /* Checksum and EEPROM pointers */ /* MSI-X capability fields masks */ /* Legacy EEPROM word offsets */ /* EEPROM Commands - SPI */ /* EEPROM reset Write Enable latch */ /* EEPROM Read Register */ /* Number of 5 microseconds we wait for EERD read and * EERW write to complete */ /* # attempts we wait for flush update to complete */ /* version word 2 (month & day) */ /* version word 3 (silicon compatibility & year) */ /* version word 4 (major & minor numbers) */ /* Number of 100 microseconds we wait for PCI Express master disable */ /* Check whether address is multicast. This is little-endian specific check.*/ /* Check whether an address is broadcast. */ /* Header split receive */ /* Transmit Config masks */ /* Enable short packet padding to 64 bytes */ /* This allows for 16K packets + 4k for vlan */ /* Receive Config masks */ /* Receive Priority Flow Control Enable */ /* Multiple Receive Queue Control */ /* Multiple Transmit Queue Command Register */ /* Receive Descriptor bit definitions */ /* PSRTYPE bit definitions */ /* SRRCTL bit definitions */ * + at bit 8 offset (<< 8) /* RSS Packet Types as indicated in the receive descriptor. */ /* Security Processing bit Indication */ /* Masks to determine if packets should be dropped due to frame errors */ /* Number of Transmit and Receive Descriptors must be a multiple of 8 */ /* Vlan-specific macros */ /* SR-IOV specific macros */ /* Translated register #defines */ (
0x012300 + (((P) -
24) *
4)))
: (
0x0D000 + (
0x40 * ((P) -
64))))
: (
0x0D004 + (
0x40 * ((P) -
64))))
: (
0x0D008 + (
0x40 * ((P) -
64))))
#
define IXGBE_PVFRDH(P) ((P <
64) ? (
0x01010 + (
0x40 * (P))) \
: (
0x0D010 + (
0x40 * ((P) -
64))))
#
define IXGBE_PVFRDT(P) ((P <
64) ? (
0x01018 + (
0x40 * (P))) \
: (
0x0D018 + (
0x40 * ((P) -
64))))
: (
0x0D028 + (
0x40 * ((P) -
64))))
: (
0x0D014 + (
0x40 * ((P) -
64))))
: (
0x0D00C + (
0x40 * ((P) -
64))))
/* Little Endian defines */ /* Flow Director register values */ /* Manageablility Host Interface defines */ /* Host Interface Command Structures */ u8 pad;
/* end spacing to ensure length is mult. of dword */ u16 pad2;
/* end spacing to ensure length is mult. of dword2 */ /* These need to be dword aligned */ /* Transmit Descriptor - Legacy */ u8 cso;
/* Checksum offset */ u8 cmd;
/* Descriptor control */ u8 css;
/* Checksum start */ /* Transmit Descriptor - Advanced */ /* Receive Descriptor - Legacy */ /* Receive Descriptor - Advanced */ /* Context descriptors */ /* Adv Transmit Descriptor Config Masks */ /* 1st&Last TSO-full iSCSI PDU */ /* Autonegotiation advertised speeds */ /* Physical layer type */ /* Flow Control Data Sheet defined values * Calculation and defines taken from 802.1bb Annex O /* BitTimes (BT) conversion */ /* Calculate Delay to respond to PFC */ /* Calculate Cable Delay */ /* Calculate Interface Delay X540 */ /* Calculate Interface Delay 82598, 82599 */ /* Calculate Delay incurred from higher layer */ /* Calculate PCI Bus delay for low thresholds */ /* Calculate X540 delay value in bit times */ /* Calculate 82599, 82598 delay value in bit times */ /* Calculate low threshold delay values */ /* Software ATR hash keys */ /* Software ATR input stream values and masks */ /* Flow Director ATR input struct. */ * Byte layout in order, all values with MSB first: /* Flow Director compressed ATR hash input struct */ * Unavailable: The FCoE Boot Option ROM is not present in the flash. * Disabled: Present; boot order is not set for any targets on the port. * Enabled: Present; boot order is set for at least one target on the port. * 3 SFP_DA_CU_CORE0 - 82599-specific * 4 SFP_DA_CU_CORE1 - 82599-specific /* Flow Control Settings */ /* Smart Speed Settings */ /* Flow control parameters */ bool send_xon;
/* Flow control send XON */ /* Statistics counters collected by the MAC */ /* forward declaration */ /* iterator type for walking multicast address lists */ /* Function pointer table */ /* Packet Buffer manipulation */ /* RAR, Multicast, VLAN */ /* Manageability interface */ /* prefix for World Wide Node Name (WWNN) */ /* prefix for World Wide Port Name (WWPN) */ #
endif /* _IXGBE_TYPE_H_ */