dc0cb1cda72a989d92d813e487cdff59f629aa3fDale Ghent/******************************************************************************
dc0cb1cda72a989d92d813e487cdff59f629aa3fDale Ghent Copyright (c) 2001-2015, Intel Corporation
dc0cb1cda72a989d92d813e487cdff59f629aa3fDale Ghent All rights reserved.
dc0cb1cda72a989d92d813e487cdff59f629aa3fDale Ghent Redistribution and use in source and binary forms, with or without
dc0cb1cda72a989d92d813e487cdff59f629aa3fDale Ghent modification, are permitted provided that the following conditions are met:
dc0cb1cda72a989d92d813e487cdff59f629aa3fDale Ghent 1. Redistributions of source code must retain the above copyright notice,
dc0cb1cda72a989d92d813e487cdff59f629aa3fDale Ghent this list of conditions and the following disclaimer.
dc0cb1cda72a989d92d813e487cdff59f629aa3fDale Ghent 2. Redistributions in binary form must reproduce the above copyright
dc0cb1cda72a989d92d813e487cdff59f629aa3fDale Ghent notice, this list of conditions and the following disclaimer in the
dc0cb1cda72a989d92d813e487cdff59f629aa3fDale Ghent documentation and/or other materials provided with the distribution.
dc0cb1cda72a989d92d813e487cdff59f629aa3fDale Ghent 3. Neither the name of the Intel Corporation nor the names of its
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dc0cb1cda72a989d92d813e487cdff59f629aa3fDale Ghent this software without specific prior written permission.
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dc0cb1cda72a989d92d813e487cdff59f629aa3fDale Ghent AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
dc0cb1cda72a989d92d813e487cdff59f629aa3fDale Ghent IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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dc0cb1cda72a989d92d813e487cdff59f629aa3fDale Ghent******************************************************************************/
dc0cb1cda72a989d92d813e487cdff59f629aa3fDale Ghent/*$FreeBSD$*/
dc0cb1cda72a989d92d813e487cdff59f629aa3fDale Ghent * ixgbe_dcb_calculate_tc_credits - This calculates the ieee traffic class
dc0cb1cda72a989d92d813e487cdff59f629aa3fDale Ghent * credits from the configured bandwidth percentages. Credits
dc0cb1cda72a989d92d813e487cdff59f629aa3fDale Ghent * are the smallest unit programmable into the underlying
dc0cb1cda72a989d92d813e487cdff59f629aa3fDale Ghent * hardware. The IEEE 802.1Qaz specification do not use bandwidth
dc0cb1cda72a989d92d813e487cdff59f629aa3fDale Ghent * groups so this is much simplified from the CEE case.
dc0cb1cda72a989d92d813e487cdff59f629aa3fDale Ghents32 ixgbe_dcb_calculate_tc_credits(u8 *bw, u16 *refill, u16 *max,
dc0cb1cda72a989d92d813e487cdff59f629aa3fDale Ghent min_credit = ((max_frame_size / 2) + IXGBE_DCB_CREDIT_QUANTUM - 1) /
dc0cb1cda72a989d92d813e487cdff59f629aa3fDale Ghent for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
dc0cb1cda72a989d92d813e487cdff59f629aa3fDale Ghent /* Find out the hw credits for each TC */
dc0cb1cda72a989d92d813e487cdff59f629aa3fDale Ghent for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
dc0cb1cda72a989d92d813e487cdff59f629aa3fDale Ghent int val = min(bw[i] * multiplier, IXGBE_DCB_MAX_CREDIT_REFILL);
dc0cb1cda72a989d92d813e487cdff59f629aa3fDale Ghent max[i] = bw[i] ? (bw[i]*IXGBE_DCB_MAX_CREDIT)/100 : min_credit;
dc0cb1cda72a989d92d813e487cdff59f629aa3fDale Ghent * ixgbe_dcb_calculate_tc_credits_cee - Calculates traffic class credits
dc0cb1cda72a989d92d813e487cdff59f629aa3fDale Ghent * @ixgbe_dcb_config: Struct containing DCB settings.
dc0cb1cda72a989d92d813e487cdff59f629aa3fDale Ghent * @direction: Configuring either Tx or Rx.
dc0cb1cda72a989d92d813e487cdff59f629aa3fDale Ghent * This function calculates the credits allocated to each traffic class.
dc0cb1cda72a989d92d813e487cdff59f629aa3fDale Ghent * It should be called only after the rules are checked by
dc0cb1cda72a989d92d813e487cdff59f629aa3fDale Ghent * ixgbe_dcb_check_config_cee().
dc0cb1cda72a989d92d813e487cdff59f629aa3fDale Ghents32 ixgbe_dcb_calculate_tc_credits_cee(struct ixgbe_hw *hw,
dc0cb1cda72a989d92d813e487cdff59f629aa3fDale Ghent /* Initialization values default for Tx settings */
dc0cb1cda72a989d92d813e487cdff59f629aa3fDale Ghent min_credit = ((max_frame_size / 2) + IXGBE_DCB_CREDIT_QUANTUM - 1) /
dc0cb1cda72a989d92d813e487cdff59f629aa3fDale Ghent /* Find smallest link percentage */
dc0cb1cda72a989d92d813e487cdff59f629aa3fDale Ghent for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
dc0cb1cda72a989d92d813e487cdff59f629aa3fDale Ghent bw_percent = dcb_config->bw_percentage[direction][p->bwg_id];
dc0cb1cda72a989d92d813e487cdff59f629aa3fDale Ghent link_percentage = (link_percentage * bw_percent) / 100;
dc0cb1cda72a989d92d813e487cdff59f629aa3fDale Ghent if (link_percentage && link_percentage < min_percent)
dc0cb1cda72a989d92d813e487cdff59f629aa3fDale Ghent * The ratio between traffic classes will control the bandwidth
dc0cb1cda72a989d92d813e487cdff59f629aa3fDale Ghent * percentages seen on the wire. To calculate this ratio we use
dc0cb1cda72a989d92d813e487cdff59f629aa3fDale Ghent * a multiplier. It is required that the refill credits must be
dc0cb1cda72a989d92d813e487cdff59f629aa3fDale Ghent * larger than the max frame size so here we find the smallest
dc0cb1cda72a989d92d813e487cdff59f629aa3fDale Ghent * multiplier that will allow all bandwidth percentages to be
dc0cb1cda72a989d92d813e487cdff59f629aa3fDale Ghent * greater than the max frame size.
dc0cb1cda72a989d92d813e487cdff59f629aa3fDale Ghent /* Find out the link percentage for each TC first */
dc0cb1cda72a989d92d813e487cdff59f629aa3fDale Ghent for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
dc0cb1cda72a989d92d813e487cdff59f629aa3fDale Ghent bw_percent = dcb_config->bw_percentage[direction][p->bwg_id];
dc0cb1cda72a989d92d813e487cdff59f629aa3fDale Ghent /* Must be careful of integer division for very small nums */
dc0cb1cda72a989d92d813e487cdff59f629aa3fDale Ghent link_percentage = (link_percentage * bw_percent) / 100;
dc0cb1cda72a989d92d813e487cdff59f629aa3fDale Ghent /* Save link_percentage for reference */
dc0cb1cda72a989d92d813e487cdff59f629aa3fDale Ghent /* Calculate credit refill ratio using multiplier */
dc0cb1cda72a989d92d813e487cdff59f629aa3fDale Ghent credit_refill = min(link_percentage * min_multiplier,
dc0cb1cda72a989d92d813e487cdff59f629aa3fDale Ghent /* Refill at least minimum credit */
dc0cb1cda72a989d92d813e487cdff59f629aa3fDale Ghent /* Calculate maximum credit for the TC */
dc0cb1cda72a989d92d813e487cdff59f629aa3fDale Ghent credit_max = (link_percentage * IXGBE_DCB_MAX_CREDIT) / 100;
dc0cb1cda72a989d92d813e487cdff59f629aa3fDale Ghent * Adjustment based on rule checking, if the percentage
dc0cb1cda72a989d92d813e487cdff59f629aa3fDale Ghent * of a TC is too small, the maximum credit may not be
dc0cb1cda72a989d92d813e487cdff59f629aa3fDale Ghent * enough to send out a jumbo frame in data plane arbitration.
dc0cb1cda72a989d92d813e487cdff59f629aa3fDale Ghent * Adjustment based on rule checking, if the
dc0cb1cda72a989d92d813e487cdff59f629aa3fDale Ghent * percentage of a TC is too small, the maximum
dc0cb1cda72a989d92d813e487cdff59f629aa3fDale Ghent * credit may not be enough to send out a TSO
dc0cb1cda72a989d92d813e487cdff59f629aa3fDale Ghent * packet in descriptor plane arbitration.
dc0cb1cda72a989d92d813e487cdff59f629aa3fDale Ghent * ixgbe_dcb_unpack_pfc_cee - Unpack dcb_config PFC info
dc0cb1cda72a989d92d813e487cdff59f629aa3fDale Ghent * @cfg: dcb configuration to unpack into hardware consumable fields
dc0cb1cda72a989d92d813e487cdff59f629aa3fDale Ghent * @map: user priority to traffic class map
dc0cb1cda72a989d92d813e487cdff59f629aa3fDale Ghent * @pfc_up: u8 to store user priority PFC bitmask
dc0cb1cda72a989d92d813e487cdff59f629aa3fDale Ghent * This unpacks the dcb configuration PFC info which is stored per
dc0cb1cda72a989d92d813e487cdff59f629aa3fDale Ghent * traffic class into a 8bit user priority bitmask that can be
dc0cb1cda72a989d92d813e487cdff59f629aa3fDale Ghent * consumed by hardware routines. The priority to tc map must be
dc0cb1cda72a989d92d813e487cdff59f629aa3fDale Ghent * updated before calling this routine to use current up-to maps.
dc0cb1cda72a989d92d813e487cdff59f629aa3fDale Ghentvoid ixgbe_dcb_unpack_pfc_cee(struct ixgbe_dcb_config *cfg, u8 *map, u8 *pfc_up)
dc0cb1cda72a989d92d813e487cdff59f629aa3fDale Ghent struct ixgbe_dcb_tc_config *tc_config = &cfg->tc_config[0];
dc0cb1cda72a989d92d813e487cdff59f629aa3fDale Ghent * If the TC for this user priority has PFC enabled then set the
dc0cb1cda72a989d92d813e487cdff59f629aa3fDale Ghent * matching bit in 'pfc_up' to reflect that PFC is enabled.
dc0cb1cda72a989d92d813e487cdff59f629aa3fDale Ghent for (*pfc_up = 0, up = 0; up < IXGBE_DCB_MAX_USER_PRIORITY; up++) {
dc0cb1cda72a989d92d813e487cdff59f629aa3fDale Ghent if (tc_config[map[up]].pfc != ixgbe_dcb_pfc_disabled)
dc0cb1cda72a989d92d813e487cdff59f629aa3fDale Ghentvoid ixgbe_dcb_unpack_refill_cee(struct ixgbe_dcb_config *cfg, int direction,
dc0cb1cda72a989d92d813e487cdff59f629aa3fDale Ghent struct ixgbe_dcb_tc_config *tc_config = &cfg->tc_config[0];
dc0cb1cda72a989d92d813e487cdff59f629aa3fDale Ghent for (tc = 0; tc < IXGBE_DCB_MAX_TRAFFIC_CLASS; tc++)
dc0cb1cda72a989d92d813e487cdff59f629aa3fDale Ghent refill[tc] = tc_config[tc].path[direction].data_credits_refill;
dc0cb1cda72a989d92d813e487cdff59f629aa3fDale Ghentvoid ixgbe_dcb_unpack_max_cee(struct ixgbe_dcb_config *cfg, u16 *max)
dc0cb1cda72a989d92d813e487cdff59f629aa3fDale Ghent struct ixgbe_dcb_tc_config *tc_config = &cfg->tc_config[0];
dc0cb1cda72a989d92d813e487cdff59f629aa3fDale Ghent for (tc = 0; tc < IXGBE_DCB_MAX_TRAFFIC_CLASS; tc++)
dc0cb1cda72a989d92d813e487cdff59f629aa3fDale Ghentvoid ixgbe_dcb_unpack_bwgid_cee(struct ixgbe_dcb_config *cfg, int direction,
dc0cb1cda72a989d92d813e487cdff59f629aa3fDale Ghent struct ixgbe_dcb_tc_config *tc_config = &cfg->tc_config[0];
dc0cb1cda72a989d92d813e487cdff59f629aa3fDale Ghent for (tc = 0; tc < IXGBE_DCB_MAX_TRAFFIC_CLASS; tc++)
dc0cb1cda72a989d92d813e487cdff59f629aa3fDale Ghent bwgid[tc] = tc_config[tc].path[direction].bwg_id;
dc0cb1cda72a989d92d813e487cdff59f629aa3fDale Ghentvoid ixgbe_dcb_unpack_tsa_cee(struct ixgbe_dcb_config *cfg, int direction,
dc0cb1cda72a989d92d813e487cdff59f629aa3fDale Ghent struct ixgbe_dcb_tc_config *tc_config = &cfg->tc_config[0];
dc0cb1cda72a989d92d813e487cdff59f629aa3fDale Ghent for (tc = 0; tc < IXGBE_DCB_MAX_TRAFFIC_CLASS; tc++)
dc0cb1cda72a989d92d813e487cdff59f629aa3fDale Ghentu8 ixgbe_dcb_get_tc_from_up(struct ixgbe_dcb_config *cfg, int direction, u8 up)
dc0cb1cda72a989d92d813e487cdff59f629aa3fDale Ghent struct ixgbe_dcb_tc_config *tc_config = &cfg->tc_config[0];
dc0cb1cda72a989d92d813e487cdff59f629aa3fDale Ghent /* If tc is 0 then DCB is likely not enabled or supported */
dc0cb1cda72a989d92d813e487cdff59f629aa3fDale Ghent * Test from maximum TC to 1 and report the first match we find. If
dc0cb1cda72a989d92d813e487cdff59f629aa3fDale Ghent * we find no match we can assume that the TC is 0 since the TC must
dc0cb1cda72a989d92d813e487cdff59f629aa3fDale Ghent * be set for all user priorities
dc0cb1cda72a989d92d813e487cdff59f629aa3fDale Ghent if (prio_mask & tc_config[tc].path[direction].up_to_tc_bitmap)
dc0cb1cda72a989d92d813e487cdff59f629aa3fDale Ghentvoid ixgbe_dcb_unpack_map_cee(struct ixgbe_dcb_config *cfg, int direction,
dc0cb1cda72a989d92d813e487cdff59f629aa3fDale Ghent for (up = 0; up < IXGBE_DCB_MAX_USER_PRIORITY; up++)
dc0cb1cda72a989d92d813e487cdff59f629aa3fDale Ghent map[up] = ixgbe_dcb_get_tc_from_up(cfg, direction, up);
dc0cb1cda72a989d92d813e487cdff59f629aa3fDale Ghent * ixgbe_dcb_config - Struct containing DCB settings.
dc0cb1cda72a989d92d813e487cdff59f629aa3fDale Ghent * @dcb_config: Pointer to DCB config structure
dc0cb1cda72a989d92d813e487cdff59f629aa3fDale Ghent * This function checks DCB rules for DCB settings.
dc0cb1cda72a989d92d813e487cdff59f629aa3fDale Ghent * The following rules are checked:
dc0cb1cda72a989d92d813e487cdff59f629aa3fDale Ghent * 1. The sum of bandwidth percentages of all Bandwidth Groups must total 100%.
dc0cb1cda72a989d92d813e487cdff59f629aa3fDale Ghent * 2. The sum of bandwidth percentages of all Traffic Classes within a Bandwidth
dc0cb1cda72a989d92d813e487cdff59f629aa3fDale Ghent * Group must total 100.
dc0cb1cda72a989d92d813e487cdff59f629aa3fDale Ghent * 3. A Traffic Class should not be set to both Link Strict Priority
dc0cb1cda72a989d92d813e487cdff59f629aa3fDale Ghent * and Group Strict Priority.
dc0cb1cda72a989d92d813e487cdff59f629aa3fDale Ghent * 4. Link strict Bandwidth Groups can only have link strict traffic classes
dc0cb1cda72a989d92d813e487cdff59f629aa3fDale Ghent * with zero bandwidth.
dc0cb1cda72a989d92d813e487cdff59f629aa3fDale Ghents32 ixgbe_dcb_check_config_cee(struct ixgbe_dcb_config *dcb_config)
dc0cb1cda72a989d92d813e487cdff59f629aa3fDale Ghent /* First Tx, then Rx */
dc0cb1cda72a989d92d813e487cdff59f629aa3fDale Ghent for (i = 0; i < 2; i++) {
dc0cb1cda72a989d92d813e487cdff59f629aa3fDale Ghent /* Check each traffic class for rule violation */
dc0cb1cda72a989d92d813e487cdff59f629aa3fDale Ghent for (j = 0; j < IXGBE_DCB_MAX_TRAFFIC_CLASS; j++) {
dc0cb1cda72a989d92d813e487cdff59f629aa3fDale Ghent /* Link strict should have zero bandwidth */
dc0cb1cda72a989d92d813e487cdff59f629aa3fDale Ghent } else if (!bw) {
dc0cb1cda72a989d92d813e487cdff59f629aa3fDale Ghent * Traffic classes without link strict
dc0cb1cda72a989d92d813e487cdff59f629aa3fDale Ghent * should have non-zero bandwidth.
dc0cb1cda72a989d92d813e487cdff59f629aa3fDale Ghent /* Check each bandwidth group for rule violation */
dc0cb1cda72a989d92d813e487cdff59f629aa3fDale Ghent for (j = 0; j < IXGBE_DCB_MAX_BW_GROUP; j++) {
dc0cb1cda72a989d92d813e487cdff59f629aa3fDale Ghent * Sum of bandwidth percentages of all traffic classes
dc0cb1cda72a989d92d813e487cdff59f629aa3fDale Ghent * within a Bandwidth Group must total 100 except for
dc0cb1cda72a989d92d813e487cdff59f629aa3fDale Ghent * link strict group (zero bandwidth).
dc0cb1cda72a989d92d813e487cdff59f629aa3fDale Ghent if (bw_sum[i][j]) {
dc0cb1cda72a989d92d813e487cdff59f629aa3fDale Ghent * Link strict group should have zero
dc0cb1cda72a989d92d813e487cdff59f629aa3fDale Ghent * bandwidth.
dc0cb1cda72a989d92d813e487cdff59f629aa3fDale Ghent } else if (bw_sum[i][j] != IXGBE_DCB_BW_PERCENT &&
dc0cb1cda72a989d92d813e487cdff59f629aa3fDale Ghent bw_sum[i][j] != 0) {
dc0cb1cda72a989d92d813e487cdff59f629aa3fDale Ghent DEBUGOUT2("DCB error code %d while checking %s settings.\n",
dc0cb1cda72a989d92d813e487cdff59f629aa3fDale Ghent ret_val, (i == IXGBE_DCB_TX_CONFIG) ? "Tx" : "Rx");
dc0cb1cda72a989d92d813e487cdff59f629aa3fDale Ghent * ixgbe_dcb_get_tc_stats - Returns status of each traffic class
dc0cb1cda72a989d92d813e487cdff59f629aa3fDale Ghent * @hw: pointer to hardware structure
dc0cb1cda72a989d92d813e487cdff59f629aa3fDale Ghent * @stats: pointer to statistics structure
dc0cb1cda72a989d92d813e487cdff59f629aa3fDale Ghent * @tc_count: Number of elements in bwg_array.
dc0cb1cda72a989d92d813e487cdff59f629aa3fDale Ghent * This function returns the status data for each of the Traffic Classes in use.
dc0cb1cda72a989d92d813e487cdff59f629aa3fDale Ghents32 ixgbe_dcb_get_tc_stats(struct ixgbe_hw *hw, struct ixgbe_hw_stats *stats,
dc0cb1cda72a989d92d813e487cdff59f629aa3fDale Ghent ret = ixgbe_dcb_get_tc_stats_82598(hw, stats, tc_count);
dc0cb1cda72a989d92d813e487cdff59f629aa3fDale Ghent#if !defined(NO_82599_SUPPORT) || !defined(NO_X540_SUPPORT)
dc0cb1cda72a989d92d813e487cdff59f629aa3fDale Ghent ret = ixgbe_dcb_get_tc_stats_82599(hw, stats, tc_count);
dc0cb1cda72a989d92d813e487cdff59f629aa3fDale Ghent * ixgbe_dcb_get_pfc_stats - Returns CBFC status of each traffic class
dc0cb1cda72a989d92d813e487cdff59f629aa3fDale Ghent * @hw: pointer to hardware structure
dc0cb1cda72a989d92d813e487cdff59f629aa3fDale Ghent * @stats: pointer to statistics structure
dc0cb1cda72a989d92d813e487cdff59f629aa3fDale Ghent * @tc_count: Number of elements in bwg_array.
dc0cb1cda72a989d92d813e487cdff59f629aa3fDale Ghent * This function returns the CBFC status data for each of the Traffic Classes.
dc0cb1cda72a989d92d813e487cdff59f629aa3fDale Ghents32 ixgbe_dcb_get_pfc_stats(struct ixgbe_hw *hw, struct ixgbe_hw_stats *stats,
dc0cb1cda72a989d92d813e487cdff59f629aa3fDale Ghent ret = ixgbe_dcb_get_pfc_stats_82598(hw, stats, tc_count);
dc0cb1cda72a989d92d813e487cdff59f629aa3fDale Ghent#if !defined(NO_82599_SUPPORT) || !defined(NO_X540_SUPPORT)
dc0cb1cda72a989d92d813e487cdff59f629aa3fDale Ghent ret = ixgbe_dcb_get_pfc_stats_82599(hw, stats, tc_count);
dc0cb1cda72a989d92d813e487cdff59f629aa3fDale Ghent * ixgbe_dcb_config_rx_arbiter_cee - Config Rx arbiter
dc0cb1cda72a989d92d813e487cdff59f629aa3fDale Ghent * @hw: pointer to hardware structure
dc0cb1cda72a989d92d813e487cdff59f629aa3fDale Ghent * @dcb_config: pointer to ixgbe_dcb_config structure
dc0cb1cda72a989d92d813e487cdff59f629aa3fDale Ghent * Configure Rx Data Arbiter and credits for each traffic class.
dc0cb1cda72a989d92d813e487cdff59f629aa3fDale Ghents32 ixgbe_dcb_config_rx_arbiter_cee(struct ixgbe_hw *hw,
dc0cb1cda72a989d92d813e487cdff59f629aa3fDale Ghent ixgbe_dcb_unpack_refill_cee(dcb_config, IXGBE_DCB_TX_CONFIG, refill);
dc0cb1cda72a989d92d813e487cdff59f629aa3fDale Ghent ixgbe_dcb_unpack_bwgid_cee(dcb_config, IXGBE_DCB_TX_CONFIG, bwgid);
dc0cb1cda72a989d92d813e487cdff59f629aa3fDale Ghent ixgbe_dcb_unpack_tsa_cee(dcb_config, IXGBE_DCB_TX_CONFIG, tsa);
dc0cb1cda72a989d92d813e487cdff59f629aa3fDale Ghent ixgbe_dcb_unpack_map_cee(dcb_config, IXGBE_DCB_TX_CONFIG, map);
dc0cb1cda72a989d92d813e487cdff59f629aa3fDale Ghent ret = ixgbe_dcb_config_rx_arbiter_82598(hw, refill, max, tsa);
dc0cb1cda72a989d92d813e487cdff59f629aa3fDale Ghent#if !defined(NO_82599_SUPPORT) || !defined(NO_X540_SUPPORT)
dc0cb1cda72a989d92d813e487cdff59f629aa3fDale Ghent ret = ixgbe_dcb_config_rx_arbiter_82599(hw, refill, max, bwgid,
dc0cb1cda72a989d92d813e487cdff59f629aa3fDale Ghent * ixgbe_dcb_config_tx_desc_arbiter_cee - Config Tx Desc arbiter
dc0cb1cda72a989d92d813e487cdff59f629aa3fDale Ghent * @hw: pointer to hardware structure
dc0cb1cda72a989d92d813e487cdff59f629aa3fDale Ghent * @dcb_config: pointer to ixgbe_dcb_config structure
dc0cb1cda72a989d92d813e487cdff59f629aa3fDale Ghent * Configure Tx Descriptor Arbiter and credits for each traffic class.
dc0cb1cda72a989d92d813e487cdff59f629aa3fDale Ghents32 ixgbe_dcb_config_tx_desc_arbiter_cee(struct ixgbe_hw *hw,
dc0cb1cda72a989d92d813e487cdff59f629aa3fDale Ghent ixgbe_dcb_unpack_refill_cee(dcb_config, IXGBE_DCB_TX_CONFIG, refill);
dc0cb1cda72a989d92d813e487cdff59f629aa3fDale Ghent ixgbe_dcb_unpack_bwgid_cee(dcb_config, IXGBE_DCB_TX_CONFIG, bwgid);
dc0cb1cda72a989d92d813e487cdff59f629aa3fDale Ghent ixgbe_dcb_unpack_tsa_cee(dcb_config, IXGBE_DCB_TX_CONFIG, tsa);
dc0cb1cda72a989d92d813e487cdff59f629aa3fDale Ghent ret = ixgbe_dcb_config_tx_desc_arbiter_82598(hw, refill, max,
dc0cb1cda72a989d92d813e487cdff59f629aa3fDale Ghent#if !defined(NO_82599_SUPPORT) || !defined(NO_X540_SUPPORT)
dc0cb1cda72a989d92d813e487cdff59f629aa3fDale Ghent ret = ixgbe_dcb_config_tx_desc_arbiter_82599(hw, refill, max,
dc0cb1cda72a989d92d813e487cdff59f629aa3fDale Ghent * ixgbe_dcb_config_tx_data_arbiter_cee - Config Tx data arbiter
dc0cb1cda72a989d92d813e487cdff59f629aa3fDale Ghent * @hw: pointer to hardware structure
dc0cb1cda72a989d92d813e487cdff59f629aa3fDale Ghent * @dcb_config: pointer to ixgbe_dcb_config structure
dc0cb1cda72a989d92d813e487cdff59f629aa3fDale Ghent * Configure Tx Data Arbiter and credits for each traffic class.
dc0cb1cda72a989d92d813e487cdff59f629aa3fDale Ghents32 ixgbe_dcb_config_tx_data_arbiter_cee(struct ixgbe_hw *hw,
dc0cb1cda72a989d92d813e487cdff59f629aa3fDale Ghent ixgbe_dcb_unpack_refill_cee(dcb_config, IXGBE_DCB_TX_CONFIG, refill);
dc0cb1cda72a989d92d813e487cdff59f629aa3fDale Ghent ixgbe_dcb_unpack_bwgid_cee(dcb_config, IXGBE_DCB_TX_CONFIG, bwgid);
dc0cb1cda72a989d92d813e487cdff59f629aa3fDale Ghent ixgbe_dcb_unpack_tsa_cee(dcb_config, IXGBE_DCB_TX_CONFIG, tsa);
dc0cb1cda72a989d92d813e487cdff59f629aa3fDale Ghent ixgbe_dcb_unpack_map_cee(dcb_config, IXGBE_DCB_TX_CONFIG, map);
dc0cb1cda72a989d92d813e487cdff59f629aa3fDale Ghent ret = ixgbe_dcb_config_tx_data_arbiter_82598(hw, refill, max,
dc0cb1cda72a989d92d813e487cdff59f629aa3fDale Ghent#if !defined(NO_82599_SUPPORT) || !defined(NO_X540_SUPPORT)
dc0cb1cda72a989d92d813e487cdff59f629aa3fDale Ghent ret = ixgbe_dcb_config_tx_data_arbiter_82599(hw, refill, max,
dc0cb1cda72a989d92d813e487cdff59f629aa3fDale Ghent * ixgbe_dcb_config_pfc_cee - Config priority flow control
dc0cb1cda72a989d92d813e487cdff59f629aa3fDale Ghent * @hw: pointer to hardware structure
dc0cb1cda72a989d92d813e487cdff59f629aa3fDale Ghent * @dcb_config: pointer to ixgbe_dcb_config structure
dc0cb1cda72a989d92d813e487cdff59f629aa3fDale Ghent * Configure Priority Flow Control for each traffic class.
dc0cb1cda72a989d92d813e487cdff59f629aa3fDale Ghent ixgbe_dcb_unpack_map_cee(dcb_config, IXGBE_DCB_TX_CONFIG, map);
dc0cb1cda72a989d92d813e487cdff59f629aa3fDale Ghent ixgbe_dcb_unpack_pfc_cee(dcb_config, map, &pfc_en);
dc0cb1cda72a989d92d813e487cdff59f629aa3fDale Ghent#if !defined(NO_82599_SUPPORT) || !defined(NO_X540_SUPPORT)
dc0cb1cda72a989d92d813e487cdff59f629aa3fDale Ghent ret = ixgbe_dcb_config_pfc_82599(hw, pfc_en, map);
dc0cb1cda72a989d92d813e487cdff59f629aa3fDale Ghent * ixgbe_dcb_config_tc_stats - Config traffic class statistics
dc0cb1cda72a989d92d813e487cdff59f629aa3fDale Ghent * @hw: pointer to hardware structure
dc0cb1cda72a989d92d813e487cdff59f629aa3fDale Ghent * Configure queue statistics registers, all queues belonging to same traffic
dc0cb1cda72a989d92d813e487cdff59f629aa3fDale Ghent * class uses a single set of queue statistics counters.
dc0cb1cda72a989d92d813e487cdff59f629aa3fDale Ghents32 ixgbe_dcb_config_tc_stats(struct ixgbe_hw *hw)
dc0cb1cda72a989d92d813e487cdff59f629aa3fDale Ghent#if !defined(NO_82599_SUPPORT) || !defined(NO_X540_SUPPORT)
dc0cb1cda72a989d92d813e487cdff59f629aa3fDale Ghent * ixgbe_dcb_hw_config_cee - Config and enable DCB
dc0cb1cda72a989d92d813e487cdff59f629aa3fDale Ghent * @hw: pointer to hardware structure
dc0cb1cda72a989d92d813e487cdff59f629aa3fDale Ghent * @dcb_config: pointer to ixgbe_dcb_config structure
dc0cb1cda72a989d92d813e487cdff59f629aa3fDale Ghent * Configure dcb settings and enable dcb mode.
dc0cb1cda72a989d92d813e487cdff59f629aa3fDale Ghent /* Unpack CEE standard containers */
dc0cb1cda72a989d92d813e487cdff59f629aa3fDale Ghent ixgbe_dcb_unpack_refill_cee(dcb_config, IXGBE_DCB_TX_CONFIG, refill);
dc0cb1cda72a989d92d813e487cdff59f629aa3fDale Ghent ixgbe_dcb_unpack_bwgid_cee(dcb_config, IXGBE_DCB_TX_CONFIG, bwgid);
dc0cb1cda72a989d92d813e487cdff59f629aa3fDale Ghent ixgbe_dcb_unpack_tsa_cee(dcb_config, IXGBE_DCB_TX_CONFIG, tsa);
dc0cb1cda72a989d92d813e487cdff59f629aa3fDale Ghent ixgbe_dcb_unpack_map_cee(dcb_config, IXGBE_DCB_TX_CONFIG, map);
dc0cb1cda72a989d92d813e487cdff59f629aa3fDale Ghent hw->mac.ops.setup_rxpba(hw, dcb_config->num_tcs.pg_tcs,
dc0cb1cda72a989d92d813e487cdff59f629aa3fDale Ghent ret = ixgbe_dcb_hw_config_82598(hw, dcb_config->link_speed,
dc0cb1cda72a989d92d813e487cdff59f629aa3fDale Ghent#if !defined(NO_82599_SUPPORT) || !defined(NO_X540_SUPPORT)
dc0cb1cda72a989d92d813e487cdff59f629aa3fDale Ghent ret = ixgbe_dcb_hw_config_82599(hw, dcb_config->link_speed,
dc0cb1cda72a989d92d813e487cdff59f629aa3fDale Ghent ixgbe_dcb_unpack_pfc_cee(dcb_config, map, &pfc_en);
dc0cb1cda72a989d92d813e487cdff59f629aa3fDale Ghent/* Helper routines to abstract HW specifics from DCB netlink ops */
dc0cb1cda72a989d92d813e487cdff59f629aa3fDale Ghents32 ixgbe_dcb_config_pfc(struct ixgbe_hw *hw, u8 pfc_en, u8 *map)
dc0cb1cda72a989d92d813e487cdff59f629aa3fDale Ghent#if !defined(NO_82599_SUPPORT) || !defined(NO_X540_SUPPORT)
dc0cb1cda72a989d92d813e487cdff59f629aa3fDale Ghent ret = ixgbe_dcb_config_pfc_82599(hw, pfc_en, map);
dc0cb1cda72a989d92d813e487cdff59f629aa3fDale Ghents32 ixgbe_dcb_hw_config(struct ixgbe_hw *hw, u16 *refill, u16 *max,
dc0cb1cda72a989d92d813e487cdff59f629aa3fDale Ghent ixgbe_dcb_config_rx_arbiter_82598(hw, refill, max, tsa);
dc0cb1cda72a989d92d813e487cdff59f629aa3fDale Ghent ixgbe_dcb_config_tx_desc_arbiter_82598(hw, refill, max, bwg_id,
dc0cb1cda72a989d92d813e487cdff59f629aa3fDale Ghent ixgbe_dcb_config_tx_data_arbiter_82598(hw, refill, max, bwg_id,
dc0cb1cda72a989d92d813e487cdff59f629aa3fDale Ghent#if !defined(NO_82599_SUPPORT) || !defined(NO_X540_SUPPORT)
dc0cb1cda72a989d92d813e487cdff59f629aa3fDale Ghent ixgbe_dcb_config_rx_arbiter_82599(hw, refill, max, bwg_id,
dc0cb1cda72a989d92d813e487cdff59f629aa3fDale Ghent ixgbe_dcb_config_tx_desc_arbiter_82599(hw, refill, max, bwg_id,