ixgbe_common.c revision dc0cb1cda72a989d92d813e487cdff59f629aa3f
/******************************************************************************
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/*$FreeBSD$*/
#include "ixgbe_common.h"
#include "ixgbe_phy.h"
#include "ixgbe_dcb.h"
#include "ixgbe_dcb_82599.h"
#include "ixgbe_api.h"
/**
* ixgbe_init_ops_generic - Inits function ptrs
* @hw: pointer to the hardware structure
*
* Initialize the function pointers.
**/
{
DEBUGFUNC("ixgbe_init_ops_generic");
/* EEPROM */
/* If EEPROM is valid (bit 8 = 1), use EERD otherwise use bit bang */
if (eec & IXGBE_EEC_PRES) {
} else {
}
/* MAC */
/* LEDs */
/* RAR, Multicast, VLAN */
/* Flow Control */
/* Link */
return IXGBE_SUCCESS;
}
/**
* ixgbe_device_supports_autoneg_fc - Check if device supports autonegotiation
* of flow control
* @hw: pointer to hardware structure
*
* This function returns TRUE if the device supports flow control
* autonegotiation, and FALSE if it does not.
*
**/
{
bool link_up;
DEBUGFUNC("ixgbe_device_supports_autoneg_fc");
case ixgbe_media_type_fiber:
/* if link is down, assume supported */
if (link_up)
else
break;
break;
case ixgbe_media_type_copper:
/* only some copper devices support flow control autoneg */
case IXGBE_DEV_ID_X540T:
case IXGBE_DEV_ID_X540T1:
case IXGBE_DEV_ID_X540_BYPASS:
case IXGBE_DEV_ID_X550T:
case IXGBE_DEV_ID_X550T1:
break;
default:
}
default:
break;
}
if (!supported) {
"Device %x does not support flow control autoneg",
}
return supported;
}
/**
* ixgbe_setup_fc_generic - Set up flow control
* @hw: pointer to hardware structure
*
* Called at init time to set up flow control.
**/
{
DEBUGFUNC("ixgbe_setup_fc_generic");
/* Validate the requested mode */
"ixgbe_fc_rx_pause not valid in strict IEEE mode\n");
goto out;
}
/*
* 10gig parts do not have a word in the EEPROM to determine the
* default flow control setting, so we explicitly set it to full.
*/
/*
* Set up the 1G and 10G flow control advertisement registers so the
* HW will be able to do fc autoneg once the cable is plugged in. If
* we link at 10G, the 1G advertisement is harmless and vice versa.
*/
/* some MAC's need RMW protection on AUTOC */
if (ret_val != IXGBE_SUCCESS)
goto out;
/* only backplane uses autoc so fall though */
case ixgbe_media_type_fiber:
break;
case ixgbe_media_type_copper:
break;
default:
break;
}
/*
* The possible values of fc.requested_mode are:
* 0: Flow control is completely disabled
* 1: Rx flow control is enabled (we can receive pause frames,
* but not send pause frames).
* 2: Tx flow control is enabled (we can send pause frames but
* we do not support receiving pause frames).
* 3: Both Rx and Tx flow control (symmetric) are enabled.
* other: Invalid.
*/
case ixgbe_fc_none:
/* Flow control completely disabled by software override. */
reg_bp &= ~(IXGBE_AUTOC_SYM_PAUSE |
break;
case ixgbe_fc_tx_pause:
/*
* Tx Flow control is enabled, and Rx Flow control is
* disabled by software override.
*/
}
break;
case ixgbe_fc_rx_pause:
/*
* Rx Flow control is enabled and Tx Flow control is
* disabled by software override. Since there really
* isn't a way to advertise that we are capable of RX
* Pause ONLY, we will advertise that we support both
* symmetric and asymmetric Rx PAUSE, as such we fall
* through to the fc_full statement. Later, we will
* disable the adapter's ability to send PAUSE frames.
*/
case ixgbe_fc_full:
/* Flow control (both Rx and Tx) is enabled by SW override. */
break;
default:
"Flow control param set incorrectly\n");
goto out;
break;
}
/*
* Enable auto-negotiation between the MAC & PHY;
* the MAC will advertise clause 37 flow control.
*/
/* Disable AN timeout */
}
/*
* AUTOC restart handles negotiation of 1G and 10G on backplane
* and copper. There is no need to set the PCS1GCTL register.
*
*/
if (ret_val)
goto out;
}
out:
return ret_val;
}
/**
* @hw: pointer to hardware structure
*
* Starts the hardware by filling the bus info structure and media type, clears
* all on chip counters, initializes receive address registers, multicast
* table, VLAN filter table, calls routine to set up link and flow control
* settings, and leaves transmit and receive units disabled and uninitialized
**/
{
DEBUGFUNC("ixgbe_start_hw_generic");
/* Set the media type */
/* PHY ops initialization must be done in reset_hw() */
/* Clear the VLAN filter table */
/* Clear statistics registers */
/* Set No Snoop Disable */
/* Setup flow control */
if (ret_val != IXGBE_SUCCESS)
goto out;
/* Clear adapter stopped flag */
out:
return ret_val;
}
/**
* ixgbe_start_hw_gen2 - Init sequence for common device family
* @hw: pointer to hw structure
*
* Performs the init sequence common to the second generation
* of 10 GbE devices.
* Devices in the second generation:
* 82599
* X540
**/
{
u32 i;
/* Clear the rate limiters */
}
/* Disable relaxed ordering */
}
}
return IXGBE_SUCCESS;
}
/**
* ixgbe_init_hw_generic - Generic hardware initialization
* @hw: pointer to hardware structure
*
* Initialize the hardware by resetting the hardware, filling the bus info
* structure and media type, clears all on chip counters, initializes receive
* address registers, multicast table, VLAN filter table, calls routine to set
* up link and flow control settings, and leaves transmit and receive units
* disabled and uninitialized
**/
{
DEBUGFUNC("ixgbe_init_hw_generic");
/* Reset the hardware */
if (status == IXGBE_SUCCESS) {
/* Start the HW */
}
return status;
}
/**
* ixgbe_clear_hw_cntrs_generic - Generic clear hardware counters
* @hw: pointer to hardware structure
*
* Clears all hardware statistics counters by reading them from the hardware
* Statistics counters are clear on read.
**/
{
u16 i = 0;
DEBUGFUNC("ixgbe_clear_hw_cntrs_generic");
for (i = 0; i < 8; i++)
} else {
}
for (i = 0; i < 8; i++) {
} else {
}
}
for (i = 0; i < 8; i++)
for (i = 0; i < 8; i++)
for (i = 0; i < 16; i++) {
} else {
}
}
IXGBE_MDIO_PCS_DEV_TYPE, &i);
IXGBE_MDIO_PCS_DEV_TYPE, &i);
IXGBE_MDIO_PCS_DEV_TYPE, &i);
IXGBE_MDIO_PCS_DEV_TYPE, &i);
}
return IXGBE_SUCCESS;
}
/**
* ixgbe_read_pba_string_generic - Reads part number string from EEPROM
* @hw: pointer to hardware structure
* @pba_num: stores the part number string from the EEPROM
* @pba_num_size: part number string buffer length
*
* Reads the part number string from the EEPROM.
**/
{
DEBUGFUNC("ixgbe_read_pba_string_generic");
DEBUGOUT("PBA string buffer was null\n");
return IXGBE_ERR_INVALID_ARGUMENT;
}
if (ret_val) {
DEBUGOUT("NVM Read Error\n");
return ret_val;
}
if (ret_val) {
DEBUGOUT("NVM Read Error\n");
return ret_val;
}
/*
* if data is not ptr guard the PBA must be in legacy format which
* means pba_ptr is actually our second data word for the PBA number
* and we can decode it into an ascii string
*/
if (data != IXGBE_PBANUM_PTR_GUARD) {
DEBUGOUT("NVM PBA number is not stored as string\n");
/* we will need 11 characters to store the PBA */
if (pba_num_size < 11) {
DEBUGOUT("PBA string buffer too small\n");
return IXGBE_ERR_NO_SPACE;
}
/* extract hex string from data and pba_ptr */
pba_num[7] = 0;
/* put a null character on the end of our string */
/* switch all the data but the '-' to hex char */
}
return IXGBE_SUCCESS;
}
if (ret_val) {
DEBUGOUT("NVM Read Error\n");
return ret_val;
}
DEBUGOUT("NVM PBA number section invalid length\n");
return IXGBE_ERR_PBA_SECTION;
}
/* check if pba_num buffer is big enough */
DEBUGOUT("PBA string buffer too small\n");
return IXGBE_ERR_NO_SPACE;
}
/* trim pba length from start of string */
pba_ptr++;
length--;
if (ret_val) {
DEBUGOUT("NVM Read Error\n");
return ret_val;
}
}
return IXGBE_SUCCESS;
}
/**
* ixgbe_read_pba_num_generic - Reads part number from EEPROM
* @hw: pointer to hardware structure
* @pba_num: stores the part number from the EEPROM
*
* Reads the part number from the EEPROM.
**/
{
DEBUGFUNC("ixgbe_read_pba_num_generic");
if (ret_val) {
DEBUGOUT("NVM Read Error\n");
return ret_val;
} else if (data == IXGBE_PBANUM_PTR_GUARD) {
DEBUGOUT("NVM Not supported\n");
return IXGBE_NOT_IMPLEMENTED;
}
if (ret_val) {
DEBUGOUT("NVM Read Error\n");
return ret_val;
}
return IXGBE_SUCCESS;
}
/**
* ixgbe_read_pba_raw
* @hw: pointer to the HW structure
* @eeprom_buf: optional pointer to EEPROM image
* @eeprom_buf_size: size of EEPROM image in words
* @max_pba_block_size: PBA block size limit
* @pba: pointer to output PBA structure
*
* Reads PBA from EEPROM image when eeprom_buf is not NULL.
* Reads PBA from physical EEPROM device when eeprom_buf is NULL.
*
**/
{
return IXGBE_ERR_PARAM;
if (eeprom_buf == NULL) {
if (ret_val)
return ret_val;
} else {
if (eeprom_buf_size > IXGBE_PBANUM1_PTR) {
} else {
return IXGBE_ERR_PARAM;
}
}
return IXGBE_ERR_PARAM;
if (ret_val)
return ret_val;
if (pba_block_size > max_pba_block_size)
return IXGBE_ERR_PARAM;
if (eeprom_buf == NULL) {
if (ret_val)
return ret_val;
} else {
pba_block_size)) {
pba_block_size * sizeof(u16));
} else {
return IXGBE_ERR_PARAM;
}
}
}
return IXGBE_SUCCESS;
}
/**
* ixgbe_write_pba_raw
* @hw: pointer to the HW structure
* @eeprom_buf: optional pointer to EEPROM image
* @eeprom_buf_size: size of EEPROM image in words
* @pba: pointer to PBA structure
*
* Writes PBA to EEPROM image when eeprom_buf is not NULL.
* Writes PBA to physical EEPROM device when eeprom_buf is NULL.
*
**/
{
return IXGBE_ERR_PARAM;
if (eeprom_buf == NULL) {
if (ret_val)
return ret_val;
} else {
if (eeprom_buf_size > IXGBE_PBANUM1_PTR) {
} else {
return IXGBE_ERR_PARAM;
}
}
return IXGBE_ERR_PARAM;
if (eeprom_buf == NULL) {
if (ret_val)
return ret_val;
} else {
} else {
return IXGBE_ERR_PARAM;
}
}
}
return IXGBE_SUCCESS;
}
/**
* ixgbe_get_pba_block_size
* @hw: pointer to the HW structure
* @eeprom_buf: optional pointer to EEPROM image
* @eeprom_buf_size: size of EEPROM image in words
* @pba_data_size: pointer to output variable
*
* Returns the size of the PBA block in words. Function operates on EEPROM
* image if the eeprom_buf pointer is not NULL otherwise it accesses physical
* EEPROM device.
*
**/
{
DEBUGFUNC("ixgbe_get_pba_block_size");
if (eeprom_buf == NULL) {
&pba_word[0]);
if (ret_val)
return ret_val;
} else {
if (eeprom_buf_size > IXGBE_PBANUM1_PTR) {
} else {
return IXGBE_ERR_PARAM;
}
}
if (pba_word[0] == IXGBE_PBANUM_PTR_GUARD) {
if (eeprom_buf == NULL) {
&length);
if (ret_val)
return ret_val;
} else {
else
return IXGBE_ERR_PARAM;
}
return IXGBE_ERR_PBA_SECTION;
} else {
/* PBA number in legacy format, there is no PBA Block. */
length = 0;
}
if (pba_block_size != NULL)
*pba_block_size = length;
return IXGBE_SUCCESS;
}
/**
* ixgbe_get_mac_addr_generic - Generic get MAC address
* @hw: pointer to hardware structure
* @mac_addr: Adapter MAC address
*
* Reads the adapter's MAC address from first Receive Address Register (RAR0)
* A reset of the adapter must be performed prior to calling this function
* in order for the MAC address to have been loaded from the EEPROM into RAR0
**/
{
u16 i;
DEBUGFUNC("ixgbe_get_mac_addr_generic");
for (i = 0; i < 4; i++)
for (i = 0; i < 2; i++)
return IXGBE_SUCCESS;
}
/**
* ixgbe_set_pci_config_data_generic - Generic store PCI bus info
* @hw: pointer to hardware structure
* @link_status: the link status returned by the PCI config space
*
* Stores the PCI bus info (speed, width, type) within the ixgbe_hw structure
**/
{
switch (link_status & IXGBE_PCI_LINK_WIDTH) {
case IXGBE_PCI_LINK_WIDTH_1:
break;
case IXGBE_PCI_LINK_WIDTH_2:
break;
case IXGBE_PCI_LINK_WIDTH_4:
break;
case IXGBE_PCI_LINK_WIDTH_8:
break;
default:
break;
}
switch (link_status & IXGBE_PCI_LINK_SPEED) {
break;
break;
break;
default:
break;
}
}
/**
* ixgbe_get_bus_info_generic - Generic set PCI bus info
* @hw: pointer to hardware structure
*
* Gets the PCI bus info (speed, width, type) then calls helper function to
* store this data within the ixgbe_hw structure.
**/
{
DEBUGFUNC("ixgbe_get_bus_info_generic");
/* Get the negotiated link width and speed from PCI config space */
return IXGBE_SUCCESS;
}
/**
* ixgbe_set_lan_id_multi_port_pcie - Set LAN id for PCIe multiple port devices
* @hw: pointer to the HW structure
*
* Determines the LAN function id by reading memory-mapped registers
* and swaps the port value if requested.
**/
{
DEBUGFUNC("ixgbe_set_lan_id_multi_port_pcie");
/* check for a port swap */
if (reg & IXGBE_FACTPS_LFS)
}
/**
* @hw: pointer to hardware structure
*
* Sets the adapter_stopped flag within ixgbe_hw struct. Clears interrupts,
* disables transmit and receive units. The adapter_stopped flag is used by
* the shared code and drivers to determine if the adapter is in a stopped
* state and should not touch the hardware.
**/
{
u16 i;
DEBUGFUNC("ixgbe_stop_adapter_generic");
/*
* Set the adapter_stopped flag so other driver functions stop touching
* the hardware
*/
/* Disable the receive unit */
/* Clear interrupt mask to stop interrupts from being generated */
/* Clear any pending interrupts, flush previous writes */
/* Disable the transmit unit. Each queue must be disabled. */
/* Disable the receive unit by stopping each queue */
}
/* flush all queues disables */
msec_delay(2);
/*
* Prevent the PCI-E bus from hanging by disabling PCI-E master
* access and verify no pending requests
*/
return ixgbe_disable_pcie_master(hw);
}
/**
* ixgbe_led_on_generic - Turns on the software controllable LEDs.
* @hw: pointer to hardware structure
* @index: led number to turn on
**/
{
DEBUGFUNC("ixgbe_led_on_generic");
/* To turn on the LED, set mode to ON. */
return IXGBE_SUCCESS;
}
/**
* ixgbe_led_off_generic - Turns off the software controllable LEDs.
* @hw: pointer to hardware structure
* @index: led number to turn off
**/
{
DEBUGFUNC("ixgbe_led_off_generic");
/* To turn off the LED, set mode to OFF. */
return IXGBE_SUCCESS;
}
/**
* ixgbe_init_eeprom_params_generic - Initialize EEPROM params
* @hw: pointer to hardware structure
*
* Initializes the EEPROM parameters ixgbe_eeprom_info within the
* ixgbe_hw struct in order to set up EEPROM access.
**/
{
DEBUGFUNC("ixgbe_init_eeprom_params_generic");
/* Set default semaphore delay to 10ms which is a well
* tested value */
/* Clear EEPROM page size, it will be initialized as needed */
eeprom->word_page_size = 0;
/*
* Check for EEPROM present first.
* If not present leave as none
*/
if (eec & IXGBE_EEC_PRES) {
/*
* SPI EEPROM is assumed here. This code would need to
* change if a future EEPROM is not SPI.
*/
}
if (eec & IXGBE_EEC_ADDR_SIZE)
else
DEBUGOUT3("Eeprom params: type = %d, size = %d, address bits: "
}
return IXGBE_SUCCESS;
}
/**
* ixgbe_write_eeprom_buffer_bit_bang_generic - Write EEPROM using bit-bang
* @hw: pointer to hardware structure
* @offset: offset within the EEPROM to write
* @words: number of word(s)
* @data: 16 bit word(s) to write to EEPROM
*
* Reads 16 bit word(s) from EEPROM through bit-bang method
**/
{
DEBUGFUNC("ixgbe_write_eeprom_buffer_bit_bang_generic");
if (words == 0) {
goto out;
}
goto out;
}
/*
* The EEPROM page size cannot be queried from the chip. We do lazy
* initialization. It is worth to do that when we write large buffer.
*/
/*
* We cannot hold synchronization semaphores for too long
* to avoid other entity starvation. However it is more efficient
* to read in bursts than synchronizing access for each word.
*/
for (i = 0; i < words; i += IXGBE_EEPROM_RD_BUFFER_MAX_COUNT) {
IXGBE_EEPROM_RD_BUFFER_MAX_COUNT : (words - i);
if (status != IXGBE_SUCCESS)
break;
}
out:
return status;
}
/**
* ixgbe_write_eeprom_buffer_bit_bang - Writes 16 bit word(s) to EEPROM
* @hw: pointer to hardware structure
* @offset: offset within the EEPROM to be written to
* @words: number of word(s)
* @data: 16 bit word(s) to be written to the EEPROM
*
* If ixgbe_eeprom_update_checksum is not called after this function, the
* EEPROM will most likely contain an invalid checksum.
**/
{
u16 i;
DEBUGFUNC("ixgbe_write_eeprom_buffer_bit_bang");
/* Prepare the EEPROM for writing */
if (status == IXGBE_SUCCESS) {
}
}
if (status == IXGBE_SUCCESS) {
for (i = 0; i < words; i++) {
/* Send the WRITE ENABLE command (8 bit opcode ) */
/*
* Some SPI eeproms use the 8th address bit embedded
* in the opcode
*/
((offset + i) >= 128))
/* Send the Write command (8-bit opcode + addr) */
/* Send the data in burst via SPI*/
do {
if (page_size == 0)
break;
/* do not wrap around page */
(page_size - 1))
break;
} while (++i < words);
msec_delay(10);
}
/* Done with writing - release the EEPROM */
}
return status;
}
/**
* ixgbe_write_eeprom_generic - Writes 16 bit value to EEPROM
* @hw: pointer to hardware structure
* @offset: offset within the EEPROM to be written to
* @data: 16 bit word to be written to the EEPROM
*
* If ixgbe_eeprom_update_checksum is not called after this function, the
* EEPROM will most likely contain an invalid checksum.
**/
{
DEBUGFUNC("ixgbe_write_eeprom_generic");
goto out;
}
out:
return status;
}
/**
* ixgbe_read_eeprom_buffer_bit_bang_generic - Read EEPROM using bit-bang
* @hw: pointer to hardware structure
* @offset: offset within the EEPROM to be read
* @data: read 16 bit words(s) from EEPROM
* @words: number of word(s)
*
* Reads 16 bit word(s) from EEPROM through bit-bang method
**/
{
DEBUGFUNC("ixgbe_read_eeprom_buffer_bit_bang_generic");
if (words == 0) {
goto out;
}
goto out;
}
/*
* We cannot hold synchronization semaphores for too long
* to avoid other entity starvation. However it is more efficient
* to read in bursts than synchronizing access for each word.
*/
for (i = 0; i < words; i += IXGBE_EEPROM_RD_BUFFER_MAX_COUNT) {
IXGBE_EEPROM_RD_BUFFER_MAX_COUNT : (words - i);
if (status != IXGBE_SUCCESS)
break;
}
out:
return status;
}
/**
* ixgbe_read_eeprom_buffer_bit_bang - Read EEPROM using bit-bang
* @hw: pointer to hardware structure
* @offset: offset within the EEPROM to be read
* @words: number of word(s)
* @data: read 16 bit word(s) from EEPROM
*
* Reads 16 bit word(s) from EEPROM through bit-bang method
**/
{
u16 i;
DEBUGFUNC("ixgbe_read_eeprom_buffer_bit_bang");
/* Prepare the EEPROM for reading */
if (status == IXGBE_SUCCESS) {
}
}
if (status == IXGBE_SUCCESS) {
for (i = 0; i < words; i++) {
/*
* Some SPI eeproms use the 8th address bit embedded
* in the opcode
*/
((offset + i) >= 128))
/* Send the READ command (opcode + addr) */
/* Read the data. */
}
/* End this read operation */
}
return status;
}
/**
* ixgbe_read_eeprom_bit_bang_generic - Read EEPROM word using bit-bang
* @hw: pointer to hardware structure
* @offset: offset within the EEPROM to be read
* @data: read 16 bit value from EEPROM
*
* Reads 16 bit value from EEPROM through bit-bang method
**/
{
DEBUGFUNC("ixgbe_read_eeprom_bit_bang_generic");
goto out;
}
out:
return status;
}
/**
* ixgbe_read_eerd_buffer_generic - Read EEPROM word(s) using EERD
* @hw: pointer to hardware structure
* @offset: offset of word in the EEPROM to read
* @words: number of word(s)
* @data: 16 bit word(s) from the EEPROM
*
* Reads a 16 bit word(s) from the EEPROM using the EERD register.
**/
{
u32 i;
DEBUGFUNC("ixgbe_read_eerd_buffer_generic");
if (words == 0) {
goto out;
}
goto out;
}
for (i = 0; i < words; i++) {
if (status == IXGBE_SUCCESS) {
} else {
DEBUGOUT("Eeprom read timed out\n");
goto out;
}
}
out:
return status;
}
/**
* ixgbe_detect_eeprom_page_size_generic - Detect EEPROM page size
* @hw: pointer to hardware structure
* @offset: offset within the EEPROM to be used as a scratch pad
*
* Discover EEPROM page size by writing marching data at given offset.
* This function is called only when we are writing a new large buffer
* at given offset so the data would be overwritten anyway.
**/
{
u16 i;
DEBUGFUNC("ixgbe_detect_eeprom_page_size_generic");
for (i = 0; i < IXGBE_EEPROM_PAGE_SIZE_MAX; i++)
data[i] = i;
if (status != IXGBE_SUCCESS)
goto out;
if (status != IXGBE_SUCCESS)
goto out;
/*
* When writing in burst more than the actual page size
* EEPROM address wraps around current page.
*/
DEBUGOUT1("Detected EEPROM page size = %d words.",
out:
return status;
}
/**
* ixgbe_read_eerd_generic - Read EEPROM word using EERD
* @hw: pointer to hardware structure
* @offset: offset of word in the EEPROM to read
* @data: word read from the EEPROM
*
* Reads a 16 bit word from the EEPROM using the EERD register.
**/
{
}
/**
* ixgbe_write_eewr_buffer_generic - Write EEPROM word(s) using EEWR
* @hw: pointer to hardware structure
* @offset: offset of word in the EEPROM to write
* @words: number of word(s)
* @data: word(s) write to the EEPROM
*
* Write a 16 bit word(s) to the EEPROM using the EEWR register.
**/
{
u16 i;
DEBUGFUNC("ixgbe_write_eewr_generic");
if (words == 0) {
goto out;
}
goto out;
}
for (i = 0; i < words; i++) {
(data[i] << IXGBE_EEPROM_RW_REG_DATA) |
if (status != IXGBE_SUCCESS) {
DEBUGOUT("Eeprom write EEWR timed out\n");
goto out;
}
if (status != IXGBE_SUCCESS) {
DEBUGOUT("Eeprom write EEWR timed out\n");
goto out;
}
}
out:
return status;
}
/**
* ixgbe_write_eewr_generic - Write EEPROM word using EEWR
* @hw: pointer to hardware structure
* @offset: offset of word in the EEPROM to write
* @data: word write to the EEPROM
*
* Write a 16 bit word to the EEPROM using the EEWR register.
**/
{
}
/**
* ixgbe_poll_eerd_eewr_done - Poll EERD read or EEWR write status
* @hw: pointer to hardware structure
* @ee_reg: EEPROM flag for polling
*
* Polls the status bit (bit 1) of the EERD or EEWR to determine when the
* read or write is done respectively.
**/
{
u32 i;
DEBUGFUNC("ixgbe_poll_eerd_eewr_done");
for (i = 0; i < IXGBE_EERD_EEWR_ATTEMPTS; i++) {
if (ee_reg == IXGBE_NVM_POLL_READ)
else
if (reg & IXGBE_EEPROM_RW_REG_DONE) {
break;
}
usec_delay(5);
}
if (i == IXGBE_EERD_EEWR_ATTEMPTS)
return status;
}
/**
* ixgbe_acquire_eeprom - Acquire EEPROM using bit-bang
* @hw: pointer to hardware structure
*
* Prepares EEPROM for access using bit-bang method. This function should
* be called before issuing a command to the EEPROM.
**/
{
u32 i;
DEBUGFUNC("ixgbe_acquire_eeprom");
!= IXGBE_SUCCESS)
if (status == IXGBE_SUCCESS) {
/* Request EEPROM Access */
eec |= IXGBE_EEC_REQ;
for (i = 0; i < IXGBE_EEPROM_GRANT_ATTEMPTS; i++) {
if (eec & IXGBE_EEC_GNT)
break;
usec_delay(5);
}
/* Release if grant not acquired */
if (!(eec & IXGBE_EEC_GNT)) {
eec &= ~IXGBE_EEC_REQ;
DEBUGOUT("Could not acquire EEPROM grant\n");
}
if (status == IXGBE_SUCCESS) {
/* Clear CS and SK */
usec_delay(1);
}
}
return status;
}
/**
* ixgbe_get_eeprom_semaphore - Get hardware semaphore
* @hw: pointer to hardware structure
*
* Sets the hardware semaphores so EEPROM access can occur for bit-bang method
**/
{
u32 i;
DEBUGFUNC("ixgbe_get_eeprom_semaphore");
/* Get SMBI software semaphore between device drivers first */
for (i = 0; i < timeout; i++) {
/*
* If the SMBI bit is 0 when we read it, then the bit will be
* set and we have the semaphore
*/
if (!(swsm & IXGBE_SWSM_SMBI)) {
break;
}
usec_delay(50);
}
if (i == timeout) {
DEBUGOUT("Driver can't access the Eeprom - SMBI Semaphore "
"not granted.\n");
/*
* this release is particularly important because our attempts
* above to get the semaphore may have succeeded, and if there
* was a timeout, we should unconditionally clear the semaphore
* bits to free the driver to make progress
*/
usec_delay(50);
/*
* one last try
* If the SMBI bit is 0 when we read it, then the bit will be
* set and we have the semaphore
*/
if (!(swsm & IXGBE_SWSM_SMBI))
}
if (status == IXGBE_SUCCESS) {
for (i = 0; i < timeout; i++) {
/* Set the SW EEPROM semaphore bit to request access */
/*
* If we set the bit successfully then we got the
* semaphore.
*/
if (swsm & IXGBE_SWSM_SWESMBI)
break;
usec_delay(50);
}
/*
* Release semaphores and return error if SW EEPROM semaphore
* was not granted because we don't have access to the EEPROM
*/
if (i >= timeout) {
"SWESMBI Software EEPROM semaphore not granted.\n");
}
} else {
"Software semaphore SMBI between device drivers "
"not granted.\n");
}
return status;
}
/**
* ixgbe_release_eeprom_semaphore - Release hardware semaphore
* @hw: pointer to hardware structure
*
* This function clears hardware semaphore bits.
**/
{
DEBUGFUNC("ixgbe_release_eeprom_semaphore");
/* Release both semaphores by writing 0 to the bits SWESMBI and SMBI */
}
/**
* ixgbe_ready_eeprom - Polls for EEPROM ready
* @hw: pointer to hardware structure
**/
{
u16 i;
DEBUGFUNC("ixgbe_ready_eeprom");
/*
* Read "Status Register" repeatedly until the LSB is cleared. The
* EEPROM will signal that the command has been completed by clearing
* bit 0 of the internal status register. If it's not cleared within
* 5 milliseconds, then error out.
*/
for (i = 0; i < IXGBE_EEPROM_MAX_RETRY_SPI; i += 5) {
if (!(spi_stat_reg & IXGBE_EEPROM_STATUS_RDY_SPI))
break;
usec_delay(5);
}
/*
* On some parts, SPI write time could vary from 0-20mSec on 3.3V
* devices (and only 0-5mSec on 5V devices)
*/
if (i >= IXGBE_EEPROM_MAX_RETRY_SPI) {
DEBUGOUT("SPI EEPROM Status error\n");
}
return status;
}
/**
* ixgbe_standby_eeprom - Returns EEPROM to a "standby" state
* @hw: pointer to hardware structure
**/
{
DEBUGFUNC("ixgbe_standby_eeprom");
/* Toggle CS to flush commands */
eec |= IXGBE_EEC_CS;
usec_delay(1);
eec &= ~IXGBE_EEC_CS;
usec_delay(1);
}
/**
* ixgbe_shift_out_eeprom_bits - Shift data bits out to the EEPROM.
* @hw: pointer to hardware structure
* @data: data to send to the EEPROM
* @count: number of bits to shift out
**/
{
u32 i;
DEBUGFUNC("ixgbe_shift_out_eeprom_bits");
/*
* Mask is used to shift "count" bits of "data" out to the EEPROM
* one bit at a time. Determine the starting bit based on count
*/
for (i = 0; i < count; i++) {
/*
* A "1" is shifted out to the EEPROM by setting bit "DI" to a
* "1", and then raising and then lowering the clock (the SK
* bit controls the clock input to the EEPROM). A "0" is
* shifted out to the EEPROM by setting "DI" to "0" and then
* raising and then lowering the clock.
*/
eec |= IXGBE_EEC_DI;
else
eec &= ~IXGBE_EEC_DI;
usec_delay(1);
/*
* Shift mask to signify next bit of data to shift in to the
* EEPROM
*/
}
/* We leave the "DI" bit set to "0" when we leave this routine. */
eec &= ~IXGBE_EEC_DI;
}
/**
* ixgbe_shift_in_eeprom_bits - Shift data bits in from the EEPROM
* @hw: pointer to hardware structure
**/
{
u32 i;
DEBUGFUNC("ixgbe_shift_in_eeprom_bits");
/*
* In order to read a register from the EEPROM, we need to shift
* 'count' bits in from the EEPROM. Bits are "shifted in" by raising
* the clock input to the EEPROM (setting the SK bit), and then reading
* the value of the "DO" bit. During this "shifting in" process the
* "DI" bit should always be clear.
*/
for (i = 0; i < count; i++) {
eec &= ~(IXGBE_EEC_DI);
if (eec & IXGBE_EEC_DO)
data |= 1;
}
return data;
}
/**
* ixgbe_raise_eeprom_clk - Raises the EEPROM's clock input.
* @hw: pointer to hardware structure
* @eec: EEC register's current value
**/
{
DEBUGFUNC("ixgbe_raise_eeprom_clk");
/*
* Raise the clock input to the EEPROM
* (setting the SK bit), then delay
*/
usec_delay(1);
}
/**
* ixgbe_lower_eeprom_clk - Lowers the EEPROM's clock input.
* @hw: pointer to hardware structure
* @eecd: EECD's current value
**/
{
DEBUGFUNC("ixgbe_lower_eeprom_clk");
/*
* Lower the clock input to the EEPROM (clearing the SK bit), then
* delay
*/
usec_delay(1);
}
/**
* ixgbe_release_eeprom - Release EEPROM, release semaphores
* @hw: pointer to hardware structure
**/
{
DEBUGFUNC("ixgbe_release_eeprom");
usec_delay(1);
/* Stop requesting EEPROM access */
eec &= ~IXGBE_EEC_REQ;
/* Delay before attempt to obtain semaphore again to allow FW access */
}
/**
* ixgbe_calc_eeprom_checksum_generic - Calculates and returns the checksum
* @hw: pointer to hardware structure
*
* Returns a negative error code on error, or the 16-bit checksum
**/
{
u16 i;
u16 j;
DEBUGFUNC("ixgbe_calc_eeprom_checksum_generic");
/* Include 0x0-0x3F in the checksum */
for (i = 0; i < IXGBE_EEPROM_CHECKSUM; i++) {
DEBUGOUT("EEPROM read failed\n");
return IXGBE_ERR_EEPROM;
}
}
/* Include all data from pointers except for the fw pointer */
for (i = IXGBE_PCIE_ANALOG_PTR; i < IXGBE_FW_PTR; i++) {
DEBUGOUT("EEPROM read failed\n");
return IXGBE_ERR_EEPROM;
}
/* If the pointer seems invalid */
continue;
DEBUGOUT("EEPROM read failed\n");
return IXGBE_ERR_EEPROM;
}
continue;
DEBUGOUT("EEPROM read failed\n");
return IXGBE_ERR_EEPROM;
}
}
}
}
/**
* ixgbe_validate_eeprom_checksum_generic - Validate EEPROM checksum
* @hw: pointer to hardware structure
* @checksum_val: calculated checksum
*
* Performs checksum calculation and validates the EEPROM checksum. If the
* caller does not need checksum_val, the value can be NULL.
**/
{
u16 read_checksum = 0;
DEBUGFUNC("ixgbe_validate_eeprom_checksum_generic");
/* Read the first word from the EEPROM. If this times out or fails, do
* not continue or we could be in for a very long wait while every
* EEPROM read fails
*/
if (status) {
DEBUGOUT("EEPROM read failed\n");
return status;
}
if (status < 0)
return status;
if (status) {
DEBUGOUT("EEPROM read failed\n");
return status;
}
/* Verify read checksum from EEPROM is the same as
* calculated checksum
*/
if (read_checksum != checksum)
/* If the user cares, return the calculated checksum */
if (checksum_val)
*checksum_val = checksum;
return status;
}
/**
* ixgbe_update_eeprom_checksum_generic - Updates the EEPROM checksum
* @hw: pointer to hardware structure
**/
{
DEBUGFUNC("ixgbe_update_eeprom_checksum_generic");
/* Read the first word from the EEPROM. If this times out or fails, do
* not continue or we could be in for a very long wait while every
* EEPROM read fails
*/
if (status) {
DEBUGOUT("EEPROM read failed\n");
return status;
}
if (status < 0)
return status;
return status;
}
/**
* ixgbe_validate_mac_addr - Validate MAC address
* @mac_addr: pointer to MAC address.
*
* Tests a MAC address to ensure it is a valid Individual Address
**/
{
DEBUGFUNC("ixgbe_validate_mac_addr");
/* Make sure it is not a multicast address */
if (IXGBE_IS_MULTICAST(mac_addr)) {
DEBUGOUT("MAC address is multicast\n");
/* Not a broadcast address */
} else if (IXGBE_IS_BROADCAST(mac_addr)) {
DEBUGOUT("MAC address is broadcast\n");
/* Reject the zero address */
DEBUGOUT("MAC address is all zeros\n");
}
return status;
}
/**
* ixgbe_set_rar_generic - Set Rx address register
* @hw: pointer to hardware structure
* @index: Receive address register to write
* @addr: Address to put into receive address register
* @vmdq: VMDq "set" or "pool" index
* @enable_addr: set flag that address is active
*
* Puts an ethernet address into a receive address register.
**/
{
DEBUGFUNC("ixgbe_set_rar_generic");
/* Make sure we are using a valid rar index range */
if (index >= rar_entries) {
"RAR index %d is out of range.\n", index);
return IXGBE_ERR_INVALID_ARGUMENT;
}
/* setup VMDq pool selection before this RAR gets enabled */
/*
* HW expects these in little endian so we reverse the byte
* order from network order (big endian) to little endian
*/
/*
* Some parts put the VMDq setting in the extra RAH bits,
* so save everything except the lower 16 bits that hold part
* of the address and the address valid bit.
*/
if (enable_addr != 0)
rar_high |= IXGBE_RAH_AV;
return IXGBE_SUCCESS;
}
/**
* ixgbe_clear_rar_generic - Remove Rx address register
* @hw: pointer to hardware structure
* @index: Receive address register to write
*
* Clears an ethernet address from a receive address register.
**/
{
DEBUGFUNC("ixgbe_clear_rar_generic");
/* Make sure we are using a valid rar index range */
if (index >= rar_entries) {
"RAR index %d is out of range.\n", index);
return IXGBE_ERR_INVALID_ARGUMENT;
}
/*
* Some parts put the VMDq setting in the extra RAH bits,
* so save everything except the lower 16 bits that hold part
* of the address and the address valid bit.
*/
return IXGBE_SUCCESS;
}
/**
* ixgbe_init_rx_addrs_generic - Initializes receive address filters.
* @hw: pointer to hardware structure
*
* Places the MAC address in receive address register 0 and clears the rest
* of the receive address registers. Clears the multicast table. Assumes
* the receiver is in reset when the routine is called.
**/
{
u32 i;
DEBUGFUNC("ixgbe_init_rx_addrs_generic");
/*
* If the current mac address is valid, assume it is a software override
* to the permanent address.
* Otherwise, use the permanent address from the eeprom.
*/
/* Get the MAC address from the RAR0 for later reference */
DEBUGOUT3(" Keeping Current RAR0 Addr =%.2X %.2X %.2X ",
} else {
/* Setup the receive address. */
DEBUGOUT("Overriding MAC Address in RAR[0]\n");
DEBUGOUT3(" New MAC Addr =%.2X %.2X %.2X ",
}
/* Zero out the other receive addresses. */
for (i = 1; i < rar_entries; i++) {
}
/* Clear the MTA */
DEBUGOUT(" Clearing MTA\n");
return IXGBE_SUCCESS;
}
/**
* ixgbe_add_uc_addr - Adds a secondary unicast address.
* @hw: pointer to hardware structure
* @addr: new address
*
* Adds it to unused receive address register or goes into promiscuous mode.
**/
{
DEBUGFUNC("ixgbe_add_uc_addr");
DEBUGOUT6(" UC Addr = %.2X %.2X %.2X %.2X %.2X %.2X\n",
/*
* Place this address in the RAR if there is room,
* else put the controller into promiscuous mode
*/
} else {
}
DEBUGOUT("ixgbe_add_uc_addr Complete\n");
}
/**
* ixgbe_update_uc_addr_list_generic - Updates MAC list of secondary addresses
* @hw: pointer to hardware structure
* @addr_list: the list of new addresses
* @addr_count: number of addresses
* @next: iterator function to walk the address list
*
* The given list replaces any existing list. Clears the secondary addrs from
* receive address registers. Uses unused receive address registers for the
* first secondary addresses, and falls back to promiscuous mode as needed.
*
* Drivers using secondary unicast addresses must set user_set_promisc when
* manually putting the device into promiscuous mode.
**/
{
u32 i;
DEBUGFUNC("ixgbe_update_uc_addr_list_generic");
/*
* Clear accounting of old secondary address list,
* don't count RAR[0]
*/
/* Zero out the other receive addresses */
for (i = 0; i < uc_addr_in_use; i++) {
}
/* Add the new addresses */
for (i = 0; i < addr_count; i++) {
DEBUGOUT(" Adding the secondary addresses:\n");
}
/* enable promisc if not already in overflow or set by user */
DEBUGOUT(" Entering address overflow promisc mode\n");
fctrl |= IXGBE_FCTRL_UPE;
}
} else {
/* only disable if set by overflow, not by user */
DEBUGOUT(" Leaving address overflow promisc mode\n");
fctrl &= ~IXGBE_FCTRL_UPE;
}
}
DEBUGOUT("ixgbe_update_uc_addr_list_generic Complete\n");
return IXGBE_SUCCESS;
}
/**
* ixgbe_mta_vector - Determines bit-vector in multicast table to set
* @hw: pointer to hardware structure
* @mc_addr: the multicast address
*
* Extracts the 12 bits, from a multicast address, to determine which
* bit-vector to set in the multicast table. The hardware uses 12 bits, from
* incoming rx multicast addresses, to determine the bit-vector to check in
* the MTA. Which of the 4 combination, of 12-bits, the hardware uses is set
* by the MO field of the MCSTCTRL. The MO field is set during initialization
* to mc_filter_type.
**/
{
DEBUGFUNC("ixgbe_mta_vector");
case 0: /* use bits [47:36] of the address */
break;
case 1: /* use bits [46:35] of the address */
break;
case 2: /* use bits [45:34] of the address */
break;
case 3: /* use bits [43:32] of the address */
break;
default: /* Invalid mc_filter_type */
DEBUGOUT("MC filter type param set incorrectly\n");
ASSERT(0);
break;
}
/* vector can only be 12-bits or boundary will be exceeded */
vector &= 0xFFF;
return vector;
}
/**
* ixgbe_set_mta - Set bit-vector in multicast table
* @hw: pointer to hardware structure
* @hash_value: Multicast address hash value
*
* Sets the bit-vector in the multicast table.
**/
{
DEBUGFUNC("ixgbe_set_mta");
/*
* The MTA is a register array of 128 32-bit registers. It is treated
* like an array of 4096 bits. We want to set bit
* BitArray[vector_value]. So we figure out what register the bit is
* in, read it, OR in the new bit, then write back the new value. The
* register is determined by the upper 7 bits of the vector value and
* the bit within that register are determined by the lower 5 bits of
* the value.
*/
}
/**
* ixgbe_update_mc_addr_list_generic - Updates MAC list of multicast addresses
* @hw: pointer to hardware structure
* @mc_addr_list: the list of new multicast addresses
* @mc_addr_count: number of addresses
* @next: iterator function to walk the multicast address list
* @clear: flag, when set clears the table beforehand
*
* When the clear flag is set, the given list replaces any existing list.
* Hashes the given addresses into the multicast table.
**/
bool clear)
{
u32 i;
DEBUGFUNC("ixgbe_update_mc_addr_list_generic");
/*
* Set the new number of MC addresses that we are being requested to
* use.
*/
/* Clear mta_shadow */
if (clear) {
DEBUGOUT(" Clearing MTA\n");
}
/* Update mta_shadow */
for (i = 0; i < mc_addr_count; i++) {
DEBUGOUT(" Adding the multicast addresses:\n");
}
/* Enable mta */
DEBUGOUT("ixgbe_update_mc_addr_list_generic Complete\n");
return IXGBE_SUCCESS;
}
/**
* ixgbe_enable_mc_generic - Enable multicast address in RAR
* @hw: pointer to hardware structure
*
* Enables multicast address in RAR and the use of the multicast hash table.
**/
{
DEBUGFUNC("ixgbe_enable_mc_generic");
if (a->mta_in_use > 0)
return IXGBE_SUCCESS;
}
/**
* ixgbe_disable_mc_generic - Disable multicast address in RAR
* @hw: pointer to hardware structure
*
* Disables multicast address in RAR and the use of the multicast hash table.
**/
{
DEBUGFUNC("ixgbe_disable_mc_generic");
if (a->mta_in_use > 0)
return IXGBE_SUCCESS;
}
/**
* ixgbe_fc_enable_generic - Enable flow control
* @hw: pointer to hardware structure
*
* Enable flow control according to the current settings.
**/
{
int i;
DEBUGFUNC("ixgbe_fc_enable_generic");
/* Validate the water mark configuration */
goto out;
}
/* Low water mark of zero causes XOFF floods */
for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
DEBUGOUT("Invalid water mark configuration\n");
goto out;
}
}
}
/* Negotiate the fc mode to use */
/* Disable any previous flow control settings */
/*
* The possible values of fc.current_mode are:
* 0: Flow control is completely disabled
* 1: Rx flow control is enabled (we can receive pause frames,
* but not send pause frames).
* 2: Tx flow control is enabled (we can send pause frames but
* we do not support receiving pause frames).
* 3: Both Rx and Tx flow control (symmetric) are enabled.
* other: Invalid.
*/
case ixgbe_fc_none:
/*
* Flow control is disabled by software override or autoneg.
* The code below will actually disable it in the HW.
*/
break;
case ixgbe_fc_rx_pause:
/*
* Rx Flow control is enabled and Tx Flow control is
* disabled by software override. Since there really
* isn't a way to advertise that we are capable of RX
* Pause ONLY, we will advertise that we support both
* symmetric and asymmetric Rx PAUSE. Later, we will
* disable the adapter's ability to send PAUSE frames.
*/
break;
case ixgbe_fc_tx_pause:
/*
* Tx Flow control is enabled, and Rx Flow control is
* disabled by software override.
*/
break;
case ixgbe_fc_full:
/* Flow control (both Rx and Tx) is enabled by SW override. */
break;
default:
"Flow control param set incorrectly\n");
goto out;
break;
}
/* Set 802.3x based flow control settings. */
for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
} else {
/*
* In order to prevent Tx hangs when the internal Tx
* switch is enabled we must set the high water mark
* to the Rx packet buffer size - 24KB. This allows
* the Tx switch to function even under heavy Rx
* workloads.
*/
}
}
/* Configure pause time (2 TCs per register) */
for (i = 0; i < (IXGBE_DCB_MAX_TRAFFIC_CLASS / 2); i++)
/* Configure flow control refresh threshold value */
out:
return ret_val;
}
/**
* ixgbe_negotiate_fc - Negotiate flow control
* @hw: pointer to hardware structure
* @adv_reg: flow control advertised settings
* @lp_reg: link partner's flow control settings
* @adv_sym: symmetric pause bit in advertisement
* @adv_asm: asymmetric pause bit in advertisement
* @lp_sym: symmetric pause bit in link partner advertisement
* @lp_asm: asymmetric pause bit in link partner advertisement
*
* Find the intersection between advertised settings and link partner's
* advertised settings
**/
{
"Local or link partner's advertised flow control "
"settings are NULL. Local: %x, link partner: %x\n",
return IXGBE_ERR_FC_NOT_NEGOTIATED;
}
/*
* Now we need to check if the user selected Rx ONLY
* of pause frames. In this case, we had to advertise
* FULL flow control because we could not advertise RX
* ONLY. Hence, we must now check to see if we need to
* turn OFF the TRANSMISSION of PAUSE frames.
*/
DEBUGOUT("Flow Control = FULL.\n");
} else {
DEBUGOUT("Flow Control=RX PAUSE frames only\n");
}
DEBUGOUT("Flow Control = TX PAUSE frames only.\n");
DEBUGOUT("Flow Control = RX PAUSE frames only.\n");
} else {
DEBUGOUT("Flow Control = NONE.\n");
}
return IXGBE_SUCCESS;
}
/**
* ixgbe_fc_autoneg_fiber - Enable flow control on 1 gig fiber
* @hw: pointer to hardware structure
*
* Enable flow control according on 1 gig fiber.
**/
{
/*
* On multispeed fiber at 1g, bail out if
* - link is up but AN did not complete, or if
* - link is up and AN completed but timed out
*/
if ((!!(linkstat & IXGBE_PCS1GLSTA_AN_COMPLETE) == 0) ||
DEBUGOUT("Auto-Negotiation did not complete or timed out\n");
goto out;
}
out:
return ret_val;
}
/**
* ixgbe_fc_autoneg_backplane - Enable flow control IEEE clause 37
* @hw: pointer to hardware structure
*
* Enable flow control according to IEEE clause 37.
**/
{
/*
* On backplane, bail out if
* - backplane autoneg was not completed, or if
* - we are 82599 and link partner is not AN enabled
*/
if ((links & IXGBE_LINKS_KX_AN_COMP) == 0) {
DEBUGOUT("Auto-Negotiation did not complete\n");
goto out;
}
if ((links2 & IXGBE_LINKS2_AN_SUPPORTED) == 0) {
DEBUGOUT("Link partner is not AN enabled\n");
goto out;
}
}
/*
* Read the 10g AN autoc and LP ability registers and resolve
* local flow control settings accordingly
*/
out:
return ret_val;
}
/**
* ixgbe_fc_autoneg_copper - Enable flow control IEEE clause 37
* @hw: pointer to hardware structure
*
* Enable flow control according to IEEE clause 37.
**/
{
}
/**
* ixgbe_fc_autoneg - Configure flow control
* @hw: pointer to hardware structure
*
* Compares our advertised flow control capabilities to those advertised by
* our link partner, and determines the proper flow control mode to use.
**/
{
bool link_up;
DEBUGFUNC("ixgbe_fc_autoneg");
/*
* AN should have completed when the cable was plugged in.
* Look for reasons to bail out. Bail out if:
* - FC autoneg is disabled, or if
* - link is not up.
*/
"Flow control autoneg is disabled");
goto out;
}
if (!link_up) {
goto out;
}
/* Autoneg flow control on fiber adapters */
case ixgbe_media_type_fiber:
if (speed == IXGBE_LINK_SPEED_1GB_FULL)
break;
/* Autoneg flow control on backplane adapters */
break;
/* Autoneg flow control on copper adapters */
case ixgbe_media_type_copper:
break;
default:
break;
}
out:
if (ret_val == IXGBE_SUCCESS) {
} else {
}
}
/*
* ixgbe_pcie_timeout_poll - Return number of times to poll for completion
* @hw: pointer to hardware structure
*
* System-wide timeout range is encoded in PCIe Device Control2 register.
*
* Add 10% to specified maximum and return the number of times to poll for
* completion timeout, in units of 100 microsec. Never return less than
* 800 = 80 millisec.
*/
{
switch (devctl2) {
break;
break;
case IXGBE_PCIDEVCTRL2_1_2s:
break;
case IXGBE_PCIDEVCTRL2_4_8s:
break;
case IXGBE_PCIDEVCTRL2_17_34s:
break;
case IXGBE_PCIDEVCTRL2_50_100us: /* 100 microsecs */
case IXGBE_PCIDEVCTRL2_1_2ms: /* 2 millisecs */
case IXGBE_PCIDEVCTRL2_16_32ms: /* 32 millisec */
case IXGBE_PCIDEVCTRL2_16_32ms_def: /* 32 millisec default */
default:
break;
}
/* add 10% to spec maximum */
}
/**
* ixgbe_disable_pcie_master - Disable PCI-express master access
* @hw: pointer to hardware structure
*
* Disables PCI-Express master access and verifies there are no pending
* requests. IXGBE_ERR_MASTER_REQUESTS_PENDING is returned if master disable
* bit hasn't caused the master requests to be disabled, else IXGBE_SUCCESS
* is returned signifying master requests disabled.
**/
{
DEBUGFUNC("ixgbe_disable_pcie_master");
/* Always set this bit to ensure any future transactions are blocked */
/* Exit if master requests are blocked */
goto out;
/* Poll for master request bit to clear */
for (i = 0; i < IXGBE_PCI_MASTER_DISABLE_TIMEOUT; i++) {
usec_delay(100);
goto out;
}
/*
* Two consecutive resets are required via CTRL.RST per datasheet
* 5.2.5.3.2 Master Disable. We set a flag to inform the reset routine
* of this need. The first reset prevents new master requests from
* being issued by our device. We then must wait 1usec or more for any
* remaining completions from the PCIe bus to trickle in, and then reset
* again to clear out any effects they may have had on our device.
*/
DEBUGOUT("GIO Master Disable bit didn't clear - requesting resets\n");
goto out;
/*
* Before proceeding, make sure that the PCIe block does not have
* transactions pending.
*/
for (i = 0; i < poll; i++) {
usec_delay(100);
goto out;
goto out;
}
"PCIe transaction pending bit also did not clear.\n");
out:
return status;
}
/**
* ixgbe_acquire_swfw_sync - Acquire SWFW semaphore
* @hw: pointer to hardware structure
* @mask: Mask to specify which semaphore to acquire
*
* Acquires the SWFW semaphore through the GSSR register for the specified
* function (CSR, PHY0, PHY1, EEPROM, Flash)
**/
{
u32 i;
DEBUGFUNC("ixgbe_acquire_swfw_sync");
for (i = 0; i < timeout; i++) {
/*
* SW NVM semaphore bit is used for access to all
* SW_FW_SYNC bits (not just NVM)
*/
if (ixgbe_get_eeprom_semaphore(hw))
return IXGBE_ERR_SWFW_SYNC;
return IXGBE_SUCCESS;
} else {
/* Resource is currently in use by FW or SW */
msec_delay(5);
}
}
/* If time expired clear the bits holding the lock and retry */
msec_delay(5);
return IXGBE_ERR_SWFW_SYNC;
}
/**
* ixgbe_release_swfw_sync - Release SWFW semaphore
* @hw: pointer to hardware structure
* @mask: Mask to specify which semaphore to release
*
* Releases the SWFW semaphore through the GSSR register for the specified
* function (CSR, PHY0, PHY1, EEPROM, Flash)
**/
{
DEBUGFUNC("ixgbe_release_swfw_sync");
}
/**
* ixgbe_disable_sec_rx_path_generic - Stops the receive data path
* @hw: pointer to hardware structure
*
* Stops the receive data path and waits for the HW to internally empty
* the Rx security block
**/
{
#define IXGBE_MAX_SECRX_POLL 40
int i;
int secrxreg;
DEBUGFUNC("ixgbe_disable_sec_rx_path_generic");
for (i = 0; i < IXGBE_MAX_SECRX_POLL; i++) {
break;
else
/* Use interrupt-safe sleep just in case */
usec_delay(1000);
}
/* For informational purposes only */
if (i >= IXGBE_MAX_SECRX_POLL)
DEBUGOUT("Rx unit being enabled before security "
"path fully disabled. Continuing with init.\n");
return IXGBE_SUCCESS;
}
/**
* prot_autoc_read_generic - Hides MAC differences needed for AUTOC read
* @hw: pointer to hardware structure
* @reg_val: Value we read from AUTOC
*
* The default case requires no protection so just to the register read.
*/
{
return IXGBE_SUCCESS;
}
/**
* prot_autoc_write_generic - Hides MAC differences needed for AUTOC write
* @hw: pointer to hardware structure
* @reg_val: value to write to AUTOC
* previous read.
*
* The default case requires no protection so just to the register write.
*/
{
return IXGBE_SUCCESS;
}
/**
* ixgbe_enable_sec_rx_path_generic - Enables the receive data path
* @hw: pointer to hardware structure
*
* Enables the receive data path.
**/
{
int secrxreg;
DEBUGFUNC("ixgbe_enable_sec_rx_path_generic");
return IXGBE_SUCCESS;
}
/**
* ixgbe_enable_rx_dma_generic - Enable the Rx DMA unit
* @hw: pointer to hardware structure
* @regval: register value to write to RXCTRL
*
* Enables the Rx DMA unit
**/
{
DEBUGFUNC("ixgbe_enable_rx_dma_generic");
if (regval & IXGBE_RXCTRL_RXEN)
else
return IXGBE_SUCCESS;
}
/**
* ixgbe_blink_led_start_generic - Blink LED based on index.
* @hw: pointer to hardware structure
* @index: led number to blink
**/
{
ixgbe_link_speed speed = 0;
bool link_up = 0;
DEBUGFUNC("ixgbe_blink_led_start_generic");
/*
* Link must be up to auto-blink the LEDs;
* Force it if link is down.
*/
if (!link_up) {
if (ret_val != IXGBE_SUCCESS)
goto out;
if (ret_val != IXGBE_SUCCESS)
goto out;
msec_delay(10);
}
out:
return ret_val;
}
/**
* ixgbe_blink_led_stop_generic - Stop blinking LED based on index.
* @hw: pointer to hardware structure
* @index: led number to stop blinking
**/
{
DEBUGFUNC("ixgbe_blink_led_stop_generic");
if (ret_val != IXGBE_SUCCESS)
goto out;
autoc_reg &= ~IXGBE_AUTOC_FLU;
if (ret_val != IXGBE_SUCCESS)
goto out;
out:
return ret_val;
}
/**
* ixgbe_get_san_mac_addr_offset - Get SAN MAC address offset from the EEPROM
* @hw: pointer to hardware structure
* @san_mac_offset: SAN MAC address offset
*
* This function will read the EEPROM location for the SAN MAC address
* pointer, and returns the value at that location. This is used in both
* get and set mac_addr routines.
**/
{
DEBUGFUNC("ixgbe_get_san_mac_addr_offset");
/*
* First read the EEPROM pointer to see if the MAC addresses are
* available.
*/
if (ret_val) {
"eeprom at offset %d failed",
}
return ret_val;
}
/**
* ixgbe_get_san_mac_addr_generic - SAN MAC address retrieval from the EEPROM
* @hw: pointer to hardware structure
* @san_mac_addr: SAN MAC address
*
* Reads the SAN MAC address from the EEPROM, if it's available. This is
* per-port, so set_lan_id() must be called before reading the addresses.
* set_lan_id() is called by identify_sfp(), but this cannot be relied
* upon for non-SFP connections, so we must call it here.
**/
{
u8 i;
DEBUGFUNC("ixgbe_get_san_mac_addr_generic");
/*
* First read the EEPROM pointer to see if the MAC addresses are
* available. If they're not, no point in calling set_lan_id() here.
*/
goto san_mac_addr_out;
/* make sure we know which port we need to program */
/* apply the port offset to the address offset */
for (i = 0; i < 3; i++) {
&san_mac_data);
if (ret_val) {
"eeprom read at offset %d failed",
goto san_mac_addr_out;
}
}
return IXGBE_SUCCESS;
/*
* No addresses available in this EEPROM. It's not an
* error though, so just wipe the local address and return.
*/
for (i = 0; i < 6; i++)
san_mac_addr[i] = 0xFF;
return IXGBE_SUCCESS;
}
/**
* ixgbe_set_san_mac_addr_generic - Write the SAN MAC address to the EEPROM
* @hw: pointer to hardware structure
* @san_mac_addr: SAN MAC address
*
* Write a SAN MAC address to the EEPROM.
**/
{
u8 i;
DEBUGFUNC("ixgbe_set_san_mac_addr_generic");
/* Look for SAN mac address pointer. If not defined, return */
return IXGBE_ERR_NO_SAN_ADDR_PTR;
/* Make sure we know which port we need to write */
/* Apply the port offset to the address offset */
for (i = 0; i < 3; i++) {
}
return IXGBE_SUCCESS;
}
/**
* ixgbe_get_pcie_msix_count_generic - Gets MSI-X vector count
* @hw: pointer to hardware structure
*
* Read PCIe configuration space, and get the MSI-X vector count from
* the capabilities table.
**/
{
case ixgbe_mac_82598EB:
break;
case ixgbe_mac_82599EB:
case ixgbe_mac_X540:
case ixgbe_mac_X550:
case ixgbe_mac_X550EM_x:
break;
default:
return msix_count;
}
DEBUGFUNC("ixgbe_get_pcie_msix_count_generic");
msix_count = 0;
/* MSI-X count is zero-based in HW */
msix_count++;
if (msix_count > max_msix_count)
return msix_count;
}
/**
* ixgbe_insert_mac_addr_generic - Find a RAR for this mac address
* @hw: pointer to hardware structure
* @addr: Address to put into receive address register
* @vmdq: VMDq pool to assign
*
* Puts an ethernet address into a receive address register, or
* finds the rar that it is already in; adds to the pool list
**/
{
DEBUGFUNC("ixgbe_insert_mac_addr_generic");
/* swap bytes for HW little endian */
/*
* Either find the mac_id in rar or find the first empty space.
* rar_highwater points to just after the highest currently used
* rar in order to shorten the search. It grows when we add a new
* rar to the top.
*/
if (((IXGBE_RAH_AV & rar_high) == 0)
&& first_empty_rar == NO_EMPTY_RAR_FOUND) {
break; /* found it already in the rars */
}
}
/* already there so just add to the pool bits */
} else if (first_empty_rar != NO_EMPTY_RAR_FOUND) {
/* stick it into first empty RAR slot we found */
/* add it to the top of the list and inc the highwater mark */
return IXGBE_ERR_INVALID_MAC_ADDR;
}
/*
* If we found rar[0], make sure the default pool bit (we use pool 0)
* remains cleared to be sure default pool packets will get delivered
*/
if (rar == 0)
return rar;
}
/**
* ixgbe_clear_vmdq_generic - Disassociate a VMDq pool index from a rx address
* @hw: pointer to hardware struct
* @rar: receive address register index to disassociate
* @vmdq: VMDq pool index to remove from the rar
**/
{
DEBUGFUNC("ixgbe_clear_vmdq_generic");
/* Make sure we are using a valid rar index range */
if (rar >= rar_entries) {
"RAR index %d is out of range.\n", rar);
return IXGBE_ERR_INVALID_ARGUMENT;
}
goto done;
goto done;
if (vmdq == IXGBE_CLEAR_VMDQ_ALL) {
if (mpsar_lo) {
mpsar_lo = 0;
}
if (mpsar_hi) {
mpsar_hi = 0;
}
} else if (vmdq < 32) {
} else {
}
/* was that the last pool using this rar? */
done:
return IXGBE_SUCCESS;
}
/**
* ixgbe_set_vmdq_generic - Associate a VMDq pool index with a rx address
* @hw: pointer to hardware struct
* @rar: receive address register index to associate with a VMDq index
* @vmdq: VMDq pool index
**/
{
DEBUGFUNC("ixgbe_set_vmdq_generic");
/* Make sure we are using a valid rar index range */
if (rar >= rar_entries) {
"RAR index %d is out of range.\n", rar);
return IXGBE_ERR_INVALID_ARGUMENT;
}
if (vmdq < 32) {
} else {
}
return IXGBE_SUCCESS;
}
/**
* This function should only be involved in the IOV mode.
* In IOV mode, Default pool is next pool after the number of
* VFs advertized and not 0.
* MPSAR table needs to be updated for SAN_MAC RAR [hw->mac.san_mac_rar_index]
*
* ixgbe_set_vmdq_san_mac - Associate default VMDq pool index with a rx address
* @hw: pointer to hardware struct
* @vmdq: VMDq pool index
**/
{
DEBUGFUNC("ixgbe_set_vmdq_san_mac");
if (vmdq < 32) {
} else {
}
return IXGBE_SUCCESS;
}
/**
* ixgbe_init_uta_tables_generic - Initialize the Unicast Table Array
* @hw: pointer to hardware structure
**/
{
int i;
DEBUGFUNC("ixgbe_init_uta_tables_generic");
DEBUGOUT(" Clearing UTA\n");
for (i = 0; i < 128; i++)
return IXGBE_SUCCESS;
}
/**
* ixgbe_find_vlvf_slot - find the vlanid or the first empty slot
* @hw: pointer to hardware structure
* @vlan: VLAN id to write to VLAN filter
*
* return the VLVF index where this VLAN id should be placed
*
**/
{
u32 first_empty_slot = 0;
/* short cut the special case */
if (vlan == 0)
return 0;
/*
* Search for the vlan id in the VLVF entries. Save off the first empty
* slot found along the way
*/
if (!bits && !(first_empty_slot))
break;
}
/*
* If regindex is less than IXGBE_VLVF_ENTRIES, then we found the vlan
* in the VLVF. Else use the first empty VLVF register for this
* vlan id.
*/
if (regindex >= IXGBE_VLVF_ENTRIES) {
if (first_empty_slot)
else {
"No space in VLVF.\n");
}
}
return regindex;
}
/**
* ixgbe_set_vfta_generic - Set VLAN filter table
* @hw: pointer to hardware structure
* @vlan: VLAN id to write to VLAN filter
* @vind: VMDq output index that maps queue to VLAN id in VFVFB
*
**/
bool vlan_on)
{
bool vfta_changed = FALSE;
DEBUGFUNC("ixgbe_set_vfta_generic");
if (vlan > 4095)
return IXGBE_ERR_PARAM;
/*
* this is a 2 part operation - first the VFTA, then the
* VLVF and VLVFB if VT Mode is set
* We don't write the VFTA until we know the VLVF part succeeded.
*/
/* Part 1
* The VFTA is a bitstring made up of 128 32-bit registers
* that enable the particular VLAN id, much like the MTA:
* bits[11-5]: which register
* bits[4-0]: which bit in the register
*/
if (vlan_on) {
vfta_changed = TRUE;
}
} else {
vfta_changed = TRUE;
}
}
/* Part 2
* Call ixgbe_set_vlvf_generic to set VLVFB and VLVF
*/
&vfta_changed);
if (ret_val != IXGBE_SUCCESS)
return ret_val;
if (vfta_changed)
return IXGBE_SUCCESS;
}
/**
* ixgbe_set_vlvf_generic - Set VLAN Pool Filter
* @hw: pointer to hardware structure
* @vlan: VLAN id to write to VLAN filter
* @vind: VMDq output index that maps queue to VLAN id in VFVFB
* @vfta_changed: pointer to boolean flag which indicates whether VFTA
* should be changed
*
**/
bool vlan_on, bool *vfta_changed)
{
DEBUGFUNC("ixgbe_set_vlvf_generic");
if (vlan > 4095)
return IXGBE_ERR_PARAM;
/* If VT Mode is set
* Either vlan_on
* make sure the vlan is in VLVF
* set the vind bit in the matching VLVFB
* Or !vlan_on
* clear the pool bit and possibly the vind
*/
if (vt & IXGBE_VT_CTL_VT_ENABLE) {
if (vlvf_index < 0)
return vlvf_index;
if (vlan_on) {
/* set the pool bit */
if (vind < 32) {
bits);
} else {
bits);
}
} else {
/* clear the pool bit */
if (vind < 32) {
bits);
} else {
bits);
}
}
/*
* If there are still bits set in the VLVFB registers
* for the VLAN ID indicated we need to see if the
* caller is requesting that we clear the VFTA entry bit.
* If the caller has requested that we clear the VFTA
* ID entry then ignore the request. We're not worried
* about the case where we're turning the VFTA VLAN ID
* entry bit on, only when requested to turn it off as
* VLAN ID entry. In that case we cannot clear the
* been cleared. This will be indicated by "bits" being
* zero.
*/
if (bits) {
(IXGBE_VLVF_VIEN | vlan));
/* someone wants to clear the vfta entry
* Ignore it. */
*vfta_changed = FALSE;
}
} else
}
return IXGBE_SUCCESS;
}
/**
* ixgbe_clear_vfta_generic - Clear VLAN filter table
* @hw: pointer to hardware structure
*
* Clears the VLAN filer table, and the VMDq index associated with the filter
**/
{
DEBUGFUNC("ixgbe_clear_vfta_generic");
}
return IXGBE_SUCCESS;
}
/**
* ixgbe_check_mac_link_generic - Determine link and speed status
* @hw: pointer to hardware structure
* @speed: pointer to link speed
* @link_up: TRUE when link is up
* @link_up_wait_to_complete: bool used to wait for link up or not
*
* Reads the links register to determine if link is up and the current speed
**/
bool *link_up, bool link_up_wait_to_complete)
{
u32 i;
DEBUGFUNC("ixgbe_check_mac_link_generic");
/* clear the old state */
if (links_orig != links_reg) {
DEBUGOUT2("LINKS changed from %08X to %08X\n",
}
if (link_up_wait_to_complete) {
if (links_reg & IXGBE_LINKS_UP) {
break;
} else {
}
msec_delay(100);
}
} else {
if (links_reg & IXGBE_LINKS_UP)
else
}
switch (links_reg & IXGBE_LINKS_SPEED_82599) {
}
break;
break;
}
break;
default:
}
return IXGBE_SUCCESS;
}
/**
* the EEPROM
* @hw: pointer to hardware structure
* @wwnn_prefix: the alternative WWNN prefix
* @wwpn_prefix: the alternative WWPN prefix
*
* This function will read the EEPROM from the alternative SAN MAC address
**/
{
DEBUGFUNC("ixgbe_get_wwn_prefix_generic");
/* clear output first */
*wwnn_prefix = 0xFFFF;
*wwpn_prefix = 0xFFFF;
/* check if alternative SAN MAC is supported */
goto wwn_prefix_err;
if ((alt_san_mac_blk_offset == 0) ||
(alt_san_mac_blk_offset == 0xFFFF))
goto wwn_prefix_out;
/* check capability in alternative san mac address block */
goto wwn_prefix_err;
if (!(caps & IXGBE_ALT_SAN_MAC_ADDR_CAPS_ALTWWN))
goto wwn_prefix_out;
"eeprom read at offset %d failed", offset);
}
goto wwn_prefix_err;
return IXGBE_SUCCESS;
"eeprom read at offset %d failed", offset);
return IXGBE_SUCCESS;
}
/**
* ixgbe_get_fcoe_boot_status_generic - Get FCOE boot status from EEPROM
* @hw: pointer to hardware structure
* @bs: the fcoe boot status
*
* This function will read the FCOE boot status from the iSCSI FCOE block
**/
{
DEBUGFUNC("ixgbe_get_fcoe_boot_status_generic");
/* clear output first */
/* check if FCOE IBA block is present */
if (status != IXGBE_SUCCESS)
goto out;
if (!(caps & IXGBE_FCOE_IBA_CAPS_FCOE))
goto out;
/* check if iSCSI FCOE block is populated */
if (status != IXGBE_SUCCESS)
goto out;
goto out;
/* read fcoe flags in iSCSI FCOE block */
if (status != IXGBE_SUCCESS)
goto out;
else
out:
return status;
}
/**
* @hw: pointer to hardware structure
* @enable: enable or disable switch for anti-spoofing
* @pf: Physical Function pool - do not enable anti-spoofing for the PF
*
**/
{
int j;
return;
if (enable)
/*
* PFVFSPOOF register array is size 8 with 8 bits assigned to
* MAC anti-spoof enables in each register array element.
*/
for (j = 0; j < pf_target_reg; j++)
/*
* The PF should be allowed to spoof so that it can support
* emulation mode NICs. Do not set the bits assigned to the PF
*/
/*
* Remaining pools belong to the PF so they do not need to have
* anti-spoofing enabled.
*/
for (j++; j < IXGBE_PFVFSPOOF_REG_COUNT; j++)
}
/**
* @hw: pointer to hardware structure
* @enable: enable or disable switch for VLAN anti-spoofing
* @vf: Virtual Function pool - VF Pool to set for VLAN anti-spoofing
*
**/
{
return;
if (enable)
else
}
/**
* ixgbe_get_device_caps_generic - Get additional device capabilities
* @hw: pointer to hardware structure
* @device_caps: the EEPROM word with the extra device capabilities
*
* This function will read the EEPROM location for the device capabilities,
* and return the word through device_caps.
**/
{
DEBUGFUNC("ixgbe_get_device_caps_generic");
return IXGBE_SUCCESS;
}
/**
* ixgbe_enable_relaxed_ordering_gen2 - Enable relaxed ordering
* @hw: pointer to hardware structure
*
**/
{
u32 i;
DEBUGFUNC("ixgbe_enable_relaxed_ordering_gen2");
/* Enable relaxed ordering */
}
}
}
/**
* ixgbe_calculate_checksum - Calculate checksum for buffer
* @buffer: pointer to EEPROM
* @length: size of EEPROM to calculate a checksum for
* Calculates the checksum for some buffer on a specified length. The
* checksum calculated is returned.
**/
{
u32 i;
DEBUGFUNC("ixgbe_calculate_checksum");
if (!buffer)
return 0;
for (i = 0; i < length; i++)
}
/**
* ixgbe_host_interface_command - Issue command to manageability block
* @hw: pointer to the HW structure
* @buffer: contains the command to write and where the return status will
* be placed
* @length: length of buffer, must be multiple of 4 bytes
* @timeout: time in ms to wait for command completion
* @return_data: read and return data from the buffer (TRUE) or not (FALSE)
* Needed because FW structures are big endian and decoding of
* these fields can be 8 bit or 16 bit based on command. Decoding
* is not easily understood without making a table of commands.
* So we will leave this up to the caller to read back the data
* in these cases.
*
* Communicates with the manageability block. On success return IXGBE_SUCCESS
* else return IXGBE_ERR_HOST_INTERFACE_COMMAND.
**/
{
DEBUGFUNC("ixgbe_host_interface_command");
return IXGBE_ERR_HOST_INTERFACE_COMMAND;
}
/* Set bit 9 of FWSTS clearing FW reset indication */
/* Check that the host interface is enabled. */
if ((hicr & IXGBE_HICR_EN) == 0) {
DEBUGOUT("IXGBE_HOST_EN bit disabled.\n");
return IXGBE_ERR_HOST_INTERFACE_COMMAND;
}
/* Calculate length in DWORDs. We must be DWORD aligned */
DEBUGOUT("Buffer length failure, not aligned to dword");
return IXGBE_ERR_INVALID_ARGUMENT;
}
/* The device driver writes the relevant command block
* into the ram area.
*/
for (i = 0; i < dword_len; i++)
i, IXGBE_CPU_TO_LE32(buffer[i]));
/* Setting this bit tells the ARC that a new command is pending. */
for (i = 0; i < timeout; i++) {
if (!(hicr & IXGBE_HICR_C))
break;
msec_delay(1);
}
/* Check command completion */
"Command has failed with no status valid.\n");
return IXGBE_ERR_HOST_INTERFACE_COMMAND;
}
if (!return_data)
return 0;
/* Calculate length in DWORDs */
/* first pull in the header so we know the buffer length */
}
/* If there is any thing in data position pull it in */
if (buf_len == 0)
return 0;
DEBUGOUT("Buffer not large enough for reply message.\n");
return IXGBE_ERR_HOST_INTERFACE_COMMAND;
}
/* Calculate length in DWORDs, add 3 for odd lengths */
/* Pull in the rest of the buffer (bi is where we left off) */
}
return 0;
}
/**
* ixgbe_set_fw_drv_ver_generic - Sends driver version to firmware
* @hw: pointer to the HW structure
* @maj: driver version major number
* @min: driver version minor number
* @build: driver version build number
* @sub: driver version sub build number
*
* Sends driver version number to firmware through the manageability
* block. On success return IXGBE_SUCCESS
* else returns IXGBE_ERR_SWFW_SYNC when encountering an error acquiring
* semaphore or IXGBE_ERR_HOST_INTERFACE_COMMAND when command fails.
**/
{
struct ixgbe_hic_drv_info fw_cmd;
int i;
DEBUGFUNC("ixgbe_set_fw_drv_ver_generic");
!= IXGBE_SUCCESS) {
goto out;
}
for (i = 0; i <= FW_CEM_MAX_RETRIES; i++) {
sizeof(fw_cmd),
TRUE);
if (ret_val != IXGBE_SUCCESS)
continue;
else
break;
}
out:
return ret_val;
}
/**
* ixgbe_set_rxpba_generic - Initialize Rx packet buffer
* @hw: pointer to hardware structure
* @num_pb: number of packet buffers to allocate
* @headroom: reserve n KB of headroom
* @strategy: packet buffer allocation strategy
**/
int strategy)
{
int i = 0;
/* Reserve headroom */
if (!num_pb)
num_pb = 1;
/* Divide remaining packet buffer space amongst the number of packet
* buffers requested using supplied strategy.
*/
switch (strategy) {
case PBA_STRATEGY_WEIGHTED:
/* ixgbe_dcb_pba_80_48 strategy weight first half of packet
* buffer with 5/8 of the packet buffer space.
*/
for (; i < (num_pb / 2); i++)
/* Fall through to configure remaining packet buffers */
case PBA_STRATEGY_EQUAL:
for (; i < num_pb; i++)
break;
default:
break;
}
/* Only support an equally distributed Tx packet buffer strategy. */
for (i = 0; i < num_pb; i++) {
}
/* Clear unused TCs, if any, to zero buffer size*/
for (; i < IXGBE_MAX_PB; i++) {
}
}
/**
* ixgbe_clear_tx_pending - Clear pending TX work from the PCIe fifo
* @hw: pointer to the hardware structure
*
* The 82599 and x540 MACs can experience issues if TX work is still pending
* when a reset occurs. This function prevents this by flushing the PCIe
* buffers on the system.
**/
{
/*
* If double reset is not requested then all transactions should
* already be clear and as such there is no work to do
*/
return;
/*
* Set loopback enable to prevent any transmits from being sent
* should the link come up. This assumes that the RXCTRL.RXEN bit
* has already been cleared.
*/
/* Wait for a last completion before clearing buffers */
msec_delay(3);
/*
* Before proceeding, make sure that the PCIe block does not have
* transactions pending.
*/
for (i = 0; i < poll; i++) {
usec_delay(100);
goto out;
goto out;
}
out:
/* initiate cleaning flow for buffers in the PCIe transaction layer */
/* Flush all writes and allow 20usec for all transactions to clear */
usec_delay(20);
/* restore previous register values */
}
/**
* ixgbe_dcb_get_rtrup2tc_generic - read rtrup2tc reg
* @hw: pointer to hardware structure
* @map: pointer to u8 arr for returning map
*
* Read the rtrup2tc HW register and resolve its content into map
**/
{
for (i = 0; i < IXGBE_DCB_MAX_USER_PRIORITY; i++)
map[i] = IXGBE_RTRUP2TC_UP_MASK &
(reg >> (i * IXGBE_RTRUP2TC_UP_SHIFT));
return;
}
{
if (rxctrl & IXGBE_RXCTRL_RXEN) {
if (pfdtxgswc & IXGBE_PFDTXGSWC_VT_LBEN) {
} else {
}
}
rxctrl &= ~IXGBE_RXCTRL_RXEN;
}
}
{
}
}
}
/**
* ixgbe_mng_present - returns TRUE when management capability is present
* @hw: pointer to hardware structure
*/
{
return FALSE;
return fwsm == IXGBE_FWSM_FW_MODE_PT;
}
/**
* ixgbe_mng_enabled - Is the manageability engine enabled?
* @hw: pointer to hardware structure
*
* Returns TRUE if the manageability engine is enabled.
**/
{
return FALSE;
if (!(manc & IXGBE_MANC_RCV_TCO_EN))
return FALSE;
if (factps & IXGBE_FACTPS_MNGCG)
return FALSE;
}
return TRUE;
}
/**
* ixgbe_setup_mac_link_multispeed_fiber - Set MAC link speed
* @hw: pointer to hardware structure
* @speed: new link speed
* @autoneg_wait_to_complete: TRUE when waiting for completion is needed
*
**/
bool autoneg_wait_to_complete)
{
u32 i = 0;
DEBUGFUNC("ixgbe_setup_mac_link_multispeed_fiber");
/* Mask off requested but non-supported speeds */
if (status != IXGBE_SUCCESS)
return status;
speed &= link_speed;
/* Try each speed one by one, highest priority first. We do this in
* software because 10Gb fiber doesn't support speed autonegotiation.
*/
if (speed & IXGBE_LINK_SPEED_10GB_FULL) {
speedcnt++;
/* If we already have link at this speed, just jump out */
if (status != IXGBE_SUCCESS)
return status;
goto out;
/* Set the module link speed */
case ixgbe_media_type_fiber:
break;
/* QSFP module automatically detects MAC link speed */
break;
default:
DEBUGOUT("Unexpected media type.\n");
break;
}
/* Allow module to change analog characteristics (1G->10G) */
msec_delay(40);
if (status != IXGBE_SUCCESS)
return status;
/* Flap the Tx laser if it has not already been done */
/* Wait for the controller to acquire link. Per IEEE 802.3ap,
* Section 73.10.2, we may have to wait up to 500ms if KR is
* attempted. 82599 uses the same timing for 10g SFI.
*/
for (i = 0; i < 5; i++) {
/* Wait for the link partner to also set speed */
msec_delay(100);
/* If we have link, just jump out */
if (status != IXGBE_SUCCESS)
return status;
if (link_up)
goto out;
}
}
if (speed & IXGBE_LINK_SPEED_1GB_FULL) {
speedcnt++;
/* If we already have link at this speed, just jump out */
if (status != IXGBE_SUCCESS)
return status;
goto out;
/* Set the module link speed */
case ixgbe_media_type_fiber:
break;
/* QSFP module automatically detects link speed */
break;
default:
DEBUGOUT("Unexpected media type.\n");
break;
}
/* Allow module to change analog characteristics (10G->1G) */
msec_delay(40);
if (status != IXGBE_SUCCESS)
return status;
/* Flap the Tx laser if it has not already been done */
/* Wait for the link partner to also set speed */
msec_delay(100);
/* If we have link, just jump out */
if (status != IXGBE_SUCCESS)
return status;
if (link_up)
goto out;
}
/* We didn't get link. Configure back to the highest speed we tried,
* (if there was more than one). We call ourselves back with just the
* single highest speed that the user requested.
*/
if (speedcnt > 1)
out:
/* Set autoneg_advertised value based on input link speed */
if (speed & IXGBE_LINK_SPEED_10GB_FULL)
if (speed & IXGBE_LINK_SPEED_1GB_FULL)
return status;
}
/**
* ixgbe_set_soft_rate_select_speed - Set module link speed
* @hw: pointer to hardware structure
* @speed: link speed to set
*
* Set module link speed via the soft rate select.
*/
{
switch (speed) {
/* one bit mask same as setting on */
break;
break;
default:
DEBUGOUT("Invalid fixed module speed\n");
return;
}
/* Set RS0 */
&eeprom_data);
if (status) {
DEBUGOUT("Failed to read Rx Rate Select RS0\n");
goto out;
}
if (status) {
DEBUGOUT("Failed to write Rx Rate Select RS0\n");
goto out;
}
/* Set RS1 */
&eeprom_data);
if (status) {
DEBUGOUT("Failed to read Rx Rate Select RS1\n");
goto out;
}
if (status) {
DEBUGOUT("Failed to write Rx Rate Select RS1\n");
goto out;
}
out:
return;
}