ixgbe_api.c revision dc0cb1cda72a989d92d813e487cdff59f629aa3f
/******************************************************************************
Copyright (c) 2001-2015, Intel Corporation
All rights reserved.
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modification, are permitted provided that the following conditions are met:
1. Redistributions of source code must retain the above copyright notice,
this list of conditions and the following disclaimer.
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this software without specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
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ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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******************************************************************************/
/*$FreeBSD$*/
#include "ixgbe_api.h"
#include "ixgbe_common.h"
#define IXGBE_EMPTY_PARAM
};
};
};
};
/**
* ixgbe_dcb_get_rtrup2tc - read rtrup2tc reg
* @hw: pointer to hardware structure
* @map: pointer to u8 arr for returning map
*
* Read the rtrup2tc HW register and resolve its content into map
**/
{
}
/**
* ixgbe_init_shared_code - Initialize the shared code
* @hw: pointer to hardware structure
*
* This will assign function pointers and assign the MAC type and PHY code.
* Does not touch the hardware. This function must be called prior to any
* other function in the shared code. The ixgbe_hw structure should be
* memset to 0 prior to calling this function. The following fields in
* hw structure should be filled in prior to calling this function:
* hw_addr, back, device_id, vendor_id, subsystem_device_id,
* subsystem_vendor_id, and revision_id
**/
{
DEBUGFUNC("ixgbe_init_shared_code");
/*
* Set the mac type
*/
case ixgbe_mac_82598EB:
break;
case ixgbe_mac_82599EB:
break;
case ixgbe_mac_X540:
break;
case ixgbe_mac_X550:
break;
case ixgbe_mac_X550EM_x:
break;
case ixgbe_mac_82599_vf:
case ixgbe_mac_X540_vf:
case ixgbe_mac_X550_vf:
case ixgbe_mac_X550EM_x_vf:
break;
default:
break;
}
return status;
}
/**
* ixgbe_set_mac_type - Sets MAC type
* @hw: pointer to the HW structure
*
* This function sets the mac type of the adapter based on the
* vendor ID and device ID stored in the hw structure.
**/
{
DEBUGFUNC("ixgbe_set_mac_type\n");
return IXGBE_ERR_DEVICE_NOT_SUPPORTED;
}
case IXGBE_DEV_ID_82598:
case IXGBE_DEV_ID_82598_BX:
case IXGBE_DEV_ID_82598AT:
case IXGBE_DEV_ID_82598AT2:
case IXGBE_DEV_ID_82598EB_CX4:
break;
case IXGBE_DEV_ID_82599_KX4:
case IXGBE_DEV_ID_82599_KR:
case IXGBE_DEV_ID_82599_SFP:
case IXGBE_DEV_ID_82599EN_SFP:
case IXGBE_DEV_ID_82599_CX4:
break;
case IXGBE_DEV_ID_82599_VF:
case IXGBE_DEV_ID_82599_VF_HV:
break;
case IXGBE_DEV_ID_X540_VF:
case IXGBE_DEV_ID_X540_VF_HV:
break;
case IXGBE_DEV_ID_X540T:
case IXGBE_DEV_ID_X540T1:
case IXGBE_DEV_ID_X540_BYPASS:
break;
case IXGBE_DEV_ID_X550T:
case IXGBE_DEV_ID_X550T1:
break;
case IXGBE_DEV_ID_X550EM_X_KR:
break;
case IXGBE_DEV_ID_X550_VF:
case IXGBE_DEV_ID_X550_VF_HV:
break;
case IXGBE_DEV_ID_X550EM_X_VF:
break;
default:
"Unsupported device id: %x",
break;
}
DEBUGOUT2("ixgbe_set_mac_type found mac: %d, returns: %d\n",
return ret_val;
}
/**
* ixgbe_init_hw - Initialize the hardware
* @hw: pointer to hardware structure
*
* Initialize the hardware by resetting and then starting the hardware
**/
{
}
/**
* ixgbe_reset_hw - Performs a hardware reset
* @hw: pointer to hardware structure
*
* Resets the hardware by resetting the transmit and receive units, masks and
* clears all interrupts, performs a PHY reset, and performs a MAC reset
**/
{
}
/**
* @hw: pointer to hardware structure
*
* Starts the hardware by filling the bus info structure and media type,
* clears all on chip counters, initializes receive address registers,
* multicast table, VLAN filter table, calls routine to setup link and
* flow control settings, and leaves transmit and receive units disabled
* and uninitialized.
**/
{
}
/**
* ixgbe_enable_relaxed_ordering - Enables tx relaxed ordering,
* which is disabled by default in ixgbe_start_hw();
*
* @hw: pointer to hardware structure
*
* Enable relaxed ordering;
**/
{
}
/**
* ixgbe_clear_hw_cntrs - Clear hardware counters
* @hw: pointer to hardware structure
*
* Clears all hardware statistics counters by reading them from the hardware
* Statistics counters are clear on read.
**/
{
}
/**
* ixgbe_get_media_type - Get media type
* @hw: pointer to hardware structure
*
* Returns the media type (fiber, copper, backplane)
**/
{
}
/**
* ixgbe_get_mac_addr - Get MAC address
* @hw: pointer to hardware structure
* @mac_addr: Adapter MAC address
*
* Reads the adapter's MAC address from the first Receive Address Register
* (RAR0) A reset of the adapter must have been performed prior to calling
* this function in order for the MAC address to have been loaded from the
* EEPROM into RAR0
**/
{
}
/**
* ixgbe_get_san_mac_addr - Get SAN MAC address
* @hw: pointer to hardware structure
* @san_mac_addr: SAN MAC address
*
* Reads the SAN MAC address from the EEPROM, if it's available. This is
* per-port, so set_lan_id() must be called before reading the addresses.
**/
{
}
/**
* ixgbe_set_san_mac_addr - Write a SAN MAC address
* @hw: pointer to hardware structure
* @san_mac_addr: SAN MAC address
*
* Writes A SAN MAC address to the EEPROM.
**/
{
}
/**
* ixgbe_get_device_caps - Get additional device capabilities
* @hw: pointer to hardware structure
* @device_caps: the EEPROM word for device capabilities
*
* Reads the extra device capabilities from the EEPROM
**/
{
}
/**
* @hw: pointer to hardware structure
* @wwnn_prefix: the alternative WWNN prefix
* @wwpn_prefix: the alternative WWPN prefix
*
* This function will read the EEPROM from the alternative SAN MAC address
**/
{
}
/**
* ixgbe_get_fcoe_boot_status - Get FCOE boot status from EEPROM
* @hw: pointer to hardware structure
* @bs: the fcoe boot status
*
* This function will read the FCOE boot status from the iSCSI FCOE block
**/
{
}
/**
* ixgbe_get_bus_info - Set PCI bus info
* @hw: pointer to hardware structure
*
* Sets the PCI bus info (speed, width, type) within the ixgbe_hw structure
**/
{
}
/**
* ixgbe_get_num_of_tx_queues - Get Tx queues
* @hw: pointer to hardware structure
*
* Returns the number of transmit queues for the given adapter.
**/
{
}
/**
* ixgbe_get_num_of_rx_queues - Get Rx queues
* @hw: pointer to hardware structure
*
* Returns the number of receive queues for the given adapter.
**/
{
}
/**
* @hw: pointer to hardware structure
*
* Sets the adapter_stopped flag within ixgbe_hw struct. Clears interrupts,
* disables transmit and receive units. The adapter_stopped flag is used by
* the shared code and drivers to determine if the adapter is in a stopped
* state and should not touch the hardware.
**/
{
}
/**
* ixgbe_read_pba_string - Reads part number string from EEPROM
* @hw: pointer to hardware structure
* @pba_num: stores the part number string from the EEPROM
* @pba_num_size: part number string buffer length
*
* Reads the part number string from the EEPROM.
**/
{
}
/**
* ixgbe_read_pba_num - Reads part number from EEPROM
* @hw: pointer to hardware structure
* @pba_num: stores the part number from the EEPROM
*
* Reads the part number from the EEPROM.
**/
{
}
/**
* ixgbe_identify_phy - Get PHY type
* @hw: pointer to hardware structure
*
* Determines the physical layer module found on the current adapter.
**/
{
}
return status;
}
/**
* ixgbe_reset_phy - Perform a PHY reset
* @hw: pointer to hardware structure
**/
{
}
if (status == IXGBE_SUCCESS) {
}
return status;
}
/**
* ixgbe_get_phy_firmware_version -
* @hw: pointer to hardware structure
* @firmware_version: pointer to firmware version
**/
{
(hw, firmware_version),
return status;
}
/**
* ixgbe_read_phy_reg - Read PHY register
* @hw: pointer to hardware structure
* @reg_addr: 32 bit address of PHY register to read
* @phy_data: Pointer to read data from PHY register
*
* Reads a value from a specified PHY register
**/
{
}
/**
* ixgbe_write_phy_reg - Write PHY register
* @hw: pointer to hardware structure
* @reg_addr: 32 bit PHY register to write
* @phy_data: Data to write to the PHY register
*
* Writes a value to specified PHY register
**/
{
}
/**
* ixgbe_setup_phy_link - Restart PHY autoneg
* @hw: pointer to hardware structure
*
* Restart autonegotiation and PHY and waits for completion.
**/
{
}
/**
* ixgbe_setup_internal_phy - Configure integrated PHY
* @hw: pointer to hardware structure
*
* Reconfigure the integrated PHY in order to enable talk to the external PHY.
* Returns success if not implemented, since nothing needs to be done in this
* case.
*/
{
}
/**
* ixgbe_check_phy_link - Determine link and speed status
* @hw: pointer to hardware structure
*
* Reads a PHY register to determine if link is up and the current speed for
* the PHY.
**/
bool *link_up)
{
}
/**
* ixgbe_setup_phy_link_speed - Set auto advertise
* @hw: pointer to hardware structure
* @speed: new link speed
*
* Sets the auto advertised capabilities
**/
bool autoneg_wait_to_complete)
{
}
/**
* ixgbe_set_phy_power - Control the phy power state
* @hw: pointer to hardware structure
* @on: TRUE for on, FALSE for off
*/
{
}
/**
* ixgbe_check_link - Get link and speed status
* @hw: pointer to hardware structure
*
* Reads the links register to determine if link is up and the current speed
**/
bool *link_up, bool link_up_wait_to_complete)
{
}
/**
* ixgbe_disable_tx_laser - Disable Tx laser
* @hw: pointer to hardware structure
*
* If the driver needs to disable the laser on SFI optics.
**/
{
}
/**
* ixgbe_enable_tx_laser - Enable Tx laser
* @hw: pointer to hardware structure
*
* If the driver needs to enable the laser on SFI optics.
**/
{
}
/**
* ixgbe_flap_tx_laser - flap Tx laser to start autotry process
* @hw: pointer to hardware structure
*
* When the driver changes the link speeds that it can support then
* flap the tx laser to alert the link partner to start autotry
* process on its end.
**/
{
}
/**
* ixgbe_setup_link - Set link speed
* @hw: pointer to hardware structure
* @speed: new link speed
*
* Configures link settings. Restarts the link.
* Performs autonegotiation if needed.
**/
bool autoneg_wait_to_complete)
{
}
/**
* ixgbe_setup_mac_link - Set link speed
* @hw: pointer to hardware structure
* @speed: new link speed
*
* Configures link settings. Restarts the link.
* Performs autonegotiation if needed.
**/
bool autoneg_wait_to_complete)
{
}
/**
* ixgbe_get_link_capabilities - Returns link capabilities
* @hw: pointer to hardware structure
*
* Determines the link capabilities of the current configuration.
**/
bool *autoneg)
{
}
/**
* ixgbe_led_on - Turn on LEDs
* @hw: pointer to hardware structure
* @index: led number to turn on
*
* Turns on the software controllable LEDs.
**/
{
}
/**
* ixgbe_led_off - Turn off LEDs
* @hw: pointer to hardware structure
* @index: led number to turn off
*
* Turns off the software controllable LEDs.
**/
{
}
/**
* ixgbe_blink_led_start - Blink LEDs
* @hw: pointer to hardware structure
* @index: led number to blink
*
* Blink LED based on index.
**/
{
}
/**
* ixgbe_blink_led_stop - Stop blinking LEDs
* @hw: pointer to hardware structure
*
* Stop blinking LED based on index.
**/
{
}
/**
* ixgbe_init_eeprom_params - Initialize EEPROM parameters
* @hw: pointer to hardware structure
*
* Initializes the EEPROM parameters ixgbe_eeprom_info within the
* ixgbe_hw struct in order to set up EEPROM access.
**/
{
}
/**
* ixgbe_write_eeprom - Write word to EEPROM
* @hw: pointer to hardware structure
* @offset: offset within the EEPROM to be written to
* @data: 16 bit word to be written to the EEPROM
*
* Writes 16 bit value to EEPROM. If ixgbe_eeprom_update_checksum is not
* called after this function, the EEPROM will most likely contain an
* invalid checksum.
**/
{
}
/**
* ixgbe_write_eeprom_buffer - Write word(s) to EEPROM
* @hw: pointer to hardware structure
* @offset: offset within the EEPROM to be written to
* @data: 16 bit word(s) to be written to the EEPROM
* @words: number of words
*
* Writes 16 bit word(s) to EEPROM. If ixgbe_eeprom_update_checksum is not
* called after this function, the EEPROM will most likely contain an
* invalid checksum.
**/
{
}
/**
* ixgbe_read_eeprom - Read word from EEPROM
* @hw: pointer to hardware structure
* @offset: offset within the EEPROM to be read
* @data: read 16 bit value from EEPROM
*
* Reads 16 bit value from EEPROM
**/
{
}
/**
* ixgbe_read_eeprom_buffer - Read word(s) from EEPROM
* @hw: pointer to hardware structure
* @offset: offset within the EEPROM to be read
* @data: read 16 bit word(s) from EEPROM
* @words: number of words
*
* Reads 16 bit word(s) from EEPROM
**/
{
}
/**
* ixgbe_validate_eeprom_checksum - Validate EEPROM checksum
* @hw: pointer to hardware structure
* @checksum_val: calculated checksum
*
* Performs checksum calculation and validates the EEPROM checksum
**/
{
}
/**
* ixgbe_eeprom_update_checksum - Updates the EEPROM checksum
* @hw: pointer to hardware structure
**/
{
}
/**
* ixgbe_insert_mac_addr - Find a RAR for this mac address
* @hw: pointer to hardware structure
* @addr: Address to put into receive address register
* @vmdq: VMDq pool to assign
*
* Puts an ethernet address into a receive address register, or
* finds the rar that it is already in; adds to the pool list
**/
{
}
/**
* ixgbe_set_rar - Set Rx address register
* @hw: pointer to hardware structure
* @index: Receive address register to write
* @addr: Address to put into receive address register
* @vmdq: VMDq "set"
* @enable_addr: set flag that address is active
*
* Puts an ethernet address into a receive address register.
**/
{
}
/**
* ixgbe_clear_rar - Clear Rx address register
* @hw: pointer to hardware structure
* @index: Receive address register to write
*
* Puts an ethernet address into a receive address register.
**/
{
}
/**
* ixgbe_set_vmdq - Associate a VMDq index with a receive address
* @hw: pointer to hardware structure
* @rar: receive address register index to associate with VMDq index
* @vmdq: VMDq set or pool index
**/
{
}
/**
* ixgbe_set_vmdq_san_mac - Associate VMDq index 127 with a receive address
* @hw: pointer to hardware structure
* @vmdq: VMDq default pool index
**/
{
}
/**
* ixgbe_clear_vmdq - Disassociate a VMDq index from a receive address
* @hw: pointer to hardware structure
* @rar: receive address register index to disassociate with VMDq index
* @vmdq: VMDq set or pool index
**/
{
}
/**
* ixgbe_init_rx_addrs - Initializes receive address filters.
* @hw: pointer to hardware structure
*
* Places the MAC address in receive address register 0 and clears the rest
* of the receive address registers. Clears the multicast table. Assumes
* the receiver is in reset when the routine is called.
**/
{
}
/**
* ixgbe_get_num_rx_addrs - Returns the number of RAR entries.
* @hw: pointer to hardware structure
**/
{
}
/**
* ixgbe_update_uc_addr_list - Updates the MAC's list of secondary addresses
* @hw: pointer to hardware structure
* @addr_list: the list of new multicast addresses
* @addr_count: number of addresses
* @func: iterator function to walk the multicast address list
*
* The given list replaces any existing list. Clears the secondary addrs from
* receive address registers. Uses unused receive address registers for the
* first secondary addresses, and falls back to promiscuous mode as needed.
**/
{
}
/**
* ixgbe_update_mc_addr_list - Updates the MAC's list of multicast addresses
* @hw: pointer to hardware structure
* @mc_addr_list: the list of new multicast addresses
* @mc_addr_count: number of addresses
* @func: iterator function to walk the multicast address list
*
* The given list replaces any existing list. Clears the MC addrs from receive
* address registers and the multicast table. Uses unused receive address
* registers for the first multicast addresses, and hashes the rest into the
* multicast table.
**/
bool clear)
{
}
/**
* ixgbe_enable_mc - Enable multicast address in RAR
* @hw: pointer to hardware structure
*
* Enables multicast address in RAR and the use of the multicast hash table.
**/
{
}
/**
* ixgbe_disable_mc - Disable multicast address in RAR
* @hw: pointer to hardware structure
*
* Disables multicast address in RAR and the use of the multicast hash table.
**/
{
}
/**
* ixgbe_clear_vfta - Clear VLAN filter table
* @hw: pointer to hardware structure
*
* Clears the VLAN filer table, and the VMDq index associated with the filter
**/
{
}
/**
* ixgbe_set_vfta - Set VLAN filter table
* @hw: pointer to hardware structure
* @vlan: VLAN id to write to VLAN filter
* @vind: VMDq output index that maps queue to VLAN id in VFTA
*
**/
{
}
/**
* ixgbe_set_vlvf - Set VLAN Pool Filter
* @hw: pointer to hardware structure
* @vlan: VLAN id to write to VLAN filter
* @vind: VMDq output index that maps queue to VLAN id in VFVFB
* @vfta_changed: pointer to boolean flag which indicates whether VFTA
* should be changed
*
**/
bool *vfta_changed)
{
}
/**
* ixgbe_fc_enable - Enable flow control
* @hw: pointer to hardware structure
*
* Configures the flow control settings based on SW configuration.
**/
{
}
/**
* ixgbe_setup_fc - Set up flow control
* @hw: pointer to hardware structure
*
* Called at init time to set up flow control.
**/
{
}
/**
* ixgbe_set_fw_drv_ver - Try to send the driver version number FW
* @hw: pointer to hardware structure
* @maj: driver major number to be sent to firmware
* @min: driver minor number to be sent to firmware
* @build: driver build number to be sent to firmware
* @ver: driver version number to be sent to firmware
**/
{
}
/**
* ixgbe_dmac_config - Configure DMA Coalescing registers.
* @hw: pointer to hardware structure
*
* Configure DMA coalescing. If enabling dmac, dmac is activated.
* When disabling dmac, dmac enable dmac bit is cleared.
**/
{
}
/**
* ixgbe_dmac_update_tcs - Configure DMA Coalescing registers.
* @hw: pointer to hardware structure
*
* Disables dmac, updates per TC settings, and then enable dmac.
**/
{
}
/**
* ixgbe_dmac_config_tcs - Configure DMA Coalescing registers.
* @hw: pointer to hardware structure
*
* Configure DMA coalescing threshold per TC and set high priority bit for
* FCOE TC. The dmac enable bit must be cleared before configuring.
**/
{
}
/**
* @hw: pointer to the HW structure
* @enable_eee: boolean flag to enable EEE
*
* Auto-negotiation must be started after BASE-T EEE bits in PHY register 7.3C
* are modified.
*
**/
{
}
/**
* @hw: pointer to hardware structure
* @enbale: enable or disable source address pruning
* @pool: Rx pool - Rx pool to toggle source address pruning
**/
unsigned int pool)
{
}
/**
* @hw: pointer to hardware structure
* @enable: enable or disable switch for Ethertype anti-spoofing
* @vf: Virtual Function pool - VF Pool to set for Ethertype anti-spoofing
*
**/
{
}
/**
* ixgbe_read_iosf_sb_reg - Read 32 bit PHY register
* @hw: pointer to hardware structure
* @reg_addr: 32 bit address of PHY register to read
* @device_type: type of device you want to communicate with
* @phy_data: Pointer to read data from PHY register
*
* Reads a value from a specified PHY register
**/
{
}
/**
* ixgbe_write_iosf_sb_reg - Write 32 bit register through IOSF Sideband
* @hw: pointer to hardware structure
* @reg_addr: 32 bit PHY register to write
* @device_type: type of device you want to communicate with
* @phy_data: Data to write to the PHY register
*
* Writes a value to specified PHY register
**/
{
}
/**
* ixgbe_disable_mdd - Disable malicious driver detection
* @hw: pointer to hardware structure
*
**/
{
}
/**
* ixgbe_enable_mdd - Enable malicious driver detection
* @hw: pointer to hardware structure
*
**/
{
}
/**
* ixgbe_mdd_event - Handle malicious driver detection event
* @hw: pointer to hardware structure
* @vf_bitmap: vf bitmap of malicious vfs
*
**/
{
}
/**
* ixgbe_restore_mdd_vf - Restore VF that was disabled during malicious driver
* detection event
* @hw: pointer to hardware structure
* @vf: vf index
*
**/
{
}
/**
* ixgbe_enter_lplu - Transition to low power states
* @hw: pointer to hardware structure
*
* Configures Low Power Link Up on transition to low power states
* (from D0 to non-D0).
**/
{
}
/**
* ixgbe_handle_lasi - Handle external Base T PHY interrupt
* @hw: pointer to hardware structure
*
* Handle external Base T PHY interrupt. If high temperature
* failure alarm then return error, else if link status change
*
* Return IXGBE_ERR_OVERTEMP if interrupt is high temperature
* failure alarm, else return PHY access status.
*/
{
}
/**
* ixgbe_read_analog_reg8 - Reads 8 bit analog register
* @hw: pointer to hardware structure
* @reg: analog register to read
* @val: read value
*
* Performs write operation to analog register specified.
**/
{
}
/**
* ixgbe_write_analog_reg8 - Writes 8 bit analog register
* @hw: pointer to hardware structure
* @reg: analog register to write
* @val: value to write
*
* Performs write operation to Atlas analog register specified.
**/
{
}
/**
* ixgbe_init_uta_tables - Initializes Unicast Table Arrays.
* @hw: pointer to hardware structure
*
* Initializes the Unicast Table Arrays to zero on device load. This
* is part of the Rx init addr execution path.
**/
{
}
/**
* ixgbe_read_i2c_byte - Reads 8 bit word over I2C at specified device address
* @hw: pointer to hardware structure
* @byte_offset: byte offset to read
* @dev_addr: I2C bus address to read from
* @data: value read
*
* Performs byte read operation to SFP module's EEPROM over I2C interface.
**/
{
}
/**
* ixgbe_read_i2c_byte_unlocked - Reads 8 bit word via I2C from device address
* @hw: pointer to hardware structure
* @byte_offset: byte offset to read
* @dev_addr: I2C bus address to read from
* @data: value read
*
* Performs byte read operation to SFP module's EEPROM over I2C interface.
**/
{
}
/**
* ixgbe_read_i2c_combined - Perform I2C read combined operation
* @hw: pointer to the hardware structure
* @addr: I2C bus address to read from
* @reg: I2C device register to read from
* @val: pointer to location to receive read value
*
* Returns an error code on error.
*/
{
}
/**
* ixgbe_read_i2c_combined_unlocked - Perform I2C read combined operation
* @hw: pointer to the hardware structure
* @addr: I2C bus address to read from
* @reg: I2C device register to read from
* @val: pointer to location to receive read value
*
* Returns an error code on error.
**/
{
}
/**
* ixgbe_write_i2c_byte - Writes 8 bit word over I2C
* @hw: pointer to hardware structure
* @byte_offset: byte offset to write
* @dev_addr: I2C bus address to write to
* @data: value to write
*
* Performs byte write operation to SFP module's EEPROM over I2C interface
* at a specified device address.
**/
{
}
/**
* ixgbe_write_i2c_byte_unlocked - Writes 8 bit word over I2C
* @hw: pointer to hardware structure
* @byte_offset: byte offset to write
* @dev_addr: I2C bus address to write to
* @data: value to write
*
* Performs byte write operation to SFP module's EEPROM over I2C interface
* at a specified device address.
**/
{
}
/**
* ixgbe_write_i2c_combined - Perform I2C write combined operation
* @hw: pointer to the hardware structure
* @addr: I2C bus address to write to
* @reg: I2C device register to write to
* @val: value to write
*
* Returns an error code on error.
*/
{
}
/**
* ixgbe_write_i2c_combined_unlocked - Perform I2C write combined operation
* @hw: pointer to the hardware structure
* @addr: I2C bus address to write to
* @reg: I2C device register to write to
* @val: value to write
*
* Returns an error code on error.
**/
{
}
/**
* ixgbe_write_i2c_eeprom - Writes 8 bit EEPROM word over I2C interface
* @hw: pointer to hardware structure
* @byte_offset: EEPROM byte offset to write
* @eeprom_data: value to write
*
* Performs byte write operation to SFP module's EEPROM over I2C interface.
**/
{
}
/**
* ixgbe_read_i2c_eeprom - Reads 8 bit EEPROM word over I2C interface
* @hw: pointer to hardware structure
* @byte_offset: EEPROM byte offset to read
* @eeprom_data: value read
*
* Performs byte read operation to SFP module's EEPROM over I2C interface.
**/
{
}
/**
* ixgbe_get_supported_physical_layer - Returns physical layer type
* @hw: pointer to hardware structure
*
* Determines physical layer capabilities of the current configuration.
**/
{
}
/**
* ixgbe_enable_rx_dma - Enables Rx DMA unit, dependent on device specifics
* @hw: pointer to hardware structure
* @regval: bitfield to write to the Rx DMA register
*
* Enables the Rx DMA unit of the device.
**/
{
}
/**
* ixgbe_disable_sec_rx_path - Stops the receive data path
* @hw: pointer to hardware structure
*
* Stops the receive data path.
**/
{
(hw), IXGBE_NOT_IMPLEMENTED);
}
/**
* ixgbe_enable_sec_rx_path - Enables the receive data path
* @hw: pointer to hardware structure
*
* Enables the receive data path.
**/
{
(hw), IXGBE_NOT_IMPLEMENTED);
}
/**
* ixgbe_acquire_swfw_semaphore - Acquire SWFW semaphore
* @hw: pointer to hardware structure
* @mask: Mask to specify which semaphore to acquire
*
* Acquires the SWFW semaphore through SW_FW_SYNC register for the specified
* function (CSR, PHY0, PHY1, EEPROM, Flash)
**/
{
}
/**
* ixgbe_release_swfw_semaphore - Release SWFW semaphore
* @hw: pointer to hardware structure
* @mask: Mask to specify which semaphore to release
*
* Releases the SWFW semaphore through SW_FW_SYNC register for the specified
* function (CSR, PHY0, PHY1, EEPROM, Flash)
**/
{
}
{
}
{
}
/**
* ixgbe_set_rate_select_speed - Set module link speed
* @hw: pointer to hardware structure
* @speed: link speed to set
*
* Set module link speed via the rate select.
*/
{
}