d3d50737e566cade9a08d73d2af95105ac7cd960Rafael Vanoni * Copyright 2009 Sun Microsystems, Inc. All rights reserved.
bb5e3b2f129cc39517b925419c22f69a378ec023eh * Use is subject to license terms.
bb5e3b2f129cc39517b925419c22f69a378ec023eh * Copyright (c) 2004, 2005
bb5e3b2f129cc39517b925419c22f69a378ec023eh * Damien Bergamini <damien.bergamini@free.fr>. All rights reserved.
bb5e3b2f129cc39517b925419c22f69a378ec023eh * Redistribution and use in source and binary forms, with or without
bb5e3b2f129cc39517b925419c22f69a378ec023eh * modification, are permitted provided that the following conditions
bb5e3b2f129cc39517b925419c22f69a378ec023eh * are met:
bb5e3b2f129cc39517b925419c22f69a378ec023eh * 1. Redistributions of source code must retain the above copyright
bb5e3b2f129cc39517b925419c22f69a378ec023eh * notice unmodified, this list of conditions, and the following
bb5e3b2f129cc39517b925419c22f69a378ec023eh * disclaimer.
bb5e3b2f129cc39517b925419c22f69a378ec023eh * 2. Redistributions in binary form must reproduce the above copyright
bb5e3b2f129cc39517b925419c22f69a378ec023eh * notice, this list of conditions and the following disclaimer in the
bb5e3b2f129cc39517b925419c22f69a378ec023eh * documentation and/or other materials provided with the distribution.
bb5e3b2f129cc39517b925419c22f69a378ec023eh * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
bb5e3b2f129cc39517b925419c22f69a378ec023eh * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
bb5e3b2f129cc39517b925419c22f69a378ec023eh * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
bb5e3b2f129cc39517b925419c22f69a378ec023eh * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
bb5e3b2f129cc39517b925419c22f69a378ec023eh * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
bb5e3b2f129cc39517b925419c22f69a378ec023eh * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
bb5e3b2f129cc39517b925419c22f69a378ec023eh * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
bb5e3b2f129cc39517b925419c22f69a378ec023eh * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
bb5e3b2f129cc39517b925419c22f69a378ec023eh * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
bb5e3b2f129cc39517b925419c22f69a378ec023eh * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
bb5e3b2f129cc39517b925419c22f69a378ec023eh * SUCH DAMAGE.
bb5e3b2f129cc39517b925419c22f69a378ec023eh * Intel Wireless PRO/2200 mini-PCI adapter driver
bb5e3b2f129cc39517b925419c22f69a378ec023eh * ipw2200_hw.c is used t handle hardware operations and firmware operations.
bb5e3b2f129cc39517b925419c22f69a378ec023eh * Hardware related operations
bb5e3b2f129cc39517b925419c22f69a378ec023eh return (ddi_get8(sc->sc_ioh, (uint8_t *)(sc->sc_regs + off)));
bb5e3b2f129cc39517b925419c22f69a378ec023ehipw2200_csr_getbuf32(struct ipw2200_softc *sc, uint32_t off,
bb5e3b2f129cc39517b925419c22f69a378ec023eh ddi_put8(sc->sc_ioh, (uint8_t *)(sc->sc_regs + off), val);
bb5e3b2f129cc39517b925419c22f69a378ec023ehipw2200_imem_get8(struct ipw2200_softc *sc, uint32_t addr)
bb5e3b2f129cc39517b925419c22f69a378ec023eh return (ipw2200_csr_get8(sc, IPW2200_CSR_INDIRECT_DATA));
bb5e3b2f129cc39517b925419c22f69a378ec023eh return (ipw2200_csr_get16(sc, IPW2200_CSR_INDIRECT_DATA));
bb5e3b2f129cc39517b925419c22f69a378ec023ehipw2200_imem_get32(struct ipw2200_softc *sc, uint32_t addr)
bb5e3b2f129cc39517b925419c22f69a378ec023eh return (ipw2200_csr_get32(sc, IPW2200_CSR_INDIRECT_DATA));
bb5e3b2f129cc39517b925419c22f69a378ec023ehipw2200_imem_put8(struct ipw2200_softc *sc, uint32_t addr, uint8_t val)
bb5e3b2f129cc39517b925419c22f69a378ec023ehipw2200_imem_put16(struct ipw2200_softc *sc, uint32_t addr,
bb5e3b2f129cc39517b925419c22f69a378ec023ehipw2200_imem_put32(struct ipw2200_softc *sc, uint32_t addr,
bb5e3b2f129cc39517b925419c22f69a378ec023ehipw2200_rom_control(struct ipw2200_softc *sc, uint32_t val)
bb5e3b2f129cc39517b925419c22f69a378ec023eh * According to i2c bus protocol
bb5e3b2f129cc39517b925419c22f69a378ec023eh /* clock */
bb5e3b2f129cc39517b925419c22f69a378ec023eh ipw2200_rom_control(sc, IPW2200_EEPROM_S | IPW2200_EEPROM_C);
bb5e3b2f129cc39517b925419c22f69a378ec023eh /* start bit */
bb5e3b2f129cc39517b925419c22f69a378ec023eh ipw2200_rom_control(sc, IPW2200_EEPROM_S | IPW2200_EEPROM_D);
bb5e3b2f129cc39517b925419c22f69a378ec023eh ipw2200_rom_control(sc, IPW2200_EEPROM_S | IPW2200_EEPROM_D |
bb5e3b2f129cc39517b925419c22f69a378ec023eh /* read opcode */
bb5e3b2f129cc39517b925419c22f69a378ec023eh ipw2200_rom_control(sc, IPW2200_EEPROM_S | IPW2200_EEPROM_D);
bb5e3b2f129cc39517b925419c22f69a378ec023eh ipw2200_rom_control(sc, IPW2200_EEPROM_S | IPW2200_EEPROM_D |
bb5e3b2f129cc39517b925419c22f69a378ec023eh ipw2200_rom_control(sc, IPW2200_EEPROM_S | IPW2200_EEPROM_C);
bb5e3b2f129cc39517b925419c22f69a378ec023eh * address, totally 8 bits, defined by hardware, push from MSB to LSB
bb5e3b2f129cc39517b925419c22f69a378ec023eh for (n = 7; n >= 0; n--) {
bb5e3b2f129cc39517b925419c22f69a378ec023eh * data, totally 16 bits, defined by hardware, push from MSB to LSB
bb5e3b2f129cc39517b925419c22f69a378ec023eh for (n = 15; n >= 0; n--) {
bb5e3b2f129cc39517b925419c22f69a378ec023eh ipw2200_rom_control(sc, IPW2200_EEPROM_S | IPW2200_EEPROM_C);
bb5e3b2f129cc39517b925419c22f69a378ec023eh val |= ((tmp & IPW2200_EEPROM_Q) >> IPW2200_EEPROM_SHIFT_Q)
bb5e3b2f129cc39517b925419c22f69a378ec023eh /* clear chip select and clock */
bb5e3b2f129cc39517b925419c22f69a378ec023eh * Firmware related operations
bb5e3b2f129cc39517b925419c22f69a378ec023eh * These firwares were issued by Intel as binaries which need to be
bb5e3b2f129cc39517b925419c22f69a378ec023eh * loaded to hardware when card is initiated, or when fatal error
bb5e3b2f129cc39517b925419c22f69a378ec023eh * happened, or when the chip need be reset.
bb5e3b2f129cc39517b925419c22f69a378ec023eh "ipw2200_cache_firmware(): enter\n"));
bb5e3b2f129cc39517b925419c22f69a378ec023eh /* boot code */
bb5e3b2f129cc39517b925419c22f69a378ec023eh sc->sc_fw.boot_base = ipw2200_boot_bin + sizeof (struct header);
bb5e3b2f129cc39517b925419c22f69a378ec023eh /* ucode */
bb5e3b2f129cc39517b925419c22f69a378ec023eh sc->sc_fw.uc_base = ipw2200_ucode_bin + sizeof (struct header);
bb5e3b2f129cc39517b925419c22f69a378ec023eh sc->sc_fw.uc_size = sizeof (ipw2200_ucode_bin) - sizeof (struct header);
bb5e3b2f129cc39517b925419c22f69a378ec023eh /* firmware */
bb5e3b2f129cc39517b925419c22f69a378ec023eh sc->sc_fw.fw_base = ipw2200_fw_bin + sizeof (struct header);
bb5e3b2f129cc39517b925419c22f69a378ec023eh sc->sc_fw.fw_size = sizeof (ipw2200_fw_bin) - sizeof (struct header);
bb5e3b2f129cc39517b925419c22f69a378ec023eh "ipw2200_cache_firmware(): boot=%u,uc=%u,fw=%u\n",
bb5e3b2f129cc39517b925419c22f69a378ec023eh sc->sc_fw.boot_size, sc->sc_fw.uc_size, sc->sc_fw.fw_size));
bb5e3b2f129cc39517b925419c22f69a378ec023eh "ipw2200_cache_firmware(): exit\n"));
bb5e3b2f129cc39517b925419c22f69a378ec023eh * If user-land firmware loading is supported, this routine will
bb5e3b2f129cc39517b925419c22f69a378ec023eh * free kernel memory, when sc->sc_fw.bin_base & sc->sc_fw.bin_size
bb5e3b2f129cc39517b925419c22f69a378ec023eh * are not empty
bb5e3b2f129cc39517b925419c22f69a378ec023eh * the following routines load code onto ipw2200 hardware
bb5e3b2f129cc39517b925419c22f69a378ec023ehipw2200_load_uc(struct ipw2200_softc *sc, uint8_t *buf, size_t size)
bb5e3b2f129cc39517b925419c22f69a378ec023eh IPW2200_RST_STOP_MASTER | ipw2200_csr_get32(sc, IPW2200_CSR_RST));
bb5e3b2f129cc39517b925419c22f69a378ec023eh "ipw2200_load_uc(): timeout waiting for master"));
922d2c76afbee21520ffa2088c4e60dcb80d3945eh for (w = (uint16_t *)(uintptr_t)buf; size > 0; w++, size -= 2)
bb5e3b2f129cc39517b925419c22f69a378ec023eh * try many times to wait the upload is ready, 2000times
bb5e3b2f129cc39517b925419c22f69a378ec023eh "ipw2200_load_uc(): timeout waiting for ucode init.\n"));
bb5e3b2f129cc39517b925419c22f69a378ec023eh for (i = 0; i < 7; i++)
bb5e3b2f129cc39517b925419c22f69a378ec023ehipw2200_load_fw(struct ipw2200_softc *sc, uint8_t *buf, size_t size)
bb5e3b2f129cc39517b925419c22f69a378ec023eh struct dma_region dr[MAX_DR_NUM]; /* maximal, 64 * 4KB = 256KB */
d3d50737e566cade9a08d73d2af95105ac7cd960Rafael Vanoni clock_t clk = drv_usectohz(5000000); /* 5 second */
bb5e3b2f129cc39517b925419c22f69a378ec023eh err = ipw2200_dma_region_alloc(sc, &dr[cnt], MAX_DR_SIZE, DDI_DMA_READ,
bb5e3b2f129cc39517b925419c22f69a378ec023eh ipw2200_csr_put32(sc, IPW2200_CSR_AUTOINC_ADDR, 0x27000);
bb5e3b2f129cc39517b925419c22f69a378ec023eh while (p < end) {
bb5e3b2f129cc39517b925419c22f69a378ec023eh while (len > 0) {
bb5e3b2f129cc39517b925419c22f69a378ec023eh * if no DMA region is available, allocate a new one
bb5e3b2f129cc39517b925419c22f69a378ec023eh "ipw2200_load_fw(): "
bb5e3b2f129cc39517b925419c22f69a378ec023eh "maximum %d DRs is reached\n",
bb5e3b2f129cc39517b925419c22f69a378ec023eh * write a command
bb5e3b2f129cc39517b925419c22f69a378ec023eh sentinel = ipw2200_csr_get32(sc, IPW2200_CSR_AUTOINC_ADDR);
bb5e3b2f129cc39517b925419c22f69a378ec023eh "ipw2200_load_fw(): timeout processing command blocks\n"));
bb5e3b2f129cc39517b925419c22f69a378ec023eh * enable all interrupts
bb5e3b2f129cc39517b925419c22f69a378ec023eh ipw2200_csr_put32(sc, IPW2200_CSR_INTR_MASK, IPW2200_INTR_MASK_ALL);
bb5e3b2f129cc39517b925419c22f69a378ec023eh * tell the adapter to initialize the firmware,
bb5e3b2f129cc39517b925419c22f69a378ec023eh * just simply set it to 0
bb5e3b2f129cc39517b925419c22f69a378ec023eh * wait for interrupt to notify fw initialization is done
bb5e3b2f129cc39517b925419c22f69a378ec023eh * There is an enhancement! we just change from 1s to 5s
d3d50737e566cade9a08d73d2af95105ac7cd960Rafael Vanoni if (cv_reltimedwait(&sc->sc_fw_cond, &sc->sc_ilock, clk,
bb5e3b2f129cc39517b925419c22f69a378ec023eh for (i = 0; i <= cnt; i++)
bb5e3b2f129cc39517b925419c22f69a378ec023eh "ipw2200_load_fw(): DMA allocation failed, cnt=%d\n", cnt));
bb5e3b2f129cc39517b925419c22f69a378ec023eh for (i = 0; i <= cnt; i++)