igb_osdep.h revision 7d46e7ad7bb3e7ef36bb4f0816ad4d6c2784f405
2N/A/*
2N/A * CDDL HEADER START
2N/A *
2N/A * Copyright(c) 2007-2009 Intel Corporation. All rights reserved.
2N/A * The contents of this file are subject to the terms of the
2N/A * Common Development and Distribution License (the "License").
2N/A * You may not use this file except in compliance with the License.
2N/A *
2N/A * You can obtain a copy of the license at:
2N/A * http://www.opensolaris.org/os/licensing.
2N/A * See the License for the specific language governing permissions
2N/A * and limitations under the License.
2N/A *
2N/A * When using or redistributing this file, you may do so under the
2N/A * License only. No other modification of this header is permitted.
2N/A *
2N/A * If applicable, add the following below this CDDL HEADER, with the
2N/A * fields enclosed by brackets "[]" replaced with your own identifying
2N/A * information: Portions Copyright [yyyy] [name of copyright owner]
2N/A *
2N/A * CDDL HEADER END
2N/A */
2N/A
2N/A/*
2N/A * Copyright 2009 Sun Microsystems, Inc. All rights reserved.
2N/A * Use is subject to license terms of the CDDL.
2N/A */
2N/A
2N/A#ifndef _IGB_OSDEP_H
2N/A#define _IGB_OSDEP_H
2N/A
2N/A#ifdef __cplusplus
2N/Aextern "C" {
2N/A#endif
2N/A
2N/A#include <sys/types.h>
2N/A#include <sys/conf.h>
2N/A#include <sys/debug.h>
2N/A#include <sys/stropts.h>
2N/A#include <sys/stream.h>
2N/A#include <sys/strlog.h>
2N/A#include <sys/kmem.h>
2N/A#include <sys/stat.h>
2N/A#include <sys/kstat.h>
2N/A#include <sys/modctl.h>
2N/A#include <sys/errno.h>
2N/A#include <sys/ddi.h>
2N/A#include <sys/dditypes.h>
2N/A#include <sys/sunddi.h>
2N/A#include <sys/pci.h>
2N/A#include <sys/pci_cap.h>
2N/A#include <sys/atomic.h>
2N/A#include <sys/note.h>
2N/A#include "igb_debug.h"
2N/A
2N/A#define usec_delay(x) drv_usecwait(x)
2N/A#define msec_delay(x) drv_usecwait(x * 1000)
2N/A#define msec_delay_irq msec_delay
2N/A
2N/A#ifdef IGB_DEBUG
2N/A#define DEBUGOUT(S) IGB_DEBUGLOG_0(NULL, S)
2N/A#define DEBUGOUT1(S, A) IGB_DEBUGLOG_1(NULL, S, A)
2N/A#define DEBUGOUT2(S, A, B) IGB_DEBUGLOG_2(NULL, S, A, B)
2N/A#define DEBUGOUT3(S, A, B, C) IGB_DEBUGLOG_3(NULL, S, A, B, C)
2N/A#else
2N/A#define DEBUGOUT(S)
2N/A#define DEBUGOUT1(S, A)
2N/A#define DEBUGOUT2(S, A, B)
2N/A#define DEBUGOUT3(S, A, B, C)
2N/A#endif
2N/A
2N/A#define DEBUGFUNC(F)
2N/A
2N/A#define OS_DEP(hw) ((struct igb_osdep *)((hw)->back))
2N/A
2N/A#define false B_FALSE
2N/A#define true B_TRUE
2N/A
2N/A#define CMD_MEM_WRT_INVALIDATE 0x0010 /* BIT_4 */
2N/A#define PCI_COMMAND_REGISTER 0x04
2N/A#define PCI_EX_CONF_CAP 0xE0
2N/A
2N/A
2N/A/*
2N/A * Constants used in setting flow control thresholds
2N/A */
2N/A#define E1000_PBA_MASK 0xffff
2N/A#define E1000_PBA_SHIFT 10
2N/A#define E1000_FC_HIGH_DIFF 0x1638 /* High: 5688 bytes below Rx FIFO size */
2N/A#define E1000_FC_LOW_DIFF 0x1640 /* Low: 5696 bytes below Rx FIFO size */
2N/A#define E1000_FC_PAUSE_TIME 0x0680 /* 858 usec */
2N/A
2N/A/* PHY Extended Status Register */
2N/A#define IEEE_ESR_1000T_HD_CAPS 0x1000 /* 1000T HD capable */
2N/A#define IEEE_ESR_1000T_FD_CAPS 0x2000 /* 1000T FD capable */
2N/A#define IEEE_ESR_1000X_HD_CAPS 0x4000 /* 1000X HD capable */
2N/A#define IEEE_ESR_1000X_FD_CAPS 0x8000 /* 1000X FD capable */
2N/A
2N/A/* VMDq MODE supported by hardware */
2N/A#define E1000_VMDQ_OFF 0
2N/A#define E1000_VMDQ_MAC 1
2N/A#define E1000_VMDQ_MAC_RSS 2
2N/A
2N/A/* VMDq based on packet destination MAC address */
2N/A#define E1000_MRQC_ENABLE_VMDQ_MAC_GROUP 0x00000003
2N/A/* VMDq based on packet destination MAC address and RSS */
2N/A#define E1000_MRQC_ENABLE_VMDQ_MAC_RSS_GROUP 0x00000005
2N/A/* The default queue in each VMDqs */
2N/A#define E1000_VMDQ_MAC_GROUP_DEFAULT_QUEUE 0x100
2N/A
2N/A#define E1000_WRITE_FLUSH(a) (void) E1000_READ_REG(a, E1000_STATUS)
2N/A
2N/A#define E1000_WRITE_REG(hw, reg, value) \
2N/A ddi_put32((OS_DEP(hw))->reg_handle, \
2N/A (uint32_t *)((uintptr_t)(hw)->hw_addr + reg), (value))
2N/A
2N/A#define E1000_READ_REG(hw, reg) \
2N/A ddi_get32((OS_DEP(hw))->reg_handle, \
2N/A (uint32_t *)((uintptr_t)(hw)->hw_addr + reg))
2N/A
2N/A#define E1000_WRITE_REG_ARRAY(hw, reg, offset, value) \
2N/A ddi_put32((OS_DEP(hw))->reg_handle, \
2N/A (uint32_t *)((uintptr_t)(hw)->hw_addr + reg + ((offset) << 2)), \
2N/A (value))
2N/A
2N/A#define E1000_READ_REG_ARRAY(hw, reg, offset) \
2N/A ddi_get32((OS_DEP(hw))->reg_handle, \
2N/A (uint32_t *)((uintptr_t)(hw)->hw_addr + reg + ((offset) << 2)))
2N/A
2N/A#define E1000_WRITE_REG_ARRAY_DWORD(a, reg, offset, value) \
2N/A E1000_WRITE_REG_ARRAY(a, reg, offset, value)
2N/A#define E1000_READ_REG_ARRAY_DWORD(a, reg, offset) \
2N/A E1000_READ_REG_ARRAY(a, reg, offset)
2N/A
2N/A#define UNREFERENCED_1PARAMETER(_p) _NOTE(ARGUNUSED(_p))
2N/A#define UNREFERENCED_2PARAMETER(_p, _q) _NOTE(ARGUNUSED(_p, _q))
2N/A#define UNREFERENCED_3PARAMETER(_p, _q, _r) _NOTE(ARGUNUSED(_p, _q, _r))
2N/A#define UNREFERENCED_4PARAMETER(_p, _q, _r, _s) _NOTE(ARGUNUSED(_p, _q, _r, _s))
2N/A#define UNREFERENCED_5PARAMETER(_p, _q, _r, _s, _t) \
2N/A _NOTE(ARGUNUSED(_p, _q, _r, _s, _t))
2N/A
2N/A#define __le16 u16
2N/A#define __le32 u32
2N/A#define __le64 u64
2N/A
2N/Atypedef int8_t s8;
2N/Atypedef int16_t s16;
2N/Atypedef int32_t s32;
2N/Atypedef int64_t s64;
2N/Atypedef uint8_t u8;
2N/Atypedef uint16_t u16;
2N/Atypedef uint32_t u32;
2N/Atypedef uint64_t u64;
2N/Atypedef boolean_t bool;
2N/A
2N/Astruct igb_osdep {
2N/A ddi_acc_handle_t reg_handle;
2N/A ddi_acc_handle_t cfg_handle;
2N/A struct igb *igb;
2N/A};
2N/A
2N/A
2N/A#ifdef __cplusplus
2N/A}
2N/A#endif
2N/A
2N/A#endif /* _IGB_OSDEP_H */
2N/A