igb_osdep.c revision 7d46e7ad7bb3e7ef36bb4f0816ad4d6c2784f405
/*
* CDDL HEADER START
*
* Copyright(c) 2007-2009 Intel Corporation. All rights reserved.
* The contents of this file are subject to the terms of the
* Common Development and Distribution License (the "License").
* You may not use this file except in compliance with the License.
*
* You can obtain a copy of the license at:
* See the License for the specific language governing permissions
* and limitations under the License.
*
* When using or redistributing this file, you may do so under the
* License only. No other modification of this header is permitted.
*
* If applicable, add the following below this CDDL HEADER, with the
* fields enclosed by brackets "[]" replaced with your own identifying
* information: Portions Copyright [yyyy] [name of copyright owner]
*
* CDDL HEADER END
*/
/*
* Copyright 2009 Sun Microsystems, Inc. All rights reserved.
* Use is subject to license terms of the CDDL.
*/
#include "igb_osdep.h"
#include "igb_api.h"
void
{
}
void
{
*value =
}
/*
* Return the 16-bit value from pci-e config space at offset reg into the pci-e
* capability block. Note that this refers to the pci-e capability block in
* standard pci config space, not the block in pci-e extended config space.
*/
{
/* locate the pci-e capability block */
if (status == DDI_SUCCESS) {
/* read at given offset into block */
}
return (status);
}
/*
* Write the given 16-bit value to pci-e config space at offset reg into the
* pci-e capability block. Note that this refers to the pci-e capability block
* in standard pci config space, not the block in pci-e extended config space.
*/
{
/* locate the pci-e capability block */
if (status == DDI_SUCCESS) {
/* write at given offset into block */
}
return (status);
}
/*
* e1000_rar_set_vmdq - Clear the RAR registers
*/
void
{
/* Make the hardware the Address invalid by setting the clear bit */
rar_high = ~E1000_RAH_AV;
}
/*
* e1000_rar_set_vmdq - Set the RAR registers for VMDq
*/
void
{
/*
* NIC expects these in little endian so reverse the byte order
* from network order (big endian) to little endian.
*/
/* Indicate to hardware the Address is Valid. */
rar_high |= E1000_RAH_AV;
/* Set que selector based on vmdq mode */
switch (vmdq_mode) {
default:
case E1000_VMDQ_OFF:
break;
case E1000_VMDQ_MAC:
break;
case E1000_VMDQ_MAC_RSS:
break;
}
/* write to receive address registers */
}