igb_82575.c revision 80a11ad227f9c82cd6e7cf5c8913a37f00b7af0e
/*
* CDDL HEADER START
*
* Copyright(c) 2007-2009 Intel Corporation. All rights reserved.
* The contents of this file are subject to the terms of the
* Common Development and Distribution License (the "License").
* You may not use this file except in compliance with the License.
*
* You can obtain a copy of the license at:
* See the License for the specific language governing permissions
* and limitations under the License.
*
* When using or redistributing this file, you may do so under the
* License only. No other modification of this header is permitted.
*
* If applicable, add the following below this CDDL HEADER, with the
* fields enclosed by brackets "[]" replaced with your own identifying
* information: Portions Copyright [yyyy] [name of copyright owner]
*
* CDDL HEADER END
*/
/*
* Copyright 2009 Sun Microsystems, Inc. All rights reserved.
* Use is subject to license terms of the CDDL.
*/
/* IntelVersion: 1.94 v2008-10-7 */
/*
* 82575EB Gigabit Network Connection
* 82575EB Gigabit Backplane Connection
* 82575GB Gigabit Network Connection
* 82576 Gigabit Network Connection
*/
#include "igb_api.h"
bool active);
/*
* e1000_init_phy_params_82575 - Init PHY func ptrs.
* @hw: pointer to the HW structure
*/
static s32
{
DEBUGFUNC("e1000_init_phy_params_82575");
goto out;
} else {
}
if (e1000_sgmii_active_82575(hw)) {
} else {
}
/* Set phy->phy_addr and phy->id. */
/* Verify phy id and set remaining function pointers */
case M88E1111_I_PHY_ID:
break;
case IGP03E1000_E_PHY_ID:
case IGP04E1000_E_PHY_ID:
break;
default:
ret_val = -E1000_ERR_PHY;
goto out;
}
out:
return (ret_val);
}
/*
* e1000_init_nvm_params_82575 - Init NVM func ptrs.
* @hw: pointer to the HW structure
*/
static s32
{
DEBUGFUNC("e1000_init_nvm_params_82575");
break;
break;
default:
break;
}
/*
* Added to a constant, "size" becomes the left-shift value
* for setting word_size.
*/
/* EEPROM access above 16k is unsupported */
if (size > 14)
size = 14;
/* Function Pointers */
return (E1000_SUCCESS);
}
/*
* e1000_init_mac_params_82575 - Init MAC func ptrs.
* @hw: pointer to the HW structure
*/
static s32
{
DEBUGFUNC("e1000_init_mac_params_82575");
/* Set media type */
/*
* The 82575 uses bits 22:23 for link mode. The mode can be changed
* based on the EEPROM. We cannot rely upon device ID. There
* is no distinguishable difference between fiber and internal
* SerDes mode on the 82575. There can be an external PHY attached
* on the SGMII interface. For this, we'll set sgmii_active to true.
*/
dev_spec->sgmii_active = false;
if ((ctrl_ext & E1000_CTRL_EXT_LINK_MODE_MASK) ==
} else if (ctrl_ext & E1000_CTRL_EXT_LINK_MODE_SGMII) {
dev_spec->sgmii_active = true;
} else {
}
/* Set mta register count */
/* Set rar entry count */
/* Set if part includes ASF firmware */
mac->asf_firmware_present = true;
/* Set if manageability features are enabled. */
? true : false;
/* Function pointers */
/* reset */
/* hw initialization */
/* link setup */
/* physical interface link setup */
/* physical interface shutdown */
/* check for link */
/* receive address register setting */
/* read mac address */
/* multicast address update */
/* writing VFTA */
/* clearing VFTA */
/* setting MTA */
/* blink LED */
/* setup LED */
/* cleanup LED */
/* clear hardware counters */
/* link info */
return (E1000_SUCCESS);
}
/*
* e1000_init_function_pointers_82575 - Init func ptrs.
* @hw: pointer to the HW structure
*
* Called to initialize all function pointers and parameters.
*/
void
{
DEBUGFUNC("e1000_init_function_pointers_82575");
}
/*
* e1000_acquire_phy_82575 - Acquire rights to access PHY
* @hw: pointer to the HW structure
*
* Acquire access rights to the correct PHY.
*/
static s32
{
DEBUGFUNC("e1000_acquire_phy_82575");
}
/*
* e1000_release_phy_82575 - Release rights to access PHY
* @hw: pointer to the HW structure
*
* A wrapper to release access rights to the correct PHY.
*/
static void
{
DEBUGFUNC("e1000_release_phy_82575");
}
/*
* e1000_read_phy_reg_sgmii_82575 - Read PHY register using sgmii
* @hw: pointer to the HW structure
* @offset: register offset to be read
* @data: pointer to the read data
*
* Reads the PHY register at offset using the serial gigabit media independent
* interface and stores the retrieved information in data.
*/
static s32
{
DEBUGFUNC("e1000_read_phy_reg_sgmii_82575");
if (offset > E1000_MAX_SGMII_PHY_REG_ADDR) {
return (-E1000_ERR_PARAM);
}
/*
* Set up Op-code, Phy Address, and register address in the I2CCMD
* register. The MAC will take care of interfacing with the
* PHY to retrieve the desired data.
*/
/* Poll the ready bit to see if the I2C read completed */
for (i = 0; i < E1000_I2CCMD_PHY_TIMEOUT; i++) {
usec_delay(50);
if (i2ccmd & E1000_I2CCMD_READY)
break;
}
if (!(i2ccmd & E1000_I2CCMD_READY)) {
DEBUGOUT("I2CCMD Read did not complete\n");
return (-E1000_ERR_PHY);
}
if (i2ccmd & E1000_I2CCMD_ERROR) {
DEBUGOUT("I2CCMD Error bit set\n");
return (-E1000_ERR_PHY);
}
/* Need to byte-swap the 16-bit value. */
return (E1000_SUCCESS);
}
/*
* e1000_write_phy_reg_sgmii_82575 - Write PHY register using sgmii
* @hw: pointer to the HW structure
* @offset: register offset to write to
* @data: data to write at register offset
*
* Writes the data to PHY register at the offset using the serial gigabit
* media independent interface.
*/
static s32
{
DEBUGFUNC("e1000_write_phy_reg_sgmii_82575");
if (offset > E1000_MAX_SGMII_PHY_REG_ADDR) {
return (-E1000_ERR_PARAM);
}
/* Swap the data bytes for the I2C interface */
/*
* Set up Op-code, Phy Address, and register address in the I2CCMD
* register. The MAC will take care of interfacing with the
* PHY to retrieve the desired data.
*/
/* Poll the ready bit to see if the I2C read completed */
for (i = 0; i < E1000_I2CCMD_PHY_TIMEOUT; i++) {
usec_delay(50);
if (i2ccmd & E1000_I2CCMD_READY)
break;
}
if (!(i2ccmd & E1000_I2CCMD_READY)) {
DEBUGOUT("I2CCMD Write did not complete\n");
return (-E1000_ERR_PHY);
}
if (i2ccmd & E1000_I2CCMD_ERROR) {
DEBUGOUT("I2CCMD Error bit set\n");
return (-E1000_ERR_PHY);
}
return (E1000_SUCCESS);
}
/*
* e1000_get_phy_id_82575 - Retrieve PHY addr and id
* @hw: pointer to the HW structure
*
* Retrieves the PHY address and ID for both PHY's which do and do not use
* sgmi interface.
*/
static s32
{
DEBUGFUNC("e1000_get_phy_id_82575");
/*
* For SGMII PHYs, we try the list of possible addresses until
* we find one that works. For non-SGMII PHYs
* (e.g. integrated copper PHYs), an address of 1 should
* work. The result of this function should mean phy->phy_addr
* and phy->id are set correctly.
*/
if (!(e1000_sgmii_active_82575(hw))) {
goto out;
}
/*
* The address field in the I2CCMD register is 3 bits and 0 is invalid.
* Therefore, we need to test 1-7
*/
if (ret_val == E1000_SUCCESS) {
DEBUGOUT2("Vendor ID 0x%08X read at address %u\n",
/*
* At the time of this writing, The M88 part is
* the only supported SGMII PHY product.
*/
if (phy_id == M88_VENDOR)
break;
} else {
DEBUGOUT1("PHY address %u was unreadable\n",
}
}
/* A valid PHY type couldn't be found. */
ret_val = -E1000_ERR_PHY;
goto out;
}
out:
return (ret_val);
}
/*
* e1000_phy_hw_reset_sgmii_82575 - Performs a PHY reset
* @hw: pointer to the HW structure
*
* Resets the PHY using the serial gigabit media independent interface.
*/
static s32
{
DEBUGFUNC("e1000_phy_hw_reset_sgmii_82575");
/*
* This isn't a true "hard" reset, but is the only reset
* available to us at this time.
*/
DEBUGOUT("Soft resetting SGMII attached PHY...\n");
goto out;
/*
* SFP documentation requires the following to configure the SPF module
* to work on SGMII. No further documentation is given.
*/
if (ret_val)
goto out;
out:
return (ret_val);
}
/*
* e1000_set_d0_lplu_state_82575 - Set Low Power Linkup D0 state
* @hw: pointer to the HW structure
* @active: true to enable LPLU, false to disable
*
* Sets the LPLU D0 state according to the active flag. When
* activating LPLU this function also disables smart speed
* and vice versa. LPLU will not be activated unless the
* device autonegotiation advertisement meets standards of
* either 10 or 10/100 or 10/100/1000 at all duplexes.
* This is a function pointer entry point only called by
* PHY setup routines.
*/
static s32
{
DEBUGFUNC("e1000_set_d0_lplu_state_82575");
goto out;
if (ret_val)
goto out;
if (active) {
data);
if (ret_val)
goto out;
/* When LPLU is enabled, we should disable SmartSpeed */
&data);
data);
if (ret_val)
goto out;
} else {
data);
/*
* LPLU and SmartSpeed are mutually exclusive. LPLU is used
* during Dx states where the power conservation is most
* important. During driver activity we should enable
* SmartSpeed, so performance is maintained.
*/
&data);
if (ret_val)
goto out;
data);
if (ret_val)
goto out;
&data);
if (ret_val)
goto out;
data);
if (ret_val)
goto out;
}
}
out:
return (ret_val);
}
/*
* e1000_acquire_nvm_82575 - Request for access to EEPROM
* @hw: pointer to the HW structure
*
* Acquire the necessary semaphores for exclusive access to the EEPROM.
* Set the EEPROM access request bit and wait for EEPROM access grant bit.
* Return successful if access grant bit set, else clear the request for
* EEPROM access and return -E1000_ERR_NVM (-1).
*/
static s32
{
DEBUGFUNC("e1000_acquire_nvm_82575");
if (ret_val)
goto out;
if (ret_val)
out:
return (ret_val);
}
/*
* e1000_release_nvm_82575 - Release exclusive access to EEPROM
* @hw: pointer to the HW structure
*
* Stop any current commands to the EEPROM and clear the EEPROM request bit,
* then release the semaphores acquired.
*/
static void
{
DEBUGFUNC("e1000_release_nvm_82575");
}
/*
* @hw: pointer to the HW structure
* @mask: specifies which semaphore to acquire
*
* will also specify which port we're acquiring the lock for.
*/
static s32
{
DEBUGFUNC("e1000_acquire_swfw_sync_82575");
while (i < timeout) {
if (e1000_get_hw_semaphore_generic(hw)) {
goto out;
}
break;
/*
* Firmware currently using resource (fwmask)
* or other software thread using resource (swmask)
*/
msec_delay_irq(5);
i++;
}
if (i == timeout) {
DEBUGOUT("Driver can't access resource, SW_FW_SYNC timeout.\n");
goto out;
}
out:
return (ret_val);
}
/*
* @hw: pointer to the HW structure
* @mask: specifies which semaphore to acquire
*
* will also specify which port we're releasing the lock for.
*/
static void
{
DEBUGFUNC("e1000_release_swfw_sync_82575");
/* Empty */
}
}
/*
* e1000_get_cfg_done_82575 - Read config done bit
* @hw: pointer to the HW structure
*
* Read the management control register for the config done bit for
* completion status. NOTE: silicon which is EEPROM-less will fail trying
* to read the config done bit, so an error is *ONLY* logged and returns
* E1000_SUCCESS. If we were to return with error, EEPROM-less silicon
* would not be able to be reset or change link.
*/
static s32
{
DEBUGFUNC("e1000_get_cfg_done_82575");
while (timeout) {
break;
msec_delay(1);
timeout--;
}
if (!timeout) {
DEBUGOUT("MNG configuration cycle has not completed.\n");
}
/* If EEPROM is not marked present, init the PHY manually */
(void) e1000_phy_init_script_igp3(hw);
}
return (ret_val);
}
/*
* @hw: pointer to the HW structure
* @speed: stores the current speed
* @duplex: stores the current duplex
*
* This is a wrapper function, if using the serial gigabit media independent
* interface, use PCS to retrieve the link speed and duplex information.
* Otherwise, use the generic function to get the link speed and duplex info.
*/
static s32
{
DEBUGFUNC("e1000_get_link_up_info_82575");
duplex);
} else {
duplex);
}
return (ret_val);
}
/*
* e1000_check_for_link_82575 - Check for link
* @hw: pointer to the HW structure
*
* If sgmii is enabled, then use the pcs register to determine link, otherwise
* use the generic interface for determining link.
*/
static s32
{
DEBUGFUNC("e1000_check_for_link_82575");
/* SGMII link check is done through the PCS register. */
&duplex);
else
return (ret_val);
}
/*
* @hw: pointer to the HW structure
* @speed: stores the current speed
* @duplex: stores the current duplex
*
* Using the physical coding sub-layer (PCS), retrieve the current speed and
* duplex, then store the values in the pointers provided.
*/
static s32
{
DEBUGFUNC("e1000_get_pcs_speed_and_duplex_82575");
/* Set up defaults for the return values of this function */
mac->serdes_has_link = false;
*speed = 0;
*duplex = 0;
/*
* Read the PCS Status register for link state. For non-copper mode,
* the status register is not accurate. The PCS status register is
* used instead.
*/
/*
* The link up bit determines when link is up on autoneg. The sync ok
* gets set once both sides sync up and agree upon link. Stable link
* can be determined by checking for both link up and link sync ok
*/
mac->serdes_has_link = true;
/* Detect and store PCS speed */
if (pcs & E1000_PCS_LSTS_SPEED_1000) {
*speed = SPEED_1000;
} else if (pcs & E1000_PCS_LSTS_SPEED_100) {
} else {
}
/* Detect and store PCS duplex */
if (pcs & E1000_PCS_LSTS_DUPLEX_FULL) {
*duplex = FULL_DUPLEX;
} else {
*duplex = HALF_DUPLEX;
}
}
return (E1000_SUCCESS);
}
/*
* e1000_init_rx_addrs_82575 - Initialize receive address's
* @hw: pointer to the HW structure
* @rar_count: receive address registers
*
* Setups the receive address registers by setting the base receive address
* register to the devices MAC address and clearing all the other receive
* address registers to 0.
*/
static void
{
u32 i;
/*
* This function is essentially the same as that of
* e1000_init_rx_addrs_generic. However it also takes care
* of the special case where the register offset of the
* second set of RARs begins elsewhere. This is implicitly taken care by
* function e1000_rar_set_generic.
*/
DEBUGFUNC("e1000_init_rx_addrs_82575");
/* Setup the receive address */
DEBUGOUT("Programming MAC Address into RAR[0]\n");
/* Zero out the other (rar_entry_count - 1) receive addresses */
for (i = 1; i < rar_count; i++) {
}
}
/*
* e1000_update_mc_addr_list_82575 - Update Multicast addresses
* @hw: pointer to the HW structure
* @mc_addr_list: array of multicast addresses to program
* @mc_addr_count: number of multicast addresses to program
* @rar_used_count: the first RAR register free to program
* @rar_count: total number of supported Receive Address Registers
*
* Updates the Receive Address Registers and Multicast Table Array.
* The caller must have a packed mc_addr_list of multicast addresses.
* The parameter rar_count will usually be hw->mac.rar_entry_count
* unless there are workarounds that change this.
*/
static void
{
u32 i;
/*
* This function is essentially the same as that of
* e1000_update_mc_addr_list_generic. However it also takes care
* of the special case where the register offset of the
* second set of RARs begins elsewhere. This is implicitly taken care by
* function e1000_rar_set_generic.
*/
DEBUGFUNC("e1000_update_mc_addr_list_82575");
/*
* Load the first set of multicast addresses into the exact
* filters (RAR). If there are not enough to fill the RAR
* array, clear the filters.
*/
for (i = rar_used_count; i < rar_count; i++) {
if (mc_addr_count) {
} else {
}
}
/* Clear the old settings from the MTA */
DEBUGOUT("Clearing MTA\n");
}
/* Load any remaining multicast addresses into the hash table. */
for (; mc_addr_count > 0; mc_addr_count--) {
}
}
/*
* e1000_shutdown_fiber_serdes_link_82575 - Remove link during power down
* @hw: pointer to the HW structure
*
* In the case of fiber serdes shut down optics and PCS on driver unload
* when management pass thru is not enabled.
*/
void
{
u16 eeprom_data = 0;
return;
/*
* If APM is not enabled in the EEPROM and management interface is
* not enabled, then power down.
*/
if (!(eeprom_data & E1000_NVM_APME_82575) &&
/* Disable PCS to turn off link */
reg &= ~E1000_PCS_CFG_PCS_EN;
/* shutdown the laser */
/* flush the write to verfiy completion */
msec_delay(1);
}
}
/*
* e1000_reset_hw_82575 - Reset hardware
* @hw: pointer to the HW structure
*
* This resets the hardware into a known state.
*/
static s32
{
DEBUGFUNC("e1000_reset_hw_82575");
/*
* Prevent the PCI-E bus from sticking if there is no TLP connection
*/
if (ret_val) {
DEBUGOUT("PCI-E Master disable polling has failed.\n");
}
DEBUGOUT("Masking off all interrupts\n");
msec_delay(10);
DEBUGOUT("Issuing a global reset to MAC\n");
if (ret_val) {
/*
* When auto config read does not complete, do not
* return with an error. This can happen in situations
* where there is no eeprom and prevents getting link.
*/
DEBUGOUT("Auto Read Done did not complete\n");
}
/* If EEPROM is not present, run manual init scripts */
(void) e1000_reset_init_script_82575(hw);
/* Clear any pending interrupt events. */
(void) e1000_check_alt_mac_addr_generic(hw);
return (ret_val);
}
/*
* e1000_init_hw_82575 - Initialize hardware
* @hw: pointer to the HW structure
*
* This inits the hardware readying it for operation.
*/
static s32
{
DEBUGFUNC("e1000_init_hw_82575");
/* Initialize identification LED */
if (ret_val) {
DEBUGOUT("Error initializing identification LED\n");
/* This is not fatal and we should not stop init due to this */
}
/* Disabling VLAN filtering */
DEBUGOUT("Initializing the IEEE VLAN\n");
/* Setup the receive address */
/* Zero out the Multicast HASH table */
DEBUGOUT("Zeroing the MTA\n");
for (i = 0; i < mac->mta_reg_count; i++)
/* Setup link and flow control */
/*
* Clear all of the statistics registers (clear on read). It is
* important that we do this after we have tried to establish link
* because the symbol error count will increment wildly if there
* is no link.
*/
return (ret_val);
}
/*
* e1000_setup_copper_link_82575 - Configure copper link settings
* @hw: pointer to the HW structure
*
* Configures the link for auto-neg or forced speed and duplex. Then we check
* for link, once link is established calls to configure collision distance
* and flow control are called.
*/
static s32
{
bool link;
DEBUGFUNC("e1000_setup_copper_link_82575");
ctrl |= E1000_CTRL_SLU;
case e1000_phy_m88:
break;
case e1000_phy_igp_3:
/* Setup activity LED */
break;
default:
ret_val = -E1000_ERR_PHY;
break;
}
if (ret_val)
goto out;
/*
* Setup autoneg and flow control advertisement
* and perform autonegotiation.
*/
if (ret_val)
goto out;
} else {
/*
* PHY will be set to 10H, 10F, 100H or 100F
* depending on user settings.
*/
DEBUGOUT("Forcing Speed and Duplex\n");
if (ret_val) {
DEBUGOUT("Error Forcing Speed and Duplex\n");
goto out;
}
}
if (ret_val)
goto out;
/*
* Check link status. Wait up to 100 microseconds for link to become
* valid.
*/
10,
&link);
if (ret_val)
goto out;
if (link) {
DEBUGOUT("Valid link established!!!\n");
/* Config the MAC and PHY after link is up */
} else {
DEBUGOUT("Unable to establish link!!!\n");
}
out:
return (ret_val);
}
/*
* @hw: pointer to the HW structure
*
* Configures speed and duplex for fiber and serdes links.
*/
static s32
{
DEBUGFUNC("e1000_setup_fiber_serdes_link_82575");
/*
* On the 82575, SerDes loopback mode persists until it is
* explicitly turned off or a power cycle is performed. A read to
* the register does not indicate its status. Therefore, we ensure
* loopback mode is disabled during initialization.
*/
/* Force link up, set 1gb, set both sw defined pins */
reg |= E1000_CTRL_SLU |
/* Power on phy for 82576 fiber adapters */
}
/* Set switch control to serdes energy detect */
/*
* New SerDes mode allows for forcing speed or autonegotiating speed
* at 1gb. Autoneg should be default set by most drivers. This is the
* mode that will be compatible with older link partners and switches.
*/
/* Set PCS register for autoneg */
E1000_PCS_LCTL_FDV_FULL | /* SerDes Full duplex */
E1000_PCS_LCTL_AN_ENABLE | /* Enable Autoneg */
E1000_PCS_LCTL_AN_RESTART; /* Restart autoneg */
} else {
/* Set PCS register for forced speed */
E1000_PCS_LCTL_FSV_1000 | /* Force 1000 */
E1000_PCS_LCTL_FDV_FULL | /* SerDes Full duplex */
E1000_PCS_LCTL_FSD | /* Force Speed */
E1000_PCS_LCTL_FORCE_LINK; /* Force Link */
}
}
return (E1000_SUCCESS);
}
/*
* e1000_valid_led_default_82575 - Verify a valid default LED config
* @hw: pointer to the HW structure
* @data: pointer to the NVM (EEPROM)
*
* Read the EEPROM for the current default LED configuration. If the
* LED configuration is not valid, set to a valid LED configuration.
*/
static s32
{
DEBUGFUNC("e1000_valid_led_default_82575");
if (ret_val) {
DEBUGOUT("NVM Read Error\n");
goto out;
}
case e1000_media_type_fiber:
break;
case e1000_media_type_copper:
default:
*data = ID_LED_DEFAULT;
break;
}
}
out:
return (ret_val);
}
/*
* e1000_configure_pcs_link_82575 - Configure PCS link
* @hw: pointer to the HW structure
*
* Configure the physical coding sub-layer (PCS) link. The PCS link is
* only used on copper connections where the serialized gigabit media
* independent interface (sgmii) is being used. Configures the link
*/
static s32
{
DEBUGFUNC("e1000_configure_pcs_link_82575");
goto out;
/* For SGMII, we need to issue a PCS autoneg restart */
/* AN time out should be disabled for SGMII mode */
reg &= ~(E1000_PCS_LCTL_AN_TIMEOUT);
/* Make sure forced speed and force link are not set */
/*
* The PHY should be setup prior to calling this function.
* All we need to do is restart autoneg and enable autoneg.
*/
} else {
/* Set PCS register for forced speed */
/* Turn off bits for full duplex, speed, and autoneg */
reg &= ~(E1000_PCS_LCTL_FSV_1000 |
/* Check for duplex first */
/* Now set speed */
/* Force speed and force link */
reg |= E1000_PCS_LCTL_FSD |
DEBUGOUT1("Wrote 0x%08X to PCS_LCTL to configure forced link\n",
reg);
}
out:
return (E1000_SUCCESS);
}
/*
* e1000_sgmii_active_82575 - Return sgmii state
* @hw: pointer to the HW structure
*
* 82575 silicon has a serialized gigabit media independent interface (sgmii)
* which can be enabled for use in the embedded applications. Simply
* return the current state of the sgmii interface.
*/
static bool
{
DEBUGFUNC("e1000_sgmii_active_82575");
return (false);
return (dev_spec->sgmii_active);
}
/*
* e1000_reset_init_script_82575 - Inits HW defaults after reset
* @hw: pointer to the HW structure
*
* Inits recommended HW defaults after a reset when there is no EEPROM
* detected. This is only for the 82575.
*/
static s32
{
DEBUGFUNC("e1000_reset_init_script_82575");
DEBUGOUT("Running reset init script for 82575\n");
/* SerDes configuration via SERDESCTRL */
0x00, 0x0C);
0x01, 0x78);
0x1B, 0x23);
0x23, 0x15);
/* CCM configuration via CCMCTL register */
0x14, 0x00);
0x10, 0x00);
/* PCIe lanes configuration */
0x00, 0xEC);
0x61, 0xDF);
0x34, 0x05);
0x2F, 0x81);
/* PCIe PLL Configuration */
0x02, 0x47);
0x14, 0x00);
0x10, 0x00);
}
return (E1000_SUCCESS);
}
/*
* e1000_read_mac_addr_82575 - Read device MAC address
* @hw: pointer to the HW structure
*/
static s32
{
DEBUGFUNC("e1000_read_mac_addr_82575");
return (ret_val);
}
/*
* e1000_power_down_phy_copper_82575 - Remove link during PHY power down
* @hw: pointer to the HW structure
*
* In the case of a PHY power down to save power, or to turn off link during a
* driver unload, or wake on lan is not enabled, remove the link.
*/
static void
{
return;
/* If the management interface is not enabled, then power down */
}
/*
* e1000_clear_hw_cntrs_82575 - Clear device specific hardware counters
* @hw: pointer to the HW structure
*
* Clears the hardware counters by reading the counter registers.
*/
static void
{
DEBUGFUNC("e1000_clear_hw_cntrs_82575");
/* This register should not be read in copper configurations */
}
/*
* e1000_rx_fifo_flush_82575 - Clean rx fifo after RX enable
* @hw: pointer to the HW structure
*
* After rx enable if managability is enabled then there is likely some
* bad data at the start of the fifo and possibly in the DMA fifo. This
* function clears the fifos and flushes any packets that came in as rx was
* being enabled.
*/
void
{
int i, ms_wait;
DEBUGFUNC("e1000_rx_fifo_workaround_82575");
return;
/* Disable all RX queues */
for (i = 0; i < 4; i++) {
rxdctl[i] & ~E1000_RXDCTL_QUEUE_ENABLE);
}
/* Poll all queues to verify they have shut down */
msec_delay(1);
rx_enabled = 0;
for (i = 0; i < 4; i++)
if (!(rx_enabled & E1000_RXDCTL_QUEUE_ENABLE))
break;
}
if (ms_wait == 10)
DEBUGOUT("Queue disable timed out after 10ms\n");
/*
* Clear RLPML, RCTL.SBP, RFCTL.LEF, and set RCTL.LPE so that all
* incoming packets are rejected. Set enable and wait 2ms so that
* any packet that was coming in as RCTL.EN was set is flushed
*/
msec_delay(2);
/*
* Enable RX queues that were previously enabled and restore our
* previous state
*/
for (i = 0; i < 4; i++)
/* Flush receive errors generated by workaround */
}