9d26e4fc021e249c93c2861629cc665e4f5bd4d6Robert Mustacchi * This file and its contents are supplied under the terms of the
9d26e4fc021e249c93c2861629cc665e4f5bd4d6Robert Mustacchi * Common Development and Distribution License ("CDDL"), version 1.0.
9d26e4fc021e249c93c2861629cc665e4f5bd4d6Robert Mustacchi * You may only use this file in accordance with the terms of version
9d26e4fc021e249c93c2861629cc665e4f5bd4d6Robert Mustacchi * 1.0 of the CDDL.
9d26e4fc021e249c93c2861629cc665e4f5bd4d6Robert Mustacchi * A full copy of the text of the CDDL should have accompanied this
9d26e4fc021e249c93c2861629cc665e4f5bd4d6Robert Mustacchi * source. A copy of the CDDL is also available via the Internet at
9d26e4fc021e249c93c2861629cc665e4f5bd4d6Robert Mustacchi * Copyright 2015 OmniTI Computer Consulting, Inc. All rights reserved.
9d26e4fc021e249c93c2861629cc665e4f5bd4d6Robert Mustacchi * Copyright 2016 Joyent, Inc.
9d26e4fc021e249c93c2861629cc665e4f5bd4d6Robert Mustacchi * Please see i40e_main.c for an introduction to the device driver, its layout,
9d26e4fc021e249c93c2861629cc665e4f5bd4d6Robert Mustacchi * Configuration constants. Note that the hardware defines a minimum bound of 32
9d26e4fc021e249c93c2861629cc665e4f5bd4d6Robert Mustacchi * descriptors and requires that the programming of the descriptor lengths be
9d26e4fc021e249c93c2861629cc665e4f5bd4d6Robert Mustacchi * aligned in units of 32 descriptors.
9d26e4fc021e249c93c2861629cc665e4f5bd4d6Robert Mustacchi * Sizes used for asynchronous processing of the adminq. We allocate a fixed
9d26e4fc021e249c93c2861629cc665e4f5bd4d6Robert Mustacchi * size buffer for each instance of the device during attach time, rather than
9d26e4fc021e249c93c2861629cc665e4f5bd4d6Robert Mustacchi * allocating and freeing one during interrupt processing.
9d26e4fc021e249c93c2861629cc665e4f5bd4d6Robert Mustacchi * We also define the descriptor size of the admin queue here.
9d26e4fc021e249c93c2861629cc665e4f5bd4d6Robert Mustacchi * Note, while the min and maximum values are based upon the sizing of the ring
9d26e4fc021e249c93c2861629cc665e4f5bd4d6Robert Mustacchi * itself, the default is taken from ixgbe without much thought. It's basically
9d26e4fc021e249c93c2861629cc665e4f5bd4d6Robert Mustacchi * been cargo culted. See i40e_transceiver.c for a bit more information.
9d26e4fc021e249c93c2861629cc665e4f5bd4d6Robert Mustacchi * Valid MTU ranges. Note that the XL710's maximum payload is actually 9728.
9d26e4fc021e249c93c2861629cc665e4f5bd4d6Robert Mustacchi * However, we need to adjust for the ETHERFCSL (4 bytes) and the Ethernet VLAN
9d26e4fc021e249c93c2861629cc665e4f5bd4d6Robert Mustacchi * header size (18 bytes) to get the actual maximum frame we can use. If
9d26e4fc021e249c93c2861629cc665e4f5bd4d6Robert Mustacchi * different adapters end up with different sizes, we should make this value a
9d26e4fc021e249c93c2861629cc665e4f5bd4d6Robert Mustacchi * bit more dynamic.
9d26e4fc021e249c93c2861629cc665e4f5bd4d6Robert Mustacchi * Interrupt throttling related values. Interrupt throttling values are defined
9d26e4fc021e249c93c2861629cc665e4f5bd4d6Robert Mustacchi * in two microsecond increments. Note that a value of zero basically says do no
9d26e4fc021e249c93c2861629cc665e4f5bd4d6Robert Mustacchi * ITR activity. A helpful way to think about these is that setting the ITR to a
9d26e4fc021e249c93c2861629cc665e4f5bd4d6Robert Mustacchi * value will allow a certain number of interrupts per second.
9d26e4fc021e249c93c2861629cc665e4f5bd4d6Robert Mustacchi * Our default values for RX allow 20k interrupts per second while our default
9d26e4fc021e249c93c2861629cc665e4f5bd4d6Robert Mustacchi * values for TX allow for 5k interrupts per second. For other class interrupts,
9d26e4fc021e249c93c2861629cc665e4f5bd4d6Robert Mustacchi * we limit ourselves to a rate of 2k/s.
9d26e4fc021e249c93c2861629cc665e4f5bd4d6Robert Mustacchi * Indexes into the three ITR registers that we have.
9d26e4fc021e249c93c2861629cc665e4f5bd4d6Robert Mustacchi * Table 1-5 of the PRM notes that LSO supports up to 256 KB.
9d26e4fc021e249c93c2861629cc665e4f5bd4d6Robert Mustacchi#define I40E_CYCLIC_PERIOD NANOSEC /* 1 second */
9d26e4fc021e249c93c2861629cc665e4f5bd4d6Robert Mustacchi#define I40E_DRAIN_RX_WAIT (500 * MILLISEC) /* In us */
9d26e4fc021e249c93c2861629cc665e4f5bd4d6Robert Mustacchi * All the other queue types for are defined by the common code. However, this
9d26e4fc021e249c93c2861629cc665e4f5bd4d6Robert Mustacchi * is the constant to indicate that it's terminated.
9d26e4fc021e249c93c2861629cc665e4f5bd4d6Robert Mustacchi * See the comments in i40e_transceiver.c as to the purpose of this value and
9d26e4fc021e249c93c2861629cc665e4f5bd4d6Robert Mustacchi * how it's used to ensure that the IP header is eventually aligned when it's
9d26e4fc021e249c93c2861629cc665e4f5bd4d6Robert Mustacchi * received by the OS.
9d26e4fc021e249c93c2861629cc665e4f5bd4d6Robert Mustacchi * The XL710 controller has a limit of eight buffers being allowed to be used
9d26e4fc021e249c93c2861629cc665e4f5bd4d6Robert Mustacchi * for the transmission of a single frame. This is defined in 8.4.1 - Transmit
9d26e4fc021e249c93c2861629cc665e4f5bd4d6Robert Mustacchi * Packet in System Memory.
9d26e4fc021e249c93c2861629cc665e4f5bd4d6Robert Mustacchi * Sizing to determine the amount of available descriptors at which we'll
9d26e4fc021e249c93c2861629cc665e4f5bd4d6Robert Mustacchi * consider ourselves blocked. Also, when we have these available, we'll then
9d26e4fc021e249c93c2861629cc665e4f5bd4d6Robert Mustacchi * consider ourselves available to transmit to MAC again. Strictly speaking, the
9d26e4fc021e249c93c2861629cc665e4f5bd4d6Robert Mustacchi * MAX is based on the ring size. The default sizing is based on ixgbe.
9d26e4fc021e249c93c2861629cc665e4f5bd4d6Robert Mustacchi#define I40E_MIN_TX_BLOCK_THRESH I40E_TX_MAX_COOKIE
9d26e4fc021e249c93c2861629cc665e4f5bd4d6Robert Mustacchi#define I40E_DEF_TX_BLOCK_THRESH I40E_MIN_TX_BLOCK_THRESH
9d26e4fc021e249c93c2861629cc665e4f5bd4d6Robert Mustacchi * Sizing for DMA thresholds. These are used to indicate whether or not we
9d26e4fc021e249c93c2861629cc665e4f5bd4d6Robert Mustacchi * should perform a bcopy or a DMA binding of a given message block. The range
9d26e4fc021e249c93c2861629cc665e4f5bd4d6Robert Mustacchi * allows for setting things such that we'll always do a bcopy (a high value) or
9d26e4fc021e249c93c2861629cc665e4f5bd4d6Robert Mustacchi * always perform a DMA binding (a low value).
9d26e4fc021e249c93c2861629cc665e4f5bd4d6Robert Mustacchi * Resource sizing counts. There are various aspects of hardware where we may
9d26e4fc021e249c93c2861629cc665e4f5bd4d6Robert Mustacchi * have some variable number of elements that we need to handle. Such as the
9d26e4fc021e249c93c2861629cc665e4f5bd4d6Robert Mustacchi * hardware capabilities and switch capacities. We cannot know a priori how many
9d26e4fc021e249c93c2861629cc665e4f5bd4d6Robert Mustacchi * elements to do, so instead we take a starting guess and then will grow it up
9d26e4fc021e249c93c2861629cc665e4f5bd4d6Robert Mustacchi * to an upper bound on a number of elements, to limit memory consumption in
9d26e4fc021e249c93c2861629cc665e4f5bd4d6Robert Mustacchi * case of a hardware bug.
9d26e4fc021e249c93c2861629cc665e4f5bd4d6Robert Mustacchi * Host Memory Context related constants.
9d26e4fc021e249c93c2861629cc665e4f5bd4d6Robert Mustacchi#define I40E_HMC_RX_DBUFF_MAX (16 * 1024 - 128)
9d26e4fc021e249c93c2861629cc665e4f5bd4d6Robert Mustacchi * Whenever we establish and create a VSI, we need to assign some number of
9d26e4fc021e249c93c2861629cc665e4f5bd4d6Robert Mustacchi * queues that it's allowed to access from the PF. Because we only have a single
9d26e4fc021e249c93c2861629cc665e4f5bd4d6Robert Mustacchi * VSI per PF at this time, we assign it all the queues.
9d26e4fc021e249c93c2861629cc665e4f5bd4d6Robert Mustacchi * Many of the devices support what's called Data-center Bridging. Which is a
9d26e4fc021e249c93c2861629cc665e4f5bd4d6Robert Mustacchi * feature that we don't have much use of at this time. However, we still need
9d26e4fc021e249c93c2861629cc665e4f5bd4d6Robert Mustacchi * to fill in this information. We follow the guidance of the note in Table 7-80
9d26e4fc021e249c93c2861629cc665e4f5bd4d6Robert Mustacchi * which talks about bytes 62-77. It says that if we don't want to assign
9d26e4fc021e249c93c2861629cc665e4f5bd4d6Robert Mustacchi * anything to traffic classes, we should set the field to zero. Effectively
9d26e4fc021e249c93c2861629cc665e4f5bd4d6Robert Mustacchi * this means that everything in the system is assigned to traffic class zero.
9d26e4fc021e249c93c2861629cc665e4f5bd4d6Robert Mustacchi * This defines the error mask that we care about from rx descriptors. Currently
9d26e4fc021e249c93c2861629cc665e4f5bd4d6Robert Mustacchi * we're only concerned with the general errors and oversize errors.
9d26e4fc021e249c93c2861629cc665e4f5bd4d6Robert Mustacchi#define I40E_RX_ERR_BITS ((1 << I40E_RX_DESC_ERROR_RXE_SHIFT) | \
9d26e4fc021e249c93c2861629cc665e4f5bd4d6Robert Mustacchi * Property sizing macros for firmware versions, etc. They need to be large
9d26e4fc021e249c93c2861629cc665e4f5bd4d6Robert Mustacchi * enough to hold 32-bit quantities transformed to strings as %d.%d or %x.
9d26e4fc021e249c93c2861629cc665e4f5bd4d6Robert Mustacchi * We currently consolidate some overrides that we use in the code here. These
9d26e4fc021e249c93c2861629cc665e4f5bd4d6Robert Mustacchi * will be gone in the fullness of time, but as we're bringing up the device,
9d26e4fc021e249c93c2861629cc665e4f5bd4d6Robert Mustacchi * this is what we use.
9d26e4fc021e249c93c2861629cc665e4f5bd4d6Robert Mustacchi * It seems reasonable to cast this to void because the only reason that we
9d26e4fc021e249c93c2861629cc665e4f5bd4d6Robert Mustacchi * should be getting a DDI_FAILURE is due to the fact that we specify addresses
9d26e4fc021e249c93c2861629cc665e4f5bd4d6Robert Mustacchi * out of range. Because we specify no offset or address, it shouldn't happen.
9d26e4fc021e249c93c2861629cc665e4f5bd4d6Robert Mustacchi#define I40E_DMA_SYNC(handle, flag) ASSERT0(ddi_dma_sync( \
9d26e4fc021e249c93c2861629cc665e4f5bd4d6Robert Mustacchi#else /* !DEBUG */
9d26e4fc021e249c93c2861629cc665e4f5bd4d6Robert Mustacchi#define I40E_DMA_SYNC(handle, flag) ((void) ddi_dma_sync( \
9d26e4fc021e249c93c2861629cc665e4f5bd4d6Robert Mustacchi#endif /* DEBUG */
9d26e4fc021e249c93c2861629cc665e4f5bd4d6Robert Mustacchi * Constants related to ring startup and teardown. These refer to the amount of
9d26e4fc021e249c93c2861629cc665e4f5bd4d6Robert Mustacchi * time that we're willing to wait for a ring to spin up and spin down.
9d26e4fc021e249c93c2861629cc665e4f5bd4d6Robert Mustacchi * Bit flags for attach_progress
9d26e4fc021e249c93c2861629cc665e4f5bd4d6Robert Mustacchi I40E_ATTACH_PCI_CONFIG = 0x0001, /* PCI config setup */
9d26e4fc021e249c93c2861629cc665e4f5bd4d6Robert Mustacchi I40E_ATTACH_REGS_MAP = 0x0002, /* Registers mapped */
9d26e4fc021e249c93c2861629cc665e4f5bd4d6Robert Mustacchi I40E_ATTACH_PROPS = 0x0004, /* Properties initialized */
9d26e4fc021e249c93c2861629cc665e4f5bd4d6Robert Mustacchi I40E_ATTACH_ALLOC_INTR = 0x0008, /* Interrupts allocated */
9d26e4fc021e249c93c2861629cc665e4f5bd4d6Robert Mustacchi I40E_ATTACH_ALLOC_RINGSLOCKS = 0x0010, /* Rings & locks allocated */
9d26e4fc021e249c93c2861629cc665e4f5bd4d6Robert Mustacchi I40E_ATTACH_ADD_INTR = 0x0020, /* Intr handlers added */
9d26e4fc021e249c93c2861629cc665e4f5bd4d6Robert Mustacchi I40E_ATTACH_COMMON_CODE = 0x0040, /* Intel code initialized */
9d26e4fc021e249c93c2861629cc665e4f5bd4d6Robert Mustacchi I40E_ATTACH_INIT = 0x0080, /* Device initialized */
9d26e4fc021e249c93c2861629cc665e4f5bd4d6Robert Mustacchi I40E_ATTACH_STATS = 0x0200, /* Kstats created */
9d26e4fc021e249c93c2861629cc665e4f5bd4d6Robert Mustacchi I40E_ATTACH_MAC = 0x0800, /* MAC registered */
9d26e4fc021e249c93c2861629cc665e4f5bd4d6Robert Mustacchi I40E_ATTACH_ENABLE_INTR = 0x1000, /* DDI interrupts enabled */
9d26e4fc021e249c93c2861629cc665e4f5bd4d6Robert Mustacchi I40E_ATTACH_FM_INIT = 0x2000, /* FMA initialized */
9d26e4fc021e249c93c2861629cc665e4f5bd4d6Robert Mustacchi I40E_ATTACH_LINK_TIMER = 0x4000, /* link check timer */
9d26e4fc021e249c93c2861629cc665e4f5bd4d6Robert Mustacchi * State flags that what's going on in in the device. Some of these state flags
9d26e4fc021e249c93c2861629cc665e4f5bd4d6Robert Mustacchi * indicate some aspirational work that needs to happen in the driver.
9d26e4fc021e249c93c2861629cc665e4f5bd4d6Robert Mustacchi * I40E_UNKNOWN: The device has yet to be started.
9d26e4fc021e249c93c2861629cc665e4f5bd4d6Robert Mustacchi * I40E_INITIALIZED: The device has been fully attached.
9d26e4fc021e249c93c2861629cc665e4f5bd4d6Robert Mustacchi * I40E_STARTED: The device has come out of the GLDV3 start routine.
9d26e4fc021e249c93c2861629cc665e4f5bd4d6Robert Mustacchi * I40E_SUSPENDED: The device is suspended and I/O among other things
9d26e4fc021e249c93c2861629cc665e4f5bd4d6Robert Mustacchi * should not occur. This happens because of an actual
9d26e4fc021e249c93c2861629cc665e4f5bd4d6Robert Mustacchi * DDI_SUSPEND or interrupt adjustments.
9d26e4fc021e249c93c2861629cc665e4f5bd4d6Robert Mustacchi * I40E_STALL: The tx stall detection logic has found a stall.
9d26e4fc021e249c93c2861629cc665e4f5bd4d6Robert Mustacchi * I40E_OVERTEMP: The device has encountered a temperature alarm.
9d26e4fc021e249c93c2861629cc665e4f5bd4d6Robert Mustacchi * I40E_INTR_ADJUST: Our interrupts are being manipulated and therefore we
9d26e4fc021e249c93c2861629cc665e4f5bd4d6Robert Mustacchi * shouldn't be manipulating their state.
9d26e4fc021e249c93c2861629cc665e4f5bd4d6Robert Mustacchi * I40E_ERROR: We've detected an FM error and degraded the device.
9d26e4fc021e249c93c2861629cc665e4f5bd4d6Robert Mustacchi * Definitions for common Intel things that we use and some slightly more usable
9d26e4fc021e249c93c2861629cc665e4f5bd4d6Robert Mustacchitypedef struct i40e_aqc_switch_resource_alloc_element_resp i40e_switch_rsrc_t;
9d26e4fc021e249c93c2861629cc665e4f5bd4d6Robert Mustacchi * Handles and addresses of DMA buffers.
9d26e4fc021e249c93c2861629cc665e4f5bd4d6Robert Mustacchi caddr_t dmab_address; /* Virtual address */
9d26e4fc021e249c93c2861629cc665e4f5bd4d6Robert Mustacchi uint64_t dmab_dma_address; /* DMA (Hardware) address */
9d26e4fc021e249c93c2861629cc665e4f5bd4d6Robert Mustacchi ddi_acc_handle_t dmab_acc_handle; /* Data access handle */
9d26e4fc021e249c93c2861629cc665e4f5bd4d6Robert Mustacchi ddi_dma_handle_t dmab_dma_handle; /* DMA handle */
9d26e4fc021e249c93c2861629cc665e4f5bd4d6Robert Mustacchi size_t dmab_len; /* Data length in the buffer */
9d26e4fc021e249c93c2861629cc665e4f5bd4d6Robert Mustacchi * RX Control Block
9d26e4fc021e249c93c2861629cc665e4f5bd4d6Robert Mustacchitypedef enum {
9d26e4fc021e249c93c2861629cc665e4f5bd4d6Robert Mustacchitypedef union i40e_32byte_rx_desc i40e_rx_desc_t;
9d26e4fc021e249c93c2861629cc665e4f5bd4d6Robert Mustacchi * Receive ring data (used below).
9d26e4fc021e249c93c2861629cc665e4f5bd4d6Robert Mustacchi * RX descriptor ring definitions
9d26e4fc021e249c93c2861629cc665e4f5bd4d6Robert Mustacchi i40e_dma_buffer_t rxd_desc_area; /* DMA buffer of rx desc ring */
9d26e4fc021e249c93c2861629cc665e4f5bd4d6Robert Mustacchi i40e_rx_desc_t *rxd_desc_ring; /* Rx desc ring */
9d26e4fc021e249c93c2861629cc665e4f5bd4d6Robert Mustacchi uint32_t rxd_desc_next; /* Index of next rx desc */
9d26e4fc021e249c93c2861629cc665e4f5bd4d6Robert Mustacchi * RX control block list definitions
9d26e4fc021e249c93c2861629cc665e4f5bd4d6Robert Mustacchi kmutex_t rxd_free_lock; /* Lock to protect free data */
9d26e4fc021e249c93c2861629cc665e4f5bd4d6Robert Mustacchi i40e_rx_control_block_t *rxd_rcb_area; /* Array of control blocks */
9d26e4fc021e249c93c2861629cc665e4f5bd4d6Robert Mustacchi i40e_rx_control_block_t **rxd_work_list; /* Work list of rcbs */
9d26e4fc021e249c93c2861629cc665e4f5bd4d6Robert Mustacchi i40e_rx_control_block_t **rxd_free_list; /* Free list of rcbs */
9d26e4fc021e249c93c2861629cc665e4f5bd4d6Robert Mustacchi uint32_t rxd_rcb_free; /* Number of free rcbs */
9d26e4fc021e249c93c2861629cc665e4f5bd4d6Robert Mustacchi * RX software ring settings
9d26e4fc021e249c93c2861629cc665e4f5bd4d6Robert Mustacchi uint32_t rxd_ring_size; /* Rx descriptor ring size */
9d26e4fc021e249c93c2861629cc665e4f5bd4d6Robert Mustacchi uint32_t rxd_free_list_size; /* Rx free list size */
9d26e4fc021e249c93c2861629cc665e4f5bd4d6Robert Mustacchi * RX outstanding data. This is used to keep track of outstanding loaned
9d26e4fc021e249c93c2861629cc665e4f5bd4d6Robert Mustacchi * descriptors after we've shut down receiving information. Note these
9d26e4fc021e249c93c2861629cc665e4f5bd4d6Robert Mustacchi * are protected by the i40e_t`i40e_rx_pending_lock.
9d26e4fc021e249c93c2861629cc665e4f5bd4d6Robert Mustacchi * Structures for unicast and multicast addresses. Note that we keep the VSI id
9d26e4fc021e249c93c2861629cc665e4f5bd4d6Robert Mustacchi * around for unicast addresses, since they may belong to different VSIs.
9d26e4fc021e249c93c2861629cc665e4f5bd4d6Robert Mustacchi * However, since all multicast addresses belong to the default VSI, we don't
9d26e4fc021e249c93c2861629cc665e4f5bd4d6Robert Mustacchi * duplicate that information.
9d26e4fc021e249c93c2861629cc665e4f5bd4d6Robert Mustacchi * Collection of RX statistics on a given queue.
9d26e4fc021e249c93c2861629cc665e4f5bd4d6Robert Mustacchi * The i40e hardware does not maintain statistics on a per-ring basis,
9d26e4fc021e249c93c2861629cc665e4f5bd4d6Robert Mustacchi * only on a per-PF and per-VSI level. As such, to satisfy the GLDv3, we
9d26e4fc021e249c93c2861629cc665e4f5bd4d6Robert Mustacchi * need to maintain our own stats for packets and bytes.
9d26e4fc021e249c93c2861629cc665e4f5bd4d6Robert Mustacchi kstat_named_t irxs_bytes; /* Bytes in on queue */
9d26e4fc021e249c93c2861629cc665e4f5bd4d6Robert Mustacchi kstat_named_t irxs_packets; /* Packets in on queue */
9d26e4fc021e249c93c2861629cc665e4f5bd4d6Robert Mustacchi * The following set of stats cover non-checksum data path issues.
9d26e4fc021e249c93c2861629cc665e4f5bd4d6Robert Mustacchi kstat_named_t irxs_rx_desc_error; /* Error bit set on desc */
9d26e4fc021e249c93c2861629cc665e4f5bd4d6Robert Mustacchi kstat_named_t irxs_rx_copy_nomem; /* allocb failure for copy */
9d26e4fc021e249c93c2861629cc665e4f5bd4d6Robert Mustacchi kstat_named_t irxs_rx_intr_limit; /* Hit i40e_rx_limit_per_intr */
9d26e4fc021e249c93c2861629cc665e4f5bd4d6Robert Mustacchi kstat_named_t irxs_rx_bind_norcb; /* No replacement rcb free */
9d26e4fc021e249c93c2861629cc665e4f5bd4d6Robert Mustacchi kstat_named_t irxs_rx_bind_nomp; /* No mblk_t in bind rcb */
9d26e4fc021e249c93c2861629cc665e4f5bd4d6Robert Mustacchi * The following set of statistics covers rx checksum related activity.
9d26e4fc021e249c93c2861629cc665e4f5bd4d6Robert Mustacchi * These are all primarily set in i40e_rx_hcksum. If rx checksum
9d26e4fc021e249c93c2861629cc665e4f5bd4d6Robert Mustacchi * activity is disabled, then these should all be zero.
9d26e4fc021e249c93c2861629cc665e4f5bd4d6Robert Mustacchi kstat_named_t irxs_hck_v4hdrok; /* Valid IPv4 Header */
9d26e4fc021e249c93c2861629cc665e4f5bd4d6Robert Mustacchi kstat_named_t irxs_hck_l4hdrok; /* Valid L4 Header */
9d26e4fc021e249c93c2861629cc665e4f5bd4d6Robert Mustacchi kstat_named_t irxs_hck_unknown; /* !pinfo.known */
9d26e4fc021e249c93c2861629cc665e4f5bd4d6Robert Mustacchi kstat_named_t irxs_hck_nol3l4p; /* Missing L3L4P bit in desc */
9d26e4fc021e249c93c2861629cc665e4f5bd4d6Robert Mustacchi kstat_named_t irxs_hck_iperr; /* IPE error bit set */
9d26e4fc021e249c93c2861629cc665e4f5bd4d6Robert Mustacchi kstat_named_t irxs_hck_eiperr; /* EIPE error bit set */
9d26e4fc021e249c93c2861629cc665e4f5bd4d6Robert Mustacchi kstat_named_t irxs_hck_l4err; /* L4E error bit set */
9d26e4fc021e249c93c2861629cc665e4f5bd4d6Robert Mustacchi kstat_named_t irxs_hck_v6skip; /* IPv6 case hw fails on */
9d26e4fc021e249c93c2861629cc665e4f5bd4d6Robert Mustacchi kstat_named_t irxs_hck_set; /* Total times we set cksum */
9d26e4fc021e249c93c2861629cc665e4f5bd4d6Robert Mustacchi kstat_named_t irxs_hck_miss; /* Times with zero cksum bits */
9d26e4fc021e249c93c2861629cc665e4f5bd4d6Robert Mustacchi * Collection of TX Statistics on a given queue
9d26e4fc021e249c93c2861629cc665e4f5bd4d6Robert Mustacchi kstat_named_t itxs_bytes; /* Bytes out on queue */
9d26e4fc021e249c93c2861629cc665e4f5bd4d6Robert Mustacchi kstat_named_t itxs_packets; /* Packets out on queue */
9d26e4fc021e249c93c2861629cc665e4f5bd4d6Robert Mustacchi kstat_named_t itxs_descriptors; /* Descriptors issued */
9d26e4fc021e249c93c2861629cc665e4f5bd4d6Robert Mustacchi kstat_named_t itxs_recycled; /* Descriptors reclaimed */
9d26e4fc021e249c93c2861629cc665e4f5bd4d6Robert Mustacchi * Various failure conditions.
9d26e4fc021e249c93c2861629cc665e4f5bd4d6Robert Mustacchi kstat_named_t itxs_hck_meoifail; /* ether offload failures */
9d26e4fc021e249c93c2861629cc665e4f5bd4d6Robert Mustacchi kstat_named_t itxs_hck_nol2info; /* Missing l2 info */
9d26e4fc021e249c93c2861629cc665e4f5bd4d6Robert Mustacchi kstat_named_t itxs_hck_nol3info; /* Missing l3 info */
9d26e4fc021e249c93c2861629cc665e4f5bd4d6Robert Mustacchi kstat_named_t itxs_hck_nol4info; /* Missing l4 info */
9d26e4fc021e249c93c2861629cc665e4f5bd4d6Robert Mustacchi kstat_named_t itxs_hck_badl3; /* Not IPv4/IPv6 */
9d26e4fc021e249c93c2861629cc665e4f5bd4d6Robert Mustacchi kstat_named_t itxs_hck_badl4; /* Bad L4 Paylaod */
9d26e4fc021e249c93c2861629cc665e4f5bd4d6Robert Mustacchi kstat_named_t itxs_err_notcb; /* No tcb's available */
9d26e4fc021e249c93c2861629cc665e4f5bd4d6Robert Mustacchi kstat_named_t itxs_err_nodescs; /* No tcb's available */
9d26e4fc021e249c93c2861629cc665e4f5bd4d6Robert Mustacchi kstat_named_t itxs_err_context; /* Total context failures */
9d26e4fc021e249c93c2861629cc665e4f5bd4d6Robert Mustacchi kstat_named_t itxs_num_unblocked; /* Number of MAC unblocks */
9d26e4fc021e249c93c2861629cc665e4f5bd4d6Robert Mustacchi * An instance of an XL710 transmit/receive queue pair. This currently
9d26e4fc021e249c93c2861629cc665e4f5bd4d6Robert Mustacchi * represents a combination of both a transmit and receive ring, though they
9d26e4fc021e249c93c2861629cc665e4f5bd4d6Robert Mustacchi * should really be split apart into separate logical structures. Unfortunately,
9d26e4fc021e249c93c2861629cc665e4f5bd4d6Robert Mustacchi * during initial work we mistakenly joined them together.
9d26e4fc021e249c93c2861629cc665e4f5bd4d6Robert Mustacchi /* Receive-side structures. */
9d26e4fc021e249c93c2861629cc665e4f5bd4d6Robert Mustacchi mac_ring_handle_t itrq_macrxring; /* Receive ring handle. */
9d26e4fc021e249c93c2861629cc665e4f5bd4d6Robert Mustacchi i40e_rx_data_t *itrq_rxdata; /* Receive ring rx data. */
9d26e4fc021e249c93c2861629cc665e4f5bd4d6Robert Mustacchi uint64_t itrq_rxgen; /* Generation number for mac/GLDv3. */
9d26e4fc021e249c93c2861629cc665e4f5bd4d6Robert Mustacchi uint32_t itrq_index; /* Queue index in the PF */
9d26e4fc021e249c93c2861629cc665e4f5bd4d6Robert Mustacchi uint32_t itrq_rx_intrvec; /* Receive interrupt vector. */
9d26e4fc021e249c93c2861629cc665e4f5bd4d6Robert Mustacchi /* Receive-side stats. */
9d26e4fc021e249c93c2861629cc665e4f5bd4d6Robert Mustacchi /* Transmit-side structures. */
9d26e4fc021e249c93c2861629cc665e4f5bd4d6Robert Mustacchi mac_ring_handle_t itrq_mactxring; /* Transmit ring handle. */
9d26e4fc021e249c93c2861629cc665e4f5bd4d6Robert Mustacchi uint32_t itrq_tx_intrvec; /* Transmit interrupt vector. */
9d26e4fc021e249c93c2861629cc665e4f5bd4d6Robert Mustacchi boolean_t itrq_tx_blocked; /* Does MAC think we're blocked? */
9d26e4fc021e249c93c2861629cc665e4f5bd4d6Robert Mustacchi * TX data sizing
9d26e4fc021e249c93c2861629cc665e4f5bd4d6Robert Mustacchi * TX descriptor ring data
9d26e4fc021e249c93c2861629cc665e4f5bd4d6Robert Mustacchi i40e_dma_buffer_t itrq_desc_area; /* DMA buffer of tx desc ring */
9d26e4fc021e249c93c2861629cc665e4f5bd4d6Robert Mustacchi i40e_tx_desc_t *itrq_desc_ring; /* TX Desc ring */
9d26e4fc021e249c93c2861629cc665e4f5bd4d6Robert Mustacchi volatile uint32_t *itrq_desc_wbhead; /* TX write-back index */
9d26e4fc021e249c93c2861629cc665e4f5bd4d6Robert Mustacchi uint32_t itrq_desc_head; /* Last index hw freed */
9d26e4fc021e249c93c2861629cc665e4f5bd4d6Robert Mustacchi uint32_t itrq_desc_tail; /* Index of next free desc */
9d26e4fc021e249c93c2861629cc665e4f5bd4d6Robert Mustacchi uint32_t itrq_desc_free; /* Number of free descriptors */
9d26e4fc021e249c93c2861629cc665e4f5bd4d6Robert Mustacchi * TX control block (tcb) data
9d26e4fc021e249c93c2861629cc665e4f5bd4d6Robert Mustacchi i40e_tx_control_block_t *itrq_tcb_area; /* Array of control blocks */
9d26e4fc021e249c93c2861629cc665e4f5bd4d6Robert Mustacchi i40e_tx_control_block_t **itrq_tcb_work_list; /* In use tcb */
9d26e4fc021e249c93c2861629cc665e4f5bd4d6Robert Mustacchi i40e_tx_control_block_t **itrq_tcb_free_list; /* Available tcb */
9d26e4fc021e249c93c2861629cc665e4f5bd4d6Robert Mustacchi uint32_t itrq_tcb_free; /* Count of free tcb */
9d26e4fc021e249c93c2861629cc665e4f5bd4d6Robert Mustacchi /* Transmit-side stats. */
9d26e4fc021e249c93c2861629cc665e4f5bd4d6Robert Mustacchi * VSI statistics.
9d26e4fc021e249c93c2861629cc665e4f5bd4d6Robert Mustacchi * This mirrors the i40e_eth_stats structure but transforms it into a kstat.
9d26e4fc021e249c93c2861629cc665e4f5bd4d6Robert Mustacchi * Note that the stock statistic structure also includes entries for tx
9d26e4fc021e249c93c2861629cc665e4f5bd4d6Robert Mustacchi * discards. However, this is not actually implemented for the VSI (see Table
9d26e4fc021e249c93c2861629cc665e4f5bd4d6Robert Mustacchi * 7-221), hence why we don't include the member which would always have a value
9d26e4fc021e249c93c2861629cc665e4f5bd4d6Robert Mustacchi * of zero. This choice was made to minimize confusion to someone looking at
9d26e4fc021e249c93c2861629cc665e4f5bd4d6Robert Mustacchi * these, as a value of zero does not necessarily equate to the fact that it's
9d26e4fc021e249c93c2861629cc665e4f5bd4d6Robert Mustacchi * not implemented.
9d26e4fc021e249c93c2861629cc665e4f5bd4d6Robert Mustacchi uint64_t ivs_rx_unknown_protocol; /* rupp */
9d26e4fc021e249c93c2861629cc665e4f5bd4d6Robert Mustacchi * For pf statistics, we opt not to use the standard statistics as defined by
9d26e4fc021e249c93c2861629cc665e4f5bd4d6Robert Mustacchi * the Intel common code. This also currently combines statistics that are
9d26e4fc021e249c93c2861629cc665e4f5bd4d6Robert Mustacchi * global across the entire device.
9d26e4fc021e249c93c2861629cc665e4f5bd4d6Robert Mustacchi uint64_t ips_priority_xon_rx[8]; /* pxonrxc[8] */
9d26e4fc021e249c93c2861629cc665e4f5bd4d6Robert Mustacchi uint64_t ips_priority_xoff_rx[8]; /* pxoffrxc[8] */
9d26e4fc021e249c93c2861629cc665e4f5bd4d6Robert Mustacchi uint64_t ips_priority_xon_tx[8]; /* pxontxc[8] */
9d26e4fc021e249c93c2861629cc665e4f5bd4d6Robert Mustacchi uint64_t ips_priority_xoff_tx[8]; /* pxofftxc[8] */
9d26e4fc021e249c93c2861629cc665e4f5bd4d6Robert Mustacchi uint64_t ips_priority_xon_2_xoff[8]; /* rxon2offcnt[8] */
9d26e4fc021e249c93c2861629cc665e4f5bd4d6Robert Mustacchi uint64_t ips_rx_short_discards; /* mspdc */
9d26e4fc021e249c93c2861629cc665e4f5bd4d6Robert Mustacchi uint64_t ips_tx_dropped_link_down; /* tdold */
9d26e4fc021e249c93c2861629cc665e4f5bd4d6Robert Mustacchi uint64_t ips_rx_unknown_protocol; /* rupp */
9d26e4fc021e249c93c2861629cc665e4f5bd4d6Robert Mustacchi kstat_named_t ipk_rx_size_127; /* prc127 */
9d26e4fc021e249c93c2861629cc665e4f5bd4d6Robert Mustacchi kstat_named_t ipk_rx_size_255; /* prc255 */
9d26e4fc021e249c93c2861629cc665e4f5bd4d6Robert Mustacchi kstat_named_t ipk_rx_size_511; /* prc511 */
9d26e4fc021e249c93c2861629cc665e4f5bd4d6Robert Mustacchi kstat_named_t ipk_rx_size_1023; /* prc1023 */
9d26e4fc021e249c93c2861629cc665e4f5bd4d6Robert Mustacchi kstat_named_t ipk_rx_size_1522; /* prc1522 */
9d26e4fc021e249c93c2861629cc665e4f5bd4d6Robert Mustacchi kstat_named_t ipk_rx_size_9522; /* prc9522 */
9d26e4fc021e249c93c2861629cc665e4f5bd4d6Robert Mustacchi kstat_named_t ipk_tx_size_127; /* ptc127 */
9d26e4fc021e249c93c2861629cc665e4f5bd4d6Robert Mustacchi kstat_named_t ipk_tx_size_255; /* ptc255 */
9d26e4fc021e249c93c2861629cc665e4f5bd4d6Robert Mustacchi kstat_named_t ipk_tx_size_511; /* ptc511 */
9d26e4fc021e249c93c2861629cc665e4f5bd4d6Robert Mustacchi kstat_named_t ipk_tx_size_1023; /* ptc1023 */
9d26e4fc021e249c93c2861629cc665e4f5bd4d6Robert Mustacchi kstat_named_t ipk_tx_size_1522; /* ptc1522 */
9d26e4fc021e249c93c2861629cc665e4f5bd4d6Robert Mustacchi kstat_named_t ipk_tx_size_9522; /* ptc9522 */
9d26e4fc021e249c93c2861629cc665e4f5bd4d6Robert Mustacchi kstat_named_t ipk_link_xon_rx; /* lxonrxc */
9d26e4fc021e249c93c2861629cc665e4f5bd4d6Robert Mustacchi kstat_named_t ipk_link_xoff_rx; /* lxoffrxc */
9d26e4fc021e249c93c2861629cc665e4f5bd4d6Robert Mustacchi kstat_named_t ipk_link_xon_tx; /* lxontxc */
9d26e4fc021e249c93c2861629cc665e4f5bd4d6Robert Mustacchi kstat_named_t ipk_link_xoff_tx; /* lxofftxc */
9d26e4fc021e249c93c2861629cc665e4f5bd4d6Robert Mustacchi kstat_named_t ipk_priority_xon_rx[8]; /* pxonrxc[8] */
9d26e4fc021e249c93c2861629cc665e4f5bd4d6Robert Mustacchi kstat_named_t ipk_priority_xoff_rx[8]; /* pxoffrxc[8] */
9d26e4fc021e249c93c2861629cc665e4f5bd4d6Robert Mustacchi kstat_named_t ipk_priority_xon_tx[8]; /* pxontxc[8] */
9d26e4fc021e249c93c2861629cc665e4f5bd4d6Robert Mustacchi kstat_named_t ipk_priority_xoff_tx[8]; /* pxofftxc[8] */
9d26e4fc021e249c93c2861629cc665e4f5bd4d6Robert Mustacchi kstat_named_t ipk_priority_xon_2_xoff[8]; /* rxon2offcnt[8] */
9d26e4fc021e249c93c2861629cc665e4f5bd4d6Robert Mustacchi kstat_named_t ipk_crc_errors; /* crcerrs */
9d26e4fc021e249c93c2861629cc665e4f5bd4d6Robert Mustacchi kstat_named_t ipk_illegal_bytes; /* illerrc */
9d26e4fc021e249c93c2861629cc665e4f5bd4d6Robert Mustacchi kstat_named_t ipk_mac_local_faults; /* mlfc */
9d26e4fc021e249c93c2861629cc665e4f5bd4d6Robert Mustacchi kstat_named_t ipk_mac_remote_faults; /* mrfc */
9d26e4fc021e249c93c2861629cc665e4f5bd4d6Robert Mustacchi kstat_named_t ipk_rx_length_errors; /* rlec */
9d26e4fc021e249c93c2861629cc665e4f5bd4d6Robert Mustacchi kstat_named_t ipk_rx_vm_discards; /* ldpc */
9d26e4fc021e249c93c2861629cc665e4f5bd4d6Robert Mustacchi kstat_named_t ipk_rx_short_discards; /* mspdc */
9d26e4fc021e249c93c2861629cc665e4f5bd4d6Robert Mustacchi kstat_named_t ipk_tx_dropped_link_down; /* tdold */
9d26e4fc021e249c93c2861629cc665e4f5bd4d6Robert Mustacchi kstat_named_t ipk_rx_unknown_protocol; /* rupp */
9d26e4fc021e249c93c2861629cc665e4f5bd4d6Robert Mustacchi * Resources that are pooled and specific to a given i40e_t.
9d26e4fc021e249c93c2861629cc665e4f5bd4d6Robert Mustacchi * Main i40e per-instance state.
9d26e4fc021e249c93c2861629cc665e4f5bd4d6Robert Mustacchi list_node_t i40e_glink; /* Global list link */
9d26e4fc021e249c93c2861629cc665e4f5bd4d6Robert Mustacchi list_node_t i40e_dlink; /* Device list link */
9d26e4fc021e249c93c2861629cc665e4f5bd4d6Robert Mustacchi kmutex_t i40e_general_lock; /* General device lock */
9d26e4fc021e249c93c2861629cc665e4f5bd4d6Robert Mustacchi * General Data and management
9d26e4fc021e249c93c2861629cc665e4f5bd4d6Robert Mustacchi * Pointers to common code data structures and memory for the common
9d26e4fc021e249c93c2861629cc665e4f5bd4d6Robert Mustacchi struct i40e_aq_get_phy_abilities_resp i40e_phy;
9d26e4fc021e249c93c2861629cc665e4f5bd4d6Robert Mustacchi * Device state, switch information, and resources.
9d26e4fc021e249c93c2861629cc665e4f5bd4d6Robert Mustacchi * Transmit and receive information, tunables, and MAC info.
9d26e4fc021e249c93c2861629cc665e4f5bd4d6Robert Mustacchi * Interrupt state
9d26e4fc021e249c93c2861629cc665e4f5bd4d6Robert Mustacchi * Note that the use of a single boolean_t for i40e_intr_poll isn't
9d26e4fc021e249c93c2861629cc665e4f5bd4d6Robert Mustacchi * really the best design. When we have more than a single ring on the
9d26e4fc021e249c93c2861629cc665e4f5bd4d6Robert Mustacchi * device working, we'll transition to using something more
9d26e4fc021e249c93c2861629cc665e4f5bd4d6Robert Mustacchi * sophisticated.
9d26e4fc021e249c93c2861629cc665e4f5bd4d6Robert Mustacchi * DMA attributes. See i40e_transceiver.c for why we have copies of them
9d26e4fc021e249c93c2861629cc665e4f5bd4d6Robert Mustacchi * in the i40e_t.
9d26e4fc021e249c93c2861629cc665e4f5bd4d6Robert Mustacchi * The following two fields are used to protect and keep track of
9d26e4fc021e249c93c2861629cc665e4f5bd4d6Robert Mustacchi * outstanding, loaned buffers to MAC. If we have these, we can't
9d26e4fc021e249c93c2861629cc665e4f5bd4d6Robert Mustacchi * detach as we have active DMA memory outstanding.
9d26e4fc021e249c93c2861629cc665e4f5bd4d6Robert Mustacchi * PF statistics and VSI statistics.
9d26e4fc021e249c93c2861629cc665e4f5bd4d6Robert Mustacchi * Misc. stats and counters that should maybe one day be kstats.
9d26e4fc021e249c93c2861629cc665e4f5bd4d6Robert Mustacchi * The i40e_device represents a PCI device which encapsulates multiple physical
9d26e4fc021e249c93c2861629cc665e4f5bd4d6Robert Mustacchi * functions which are represented as an i40e_t. This is used to track the use
9d26e4fc021e249c93c2861629cc665e4f5bd4d6Robert Mustacchi * of pooled resources throughout all of the various devices.
9d26e4fc021e249c93c2861629cc665e4f5bd4d6Robert Mustacchi uint_t id_nfuncs; /* Total number of functions */
9d26e4fc021e249c93c2861629cc665e4f5bd4d6Robert Mustacchi list_t id_i40e_list; /* List of i40e_t's registered */
9d26e4fc021e249c93c2861629cc665e4f5bd4d6Robert Mustacchi i40e_switch_rsrc_t *id_rsrcs; /* Switch resources for this PF */
9d26e4fc021e249c93c2861629cc665e4f5bd4d6Robert Mustacchi uint_t id_rsrcs_alloc; /* Total allocated resources */
9d26e4fc021e249c93c2861629cc665e4f5bd4d6Robert Mustacchi uint_t id_rsrcs_act; /* Actual number of resources */
9d26e4fc021e249c93c2861629cc665e4f5bd4d6Robert Mustacchi/* Values for the interrupt forcing on the NIC. */
9d26e4fc021e249c93c2861629cc665e4f5bd4d6Robert Mustacchi/* Hint that we don't want to do any polling... */
9d26e4fc021e249c93c2861629cc665e4f5bd4d6Robert Mustacchi * Logging functions.
9d26e4fc021e249c93c2861629cc665e4f5bd4d6Robert Mustacchi/*PRINTFLIKE2*/
9d26e4fc021e249c93c2861629cc665e4f5bd4d6Robert Mustacchiextern void i40e_error(i40e_t *, const char *, ...) __KPRINTFLIKE(2);
9d26e4fc021e249c93c2861629cc665e4f5bd4d6Robert Mustacchi/*PRINTFLIKE2*/
9d26e4fc021e249c93c2861629cc665e4f5bd4d6Robert Mustacchiextern void i40e_notice(i40e_t *, const char *, ...) __KPRINTFLIKE(2);
9d26e4fc021e249c93c2861629cc665e4f5bd4d6Robert Mustacchi/*PRINTFLIKE2*/
9d26e4fc021e249c93c2861629cc665e4f5bd4d6Robert Mustacchiextern void i40e_log(i40e_t *, const char *, ...) __KPRINTFLIKE(2);
9d26e4fc021e249c93c2861629cc665e4f5bd4d6Robert Mustacchi * General link handling functions.
9d26e4fc021e249c93c2861629cc665e4f5bd4d6Robert Mustacchi * FMA functions.
9d26e4fc021e249c93c2861629cc665e4f5bd4d6Robert Mustacchiextern int i40e_check_acc_handle(ddi_acc_handle_t);
9d26e4fc021e249c93c2861629cc665e4f5bd4d6Robert Mustacchiextern int i40e_check_dma_handle(ddi_dma_handle_t);
9d26e4fc021e249c93c2861629cc665e4f5bd4d6Robert Mustacchiextern void i40e_fm_ereport(i40e_t *, char *);
9d26e4fc021e249c93c2861629cc665e4f5bd4d6Robert Mustacchi * Interrupt handlers and interrupt handler setup.
9d26e4fc021e249c93c2861629cc665e4f5bd4d6Robert Mustacchiextern uint_t i40e_intr_msix(void *, void *);
9d26e4fc021e249c93c2861629cc665e4f5bd4d6Robert Mustacchiextern uint_t i40e_intr_msi(void *, void *);
9d26e4fc021e249c93c2861629cc665e4f5bd4d6Robert Mustacchiextern uint_t i40e_intr_legacy(void *, void *);
9d26e4fc021e249c93c2861629cc665e4f5bd4d6Robert Mustacchiextern void i40e_intr_io_enable_all(i40e_t *);
9d26e4fc021e249c93c2861629cc665e4f5bd4d6Robert Mustacchiextern void i40e_intr_io_disable_all(i40e_t *);
9d26e4fc021e249c93c2861629cc665e4f5bd4d6Robert Mustacchiextern void i40e_intr_io_clear_cause(i40e_t *);
9d26e4fc021e249c93c2861629cc665e4f5bd4d6Robert Mustacchiextern void i40e_intr_rx_queue_disable(i40e_t *, uint_t);
9d26e4fc021e249c93c2861629cc665e4f5bd4d6Robert Mustacchiextern void i40e_intr_rx_queue_enable(i40e_t *, uint_t);
9d26e4fc021e249c93c2861629cc665e4f5bd4d6Robert Mustacchiextern void i40e_intr_set_itr(i40e_t *, i40e_itr_index_t, uint_t);
9d26e4fc021e249c93c2861629cc665e4f5bd4d6Robert Mustacchi * Receive-side functions
9d26e4fc021e249c93c2861629cc665e4f5bd4d6Robert Mustacchiextern mblk_t *i40e_ring_rx(i40e_trqpair_t *, int);
9d26e4fc021e249c93c2861629cc665e4f5bd4d6Robert Mustacchiextern mblk_t *i40e_ring_rx_poll(void *, int);
9d26e4fc021e249c93c2861629cc665e4f5bd4d6Robert Mustacchi * Transmit-side functions
9d26e4fc021e249c93c2861629cc665e4f5bd4d6Robert Mustacchiextern void i40e_tx_recycle_ring(i40e_trqpair_t *);
9d26e4fc021e249c93c2861629cc665e4f5bd4d6Robert Mustacchiextern void i40e_tx_cleanup_ring(i40e_trqpair_t *);
9d26e4fc021e249c93c2861629cc665e4f5bd4d6Robert Mustacchi * Statistics functions.
9d26e4fc021e249c93c2861629cc665e4f5bd4d6Robert Mustacchiextern boolean_t i40e_stat_vsi_init(i40e_t *);
9d26e4fc021e249c93c2861629cc665e4f5bd4d6Robert Mustacchiextern boolean_t i40e_stats_trqpair_init(i40e_trqpair_t *);
9d26e4fc021e249c93c2861629cc665e4f5bd4d6Robert Mustacchiextern void i40e_stats_trqpair_fini(i40e_trqpair_t *);
9d26e4fc021e249c93c2861629cc665e4f5bd4d6Robert Mustacchiextern int i40e_m_stat(void *, uint_t, uint64_t *);
9d26e4fc021e249c93c2861629cc665e4f5bd4d6Robert Mustacchiextern int i40e_rx_ring_stat(mac_ring_driver_t, uint_t, uint64_t *);
9d26e4fc021e249c93c2861629cc665e4f5bd4d6Robert Mustacchiextern int i40e_tx_ring_stat(mac_ring_driver_t, uint_t, uint64_t *);
9d26e4fc021e249c93c2861629cc665e4f5bd4d6Robert Mustacchi * MAC/GLDv3 functions, and functions called by MAC/GLDv3 support code.
9d26e4fc021e249c93c2861629cc665e4f5bd4d6Robert Mustacchiextern boolean_t i40e_register_mac(i40e_t *);
9d26e4fc021e249c93c2861629cc665e4f5bd4d6Robert Mustacchiextern boolean_t i40e_start(i40e_t *, boolean_t);
9d26e4fc021e249c93c2861629cc665e4f5bd4d6Robert Mustacchi * DMA & buffer functions and attributes
9d26e4fc021e249c93c2861629cc665e4f5bd4d6Robert Mustacchiextern void i40e_init_dma_attrs(i40e_t *, boolean_t);
9d26e4fc021e249c93c2861629cc665e4f5bd4d6Robert Mustacchiextern boolean_t i40e_alloc_ring_mem(i40e_t *);
9d26e4fc021e249c93c2861629cc665e4f5bd4d6Robert Mustacchiextern void i40e_free_ring_mem(i40e_t *, boolean_t);
9d26e4fc021e249c93c2861629cc665e4f5bd4d6Robert Mustacchi#endif /* _I40E_SW_H */