3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs/*
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs * CDDL HEADER START
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs *
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs * The contents of this file are subject to the terms of the
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs * Common Development and Distribution License (the "License").
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs * You may not use this file except in compliance with the License.
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs *
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs * or http://www.opensolaris.org/os/licensing.
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs * See the License for the specific language governing permissions
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs * and limitations under the License.
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs *
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs * When distributing Covered Code, include this CDDL HEADER in each
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs * If applicable, add the following below this CDDL HEADER, with the
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs * fields enclosed by brackets "[]" replaced with your own identifying
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs * information: Portions Copyright [yyyy] [name of copyright owner]
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs *
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs * CDDL HEADER END
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs */
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs/*
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs * Copyright 2008 Sun Microsystems, Inc. All rights reserved.
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs * Use is subject to license terms.
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs */
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs#ifndef _HXGE_VMAC_HW_H
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs#define _HXGE_VMAC_HW_H
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs#pragma ident "%Z%%M% %I% %E% SMI"
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs#ifdef __cplusplus
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qsextern "C" {
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs#endif
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs#define VMAC_BASE_ADDR 0X00100000
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs#define VMAC_RST (VMAC_BASE_ADDR + 0x0)
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs#define VMAC_TX_CFG (VMAC_BASE_ADDR + 0x8)
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs#define VMAC_RX_CFG (VMAC_BASE_ADDR + 0x10)
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs#define VMAC_TX_STAT (VMAC_BASE_ADDR + 0x20)
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs#define VMAC_TX_MSK (VMAC_BASE_ADDR + 0x28)
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs#define VMAC_RX_STAT (VMAC_BASE_ADDR + 0x30)
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs#define VMAC_RX_MSK (VMAC_BASE_ADDR + 0x38)
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs#define VMAC_TX_STAT_MIRROR (VMAC_BASE_ADDR + 0x40)
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs#define VMAC_RX_STAT_MIRROR (VMAC_BASE_ADDR + 0x48)
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs#define VMAC_TX_FRAME_CNT (VMAC_BASE_ADDR + 0x100)
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs#define VMAC_TX_BYTE_CNT (VMAC_BASE_ADDR + 0x108)
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs#define VMAC_RX_FRAME_CNT (VMAC_BASE_ADDR + 0x120)
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs#define VMAC_RX_BYTE_CNT (VMAC_BASE_ADDR + 0x128)
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs#define VMAC_RX_DROP_FR_CNT (VMAC_BASE_ADDR + 0x130)
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs#define VMAC_RX_DROP_BYTE_CNT (VMAC_BASE_ADDR + 0x138)
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs#define VMAC_RX_CRC_CNT (VMAC_BASE_ADDR + 0x140)
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs#define VMAC_RX_PAUSE_CNT (VMAC_BASE_ADDR + 0x148)
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs#define VMAC_RX_BCAST_FR_CNT (VMAC_BASE_ADDR + 0x150)
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs#define VMAC_RX_MCAST_FR_CNT (VMAC_BASE_ADDR + 0x158)
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs/*
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs * Register: VmacRst
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs * VMAC Software Reset Command
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs * Description:
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs * Fields:
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs * Write a '1' to reset Rx VMAC; auto clears. This brings rx vmac
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs * to power on reset state.
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs * Write a '1' to reset Tx VMAC; auto clears. This brings tx vmac
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs * to power on reset state.
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs */
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qstypedef union {
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs uint64_t value;
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs struct {
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs#if defined(_BIG_ENDIAN)
fe930412c257f961ae67039de3b164b83717976aqs uint32_t rsrvd:32;
fe930412c257f961ae67039de3b164b83717976aqs uint32_t rsrvd_l:23;
fe930412c257f961ae67039de3b164b83717976aqs uint32_t rx_reset:1;
fe930412c257f961ae67039de3b164b83717976aqs uint32_t rsrvd1:7;
fe930412c257f961ae67039de3b164b83717976aqs uint32_t tx_reset:1;
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs#else
fe930412c257f961ae67039de3b164b83717976aqs uint32_t tx_reset:1;
fe930412c257f961ae67039de3b164b83717976aqs uint32_t rsrvd1:7;
fe930412c257f961ae67039de3b164b83717976aqs uint32_t rx_reset:1;
fe930412c257f961ae67039de3b164b83717976aqs uint32_t rsrvd_l:23;
fe930412c257f961ae67039de3b164b83717976aqs uint32_t rsrvd:32;
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs#endif
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs } bits;
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs} vmac_rst_t;
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs/*
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs * Register: VmacTxCfg
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs * Tx VMAC Configuration
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs * Description:
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs * Fields:
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs * Maximum length of any total transfer gathered by Tx VMAC,
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs * including packet data, header, crc, transmit header and any
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs * pad bytes. Default value of 0x2422 represents 9220 bytes of
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs * packet data, ethernet header, and crc, 14 bytes maximum pad,
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs * and 16 bytes transmit header = 9250 (0x2422).
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs * Enable padding of short packet to meet minimum frame length of
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs * 64 bytes. Software should note that if txPad functionality is
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs * used to pad runt packets to minimum length, that crcInsert
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs * functionality (below) must also be used to provide the packet
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs * with correct L2 crc.
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs * 1: Enable generation and appending of FCS to the packets. 0:
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs * Disable generation and appending of FCS to the packets.
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs * Enable Tx VMAC. Write a '1' to enable Tx VMAC; write a '0' to
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs * disable it. This bit also propagates as vmacTdcEn to the TDC
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs * block. In TDC, the vmacTdcEn bit disables the RTab state
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs * machine. Hence, the transmission from that blade would be
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs * stopped and be queued, but no packets would be dropped. Thus,
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs * the VMAC can only be enabled/disabled at packet boundary. The
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs * VMAC will not send out portion of a packet. The currently
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs * processed packet will continue to be sent out when Tx VMAC is
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs * disabled.
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs */
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qstypedef union {
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs uint64_t value;
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs struct {
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs#if defined(_BIG_ENDIAN)
fe930412c257f961ae67039de3b164b83717976aqs uint32_t rsrvd:32;
fe930412c257f961ae67039de3b164b83717976aqs uint32_t tx_max_frame_length:14;
fe930412c257f961ae67039de3b164b83717976aqs uint32_t rsrvd1:15;
fe930412c257f961ae67039de3b164b83717976aqs uint32_t tx_pad:1;
fe930412c257f961ae67039de3b164b83717976aqs uint32_t crc_insert:1;
fe930412c257f961ae67039de3b164b83717976aqs uint32_t tx_en:1;
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs#else
fe930412c257f961ae67039de3b164b83717976aqs uint32_t tx_en:1;
fe930412c257f961ae67039de3b164b83717976aqs uint32_t crc_insert:1;
fe930412c257f961ae67039de3b164b83717976aqs uint32_t tx_pad:1;
fe930412c257f961ae67039de3b164b83717976aqs uint32_t rsrvd1:15;
fe930412c257f961ae67039de3b164b83717976aqs uint32_t tx_max_frame_length:14;
fe930412c257f961ae67039de3b164b83717976aqs uint32_t rsrvd:32;
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs#endif
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs } bits;
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs} vmac_tx_cfg_t;
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs/*
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs * Register: VmacRxCfg
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs * Rx VMAC Configuration
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs * Description: MAC address and length in Type/Length field are
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs * checked in PFC.
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs * Fields:
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs * Maximum length of a frame accepted by Rx/Tx VMAC. Only packets
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs * with length between 64 bytes and maxFrameLength will be
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs * accepted by Rx/Tx VMAC. This length indicates just the packet
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs * length excluding the packet header, crc, and any pad bytes.
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs * Maximum value is 9K (9*1024)
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs * enable packets from the same blade to loopback
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs * Enable acceptance of all Unicast packets for L2 destination
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs * address, ie, allow all Unicast packets to pass the L2
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs * filtering.
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs * Enable acceptance of all multi-cast packets, ie, allow all
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs * multi-cast packets to pass the L2 filtering.
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs * Enable the passing through of flow control frames.
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs * Enable the stripping of FCS field in the packets.
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs * Disable of FCS checking. When enable, packets with incorrect
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs * FCS value are dropped by Rx VMAC.
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs * Enable rx VMAC. Write a '1' to enable rx VMAC; write a '0' to
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs * disable it. The VMAC will begin to accept packet at the
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs * detection of the SOP (start of packet). When disable, the
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs * currently processed packet will continue to be accepted.
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs */
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qstypedef union {
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs uint64_t value;
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs struct {
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs#if defined(_BIG_ENDIAN)
fe930412c257f961ae67039de3b164b83717976aqs uint32_t rsrvd:32;
fe930412c257f961ae67039de3b164b83717976aqs uint32_t rx_max_frame_length:14;
fe930412c257f961ae67039de3b164b83717976aqs uint32_t reserved:11;
fe930412c257f961ae67039de3b164b83717976aqs uint32_t loopback:1;
fe930412c257f961ae67039de3b164b83717976aqs uint32_t promiscuous_mode:1;
fe930412c257f961ae67039de3b164b83717976aqs uint32_t promiscuous_group:1;
fe930412c257f961ae67039de3b164b83717976aqs uint32_t pass_flow_ctrl_fr:1;
fe930412c257f961ae67039de3b164b83717976aqs uint32_t strip_crc:1;
fe930412c257f961ae67039de3b164b83717976aqs uint32_t crc_check_disable:1;
fe930412c257f961ae67039de3b164b83717976aqs uint32_t rx_en:1;
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs#else
fe930412c257f961ae67039de3b164b83717976aqs uint32_t rx_en:1;
fe930412c257f961ae67039de3b164b83717976aqs uint32_t crc_check_disable:1;
fe930412c257f961ae67039de3b164b83717976aqs uint32_t strip_crc:1;
fe930412c257f961ae67039de3b164b83717976aqs uint32_t pass_flow_ctrl_fr:1;
fe930412c257f961ae67039de3b164b83717976aqs uint32_t promiscuous_group:1;
fe930412c257f961ae67039de3b164b83717976aqs uint32_t promiscuous_mode:1;
fe930412c257f961ae67039de3b164b83717976aqs uint32_t loopback:1;
fe930412c257f961ae67039de3b164b83717976aqs uint32_t reserved:11;
fe930412c257f961ae67039de3b164b83717976aqs uint32_t rx_max_frame_length:14;
fe930412c257f961ae67039de3b164b83717976aqs uint32_t rsrvd:32;
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs#endif
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs } bits;
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs} vmac_rx_cfg_t;
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs/*
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs * Register: VmacTxStat
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs * Tx VMAC Status Register
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs * Description: A new interrupt will be generated only if Tx VMAC is
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs * enabled by vmacTxCfg::txEn=1. Disabling Tx VMAC does not affect
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs * currently-existing Ldf state. Writing this register affects
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs * vmacTxStatMirror register bits also the same way.
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs * Fields:
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs * Indicates that counter of byte transmitted has exceeded the
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs * max value.
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs * Indicates that counter of frame transmitted has exceeded the
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs * max value.
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs * A frame has been successfully transmitted.
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs */
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qstypedef union {
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs uint64_t value;
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs struct {
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs#if defined(_BIG_ENDIAN)
fe930412c257f961ae67039de3b164b83717976aqs uint32_t rsrvd:32;
fe930412c257f961ae67039de3b164b83717976aqs uint32_t rsrvd_l:29;
fe930412c257f961ae67039de3b164b83717976aqs uint32_t tx_byte_cnt_overflow:1;
fe930412c257f961ae67039de3b164b83717976aqs uint32_t tx_frame_cnt_overflow:1;
fe930412c257f961ae67039de3b164b83717976aqs uint32_t frame_tx:1;
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs#else
fe930412c257f961ae67039de3b164b83717976aqs uint32_t frame_tx:1;
fe930412c257f961ae67039de3b164b83717976aqs uint32_t tx_frame_cnt_overflow:1;
fe930412c257f961ae67039de3b164b83717976aqs uint32_t tx_byte_cnt_overflow:1;
fe930412c257f961ae67039de3b164b83717976aqs uint32_t rsrvd_l:29;
fe930412c257f961ae67039de3b164b83717976aqs uint32_t rsrvd:32;
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs#endif
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs } bits;
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs} vmac_tx_stat_t;
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs/*
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs * Register: VmacTxMsk
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs * Tx VMAC Status Mask
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs * Description: masking vmacTxStat from interrupt.
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs * Fields:
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs * 1: mask interrupt due to overflow of counter of byte
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs * transmitted
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs * 1: mask interrupt due to overflow of counter of frame
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs * transmitted
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs * 1: mask interrupt due to successful transmition of frame.
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs */
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qstypedef union {
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs uint64_t value;
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs struct {
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs#if defined(_BIG_ENDIAN)
fe930412c257f961ae67039de3b164b83717976aqs uint32_t rsrvd:32;
fe930412c257f961ae67039de3b164b83717976aqs uint32_t rsrvd_l:29;
fe930412c257f961ae67039de3b164b83717976aqs uint32_t tx_byte_cnt_overflow_msk:1;
fe930412c257f961ae67039de3b164b83717976aqs uint32_t tx_frame_cnt_overflow_msk:1;
fe930412c257f961ae67039de3b164b83717976aqs uint32_t frame_tx_msk:1;
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs#else
fe930412c257f961ae67039de3b164b83717976aqs uint32_t frame_tx_msk:1;
fe930412c257f961ae67039de3b164b83717976aqs uint32_t tx_frame_cnt_overflow_msk:1;
fe930412c257f961ae67039de3b164b83717976aqs uint32_t tx_byte_cnt_overflow_msk:1;
fe930412c257f961ae67039de3b164b83717976aqs uint32_t rsrvd_l:29;
fe930412c257f961ae67039de3b164b83717976aqs uint32_t rsrvd:32;
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs#endif
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs } bits;
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs} vmac_tx_msk_t;
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs/*
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs * Register: VmacRxStat
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs * Rx VMAC Status Register
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs * Description: Overflow indicators are read-only registers; Read off
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs * the counters to clear. A new interrupt will be generated only if
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs * Rx VMAC is enabled by vmacRxCfg::rxEn=1. Disabling Rx VMAC does
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs * not affect currently-existing Ldf state. Writing this register
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs * affects vmacRxStatMirror register bits also the same way.
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs * Fields:
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs * Indicates that the counter for broadcast packets has exceeded
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs * the max value.
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs * Indicates that the counter for multicast packets has exceeded
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs * the max value.
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs * Indicates that the counter for pause packets has exceeded the
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs * max value.
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs * Indicates that the counter for packets with mismatched FCS has
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs * exceeded the max value.
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs * Indicates that counter of dropped byte has exceeded the max
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs * value.
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs * Indicates that counter of dropped frame has exceeded the max
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs * value.
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs * Indicates that counter of byte received has exceeded the max
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs * value.
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs * Indicates that counter of frame received has exceeded the max
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs * value.
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs * A valid frame has been successfully received.
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs */
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qstypedef union {
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs uint64_t value;
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs struct {
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs#if defined(_BIG_ENDIAN)
fe930412c257f961ae67039de3b164b83717976aqs uint32_t rsrvd:32;
fe930412c257f961ae67039de3b164b83717976aqs uint32_t rsrvd_l:23;
fe930412c257f961ae67039de3b164b83717976aqs uint32_t bcast_cnt_overflow:1;
fe930412c257f961ae67039de3b164b83717976aqs uint32_t mcast_cnt_overflow:1;
fe930412c257f961ae67039de3b164b83717976aqs uint32_t pause_cnt_overflow:1;
fe930412c257f961ae67039de3b164b83717976aqs uint32_t crc_err_cnt_overflow:1;
fe930412c257f961ae67039de3b164b83717976aqs uint32_t rx_drop_byte_cnt_overflow:1;
fe930412c257f961ae67039de3b164b83717976aqs uint32_t rx_drop_frame_cnt_overflow:1;
fe930412c257f961ae67039de3b164b83717976aqs uint32_t rx_byte_cnt_overflow:1;
fe930412c257f961ae67039de3b164b83717976aqs uint32_t rx_frame_cnt_overflow:1;
fe930412c257f961ae67039de3b164b83717976aqs uint32_t frame_rx:1;
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs#else
fe930412c257f961ae67039de3b164b83717976aqs uint32_t frame_rx:1;
fe930412c257f961ae67039de3b164b83717976aqs uint32_t rx_frame_cnt_overflow:1;
fe930412c257f961ae67039de3b164b83717976aqs uint32_t rx_byte_cnt_overflow:1;
fe930412c257f961ae67039de3b164b83717976aqs uint32_t rx_drop_frame_cnt_overflow:1;
fe930412c257f961ae67039de3b164b83717976aqs uint32_t rx_drop_byte_cnt_overflow:1;
fe930412c257f961ae67039de3b164b83717976aqs uint32_t crc_err_cnt_overflow:1;
fe930412c257f961ae67039de3b164b83717976aqs uint32_t pause_cnt_overflow:1;
fe930412c257f961ae67039de3b164b83717976aqs uint32_t mcast_cnt_overflow:1;
fe930412c257f961ae67039de3b164b83717976aqs uint32_t bcast_cnt_overflow:1;
fe930412c257f961ae67039de3b164b83717976aqs uint32_t rsrvd_l:23;
fe930412c257f961ae67039de3b164b83717976aqs uint32_t rsrvd:32;
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs#endif
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs } bits;
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs} vmac_rx_stat_t;
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs/*
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs * Register: VmacRxMsk
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs * Rx VMAC Status Mask
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs * Description:
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs * Fields:
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs * 1: mask interrupt due to overflow of the counter for broadcast
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs * packets
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs * 1: mask interrupt due to overflow of the counter for multicast
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs * packets
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs * 1: mask interrupt due to overflow of the counter for pause
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs * packets
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs * 1: mask interrupt due to overflow of the counter for packets
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs * with mismatched FCS the max value.
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs * 1: mask interrupt due to overflow of dropped byte counter
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs * 1: mask interrupt due to overflow of dropped frame counter
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs * 1: mask interrupt due to overflow of received byte counter
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs * 1: mask interrupt due to overflow of received frame counter
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs * 1: mask interrupt due to a valid frame has been successfully
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs * received.
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs */
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qstypedef union {
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs uint64_t value;
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs struct {
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs#if defined(_BIG_ENDIAN)
fe930412c257f961ae67039de3b164b83717976aqs uint32_t rsrvd:32;
fe930412c257f961ae67039de3b164b83717976aqs uint32_t rsrvd_l:23;
fe930412c257f961ae67039de3b164b83717976aqs uint32_t bcast_cnt_overflow_msk:1;
fe930412c257f961ae67039de3b164b83717976aqs uint32_t mcast_cnt_overflow_msk:1;
fe930412c257f961ae67039de3b164b83717976aqs uint32_t pause_cnt_overflow_msk:1;
fe930412c257f961ae67039de3b164b83717976aqs uint32_t crc_err_cnt_overflow_msk:1;
fe930412c257f961ae67039de3b164b83717976aqs uint32_t rx_drop_byte_cnt_overflow_msk:1;
fe930412c257f961ae67039de3b164b83717976aqs uint32_t rx_drop_frame_cnt_overflow_msk:1;
fe930412c257f961ae67039de3b164b83717976aqs uint32_t rx_byte_cnt_overflow_msk:1;
fe930412c257f961ae67039de3b164b83717976aqs uint32_t rx_frame_cnt_overflow_msk:1;
fe930412c257f961ae67039de3b164b83717976aqs uint32_t frame_rx_msk:1;
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs#else
fe930412c257f961ae67039de3b164b83717976aqs uint32_t frame_rx_msk:1;
fe930412c257f961ae67039de3b164b83717976aqs uint32_t rx_frame_cnt_overflow_msk:1;
fe930412c257f961ae67039de3b164b83717976aqs uint32_t rx_byte_cnt_overflow_msk:1;
fe930412c257f961ae67039de3b164b83717976aqs uint32_t rx_drop_frame_cnt_overflow_msk:1;
fe930412c257f961ae67039de3b164b83717976aqs uint32_t rx_drop_byte_cnt_overflow_msk:1;
fe930412c257f961ae67039de3b164b83717976aqs uint32_t crc_err_cnt_overflow_msk:1;
fe930412c257f961ae67039de3b164b83717976aqs uint32_t pause_cnt_overflow_msk:1;
fe930412c257f961ae67039de3b164b83717976aqs uint32_t mcast_cnt_overflow_msk:1;
fe930412c257f961ae67039de3b164b83717976aqs uint32_t bcast_cnt_overflow_msk:1;
fe930412c257f961ae67039de3b164b83717976aqs uint32_t rsrvd_l:23;
fe930412c257f961ae67039de3b164b83717976aqs uint32_t rsrvd:32;
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs#endif
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs } bits;
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs} vmac_rx_msk_t;
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs/*
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs * Register: VmacTxStatMirror
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs * Tx VMAC Status Mirror Register
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs * Description: Write a 1 to this register to force the corresponding
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs * interrupt. Reading this register returns the current Tx interrupt
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs * status which would be the same as reading the vmacTxStat register.
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs * The bits are cleared by writing 1 to the corresponding register
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs * bit in the vmacTxStat register. ie, bit 0 of this register is
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs * cleared by writing 1 to bit 0 in the vmacTxStat register.
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs *
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs * Fields:
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs * 1 : Force tx byte counter overflow interrupt generation
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs * 1 : Force tx frame counter overflow interrupt generation
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs * 1 : Force frame transmitted interrupt generation
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs */
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qstypedef union {
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs uint64_t value;
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs struct {
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs#if defined(_BIG_ENDIAN)
fe930412c257f961ae67039de3b164b83717976aqs uint32_t rsrvd:32;
fe930412c257f961ae67039de3b164b83717976aqs uint32_t rsrvd_l:29;
fe930412c257f961ae67039de3b164b83717976aqs uint32_t force_tx_byte_cnt_overflow:1;
fe930412c257f961ae67039de3b164b83717976aqs uint32_t force_tx_frame_cnt_overflow:1;
fe930412c257f961ae67039de3b164b83717976aqs uint32_t force_frame_tx:1;
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs#else
fe930412c257f961ae67039de3b164b83717976aqs uint32_t force_frame_tx:1;
fe930412c257f961ae67039de3b164b83717976aqs uint32_t force_tx_frame_cnt_overflow:1;
fe930412c257f961ae67039de3b164b83717976aqs uint32_t force_tx_byte_cnt_overflow:1;
fe930412c257f961ae67039de3b164b83717976aqs uint32_t rsrvd_l:29;
fe930412c257f961ae67039de3b164b83717976aqs uint32_t rsrvd:32;
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs#endif
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs } bits;
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs} vmac_tx_stat_mirror_t;
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs/*
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs * Register: VmacRxStatMirror
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs * Rx VMAC Status Mirror Register
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs * Description: Write a 1 to this register to force the corresponding
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs * interrupt. Reading this register returns the current Rx interrupt
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs * status which would be the same as reading the vmacRxStat register.
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs * The bits are cleared by writing 1 to the corresponding register
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs * bit in the vmacRxStat register. ie, bit 0 of this register is
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs * cleared by writing 1 to bit 0 in the vmacRxStat register.
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs * Fields:
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs * 1 : Force broadcast frame counter overflow interrupt
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs * generation
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs * 1 : Force multicast frame counter overflow interrupt
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs * generation
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs * 1 : Force pause frame counter overflow interrupt generation
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs * 1 : Force crc error counter overflow interrupt generation
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs * 1 : Force dropped frames byte counter overflow interrupt
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs * generation
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs * 1 : Force dropped frame counter overflow interrupt generation
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs * 1 : Force rx byte counter overflow interrupt generation
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs * 1 : Force rx frame counter overflow interrupt generation
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs * 1 : Force frame received interrupt generation
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs */
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qstypedef union {
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs uint64_t value;
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs struct {
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs#if defined(_BIG_ENDIAN)
fe930412c257f961ae67039de3b164b83717976aqs uint32_t rsrvd:32;
fe930412c257f961ae67039de3b164b83717976aqs uint32_t rsrvd_l:23;
fe930412c257f961ae67039de3b164b83717976aqs uint32_t force_bcast_cnt_overflow:1;
fe930412c257f961ae67039de3b164b83717976aqs uint32_t force_mcast_cnt_overflow:1;
fe930412c257f961ae67039de3b164b83717976aqs uint32_t force_pause_cnt_overflow:1;
fe930412c257f961ae67039de3b164b83717976aqs uint32_t force_crc_err_cnt_overflow:1;
fe930412c257f961ae67039de3b164b83717976aqs uint32_t force_rx_drop_byte_cnt_overflow:1;
fe930412c257f961ae67039de3b164b83717976aqs uint32_t force_rx_drop_frame_cnt_overflow:1;
fe930412c257f961ae67039de3b164b83717976aqs uint32_t force_rx_byte_cnt_overflow:1;
fe930412c257f961ae67039de3b164b83717976aqs uint32_t force_rx_frame_cnt_overflow:1;
fe930412c257f961ae67039de3b164b83717976aqs uint32_t force_frame_rx:1;
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs#else
fe930412c257f961ae67039de3b164b83717976aqs uint32_t force_frame_rx:1;
fe930412c257f961ae67039de3b164b83717976aqs uint32_t force_rx_frame_cnt_overflow:1;
fe930412c257f961ae67039de3b164b83717976aqs uint32_t force_rx_byte_cnt_overflow:1;
fe930412c257f961ae67039de3b164b83717976aqs uint32_t force_rx_drop_frame_cnt_overflow:1;
fe930412c257f961ae67039de3b164b83717976aqs uint32_t force_rx_drop_byte_cnt_overflow:1;
fe930412c257f961ae67039de3b164b83717976aqs uint32_t force_crc_err_cnt_overflow:1;
fe930412c257f961ae67039de3b164b83717976aqs uint32_t force_pause_cnt_overflow:1;
fe930412c257f961ae67039de3b164b83717976aqs uint32_t force_mcast_cnt_overflow:1;
fe930412c257f961ae67039de3b164b83717976aqs uint32_t force_bcast_cnt_overflow:1;
fe930412c257f961ae67039de3b164b83717976aqs uint32_t rsrvd_l:23;
fe930412c257f961ae67039de3b164b83717976aqs uint32_t rsrvd:32;
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs#endif
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs } bits;
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs} vmac_rx_stat_mirror_t;
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs/*
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs * Register: VmacTxFrameCnt
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs * VMAC transmitted frame counter
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs * Description:
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs * Fields:
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs * Indicates the number of frames transmitted by Tx VMAC. The
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs * counter will saturate at max value. The counter is stalled
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs * when Tx VMAC is disabled by vmacTxCfg::txEn=0
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs */
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qstypedef union {
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs uint64_t value;
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs struct {
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs#if defined(_BIG_ENDIAN)
fe930412c257f961ae67039de3b164b83717976aqs uint32_t rsrvd:32;
fe930412c257f961ae67039de3b164b83717976aqs uint32_t tx_frame_cnt:32;
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs#else
fe930412c257f961ae67039de3b164b83717976aqs uint32_t tx_frame_cnt:32;
fe930412c257f961ae67039de3b164b83717976aqs uint32_t rsrvd:32;
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs#endif
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs } bits;
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs} vmac_tx_frame_cnt_t;
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs/*
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs * Register: VmacTxByteCnt
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs * VMAC transmitted byte counter
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs * Description:
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs * Fields:
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs * Indicates the number of byte (octet) of data transmitted by Tx
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs * VMAC. This counter counts all the bytes of the incoming data
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs * including packet header, packet data, crc, and pad bytes. The
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs * counter will saturate at max value. The counter is stalled
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs * when Tx VMAC is disabled by vmacTxCfg::txEn=0
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs */
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qstypedef union {
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs uint64_t value;
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs struct {
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs#if defined(_BIG_ENDIAN)
fe930412c257f961ae67039de3b164b83717976aqs uint32_t rsrvd:32;
fe930412c257f961ae67039de3b164b83717976aqs uint32_t tx_byte_cnt:32;
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs#else
fe930412c257f961ae67039de3b164b83717976aqs uint32_t tx_byte_cnt:32;
fe930412c257f961ae67039de3b164b83717976aqs uint32_t rsrvd:32;
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs#endif
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs } bits;
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs} vmac_tx_byte_cnt_t;
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs/*
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs * Register: VmacRxFrameCnt
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs * VMAC received frame counter
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs * Description:
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs * Fields:
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs * Indicates the number of frame received by Rx VMAC. The counter
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs * will saturate at max value. The counter is stalled when Rx
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs * VMAC is disabled by vmacRxCfg::rxEn=0.
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs */
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qstypedef union {
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs uint64_t value;
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs struct {
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs#if defined(_BIG_ENDIAN)
fe930412c257f961ae67039de3b164b83717976aqs uint32_t rsrvd:32;
fe930412c257f961ae67039de3b164b83717976aqs uint32_t rx_frame_cnt:32;
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs#else
fe930412c257f961ae67039de3b164b83717976aqs uint32_t rx_frame_cnt:32;
fe930412c257f961ae67039de3b164b83717976aqs uint32_t rsrvd:32;
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs#endif
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs } bits;
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs} vmac_rx_frame_cnt_t;
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs/*
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs * Register: VmacRxByteCnt
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs * VMAC received byte counter
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs * Description:
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs * Fields:
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs * Indicates the number of bytes (octet) of data received by Rx
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs * VMAC including any error frames. The counter will saturate at
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs * max value. The counter is stalled when Rx VMAC is disabled by
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs * vmacRxCfg::rxEn=0.
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs */
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qstypedef union {
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs uint64_t value;
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs struct {
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs#if defined(_BIG_ENDIAN)
fe930412c257f961ae67039de3b164b83717976aqs uint32_t rsrvd:32;
fe930412c257f961ae67039de3b164b83717976aqs uint32_t rx_byte_cnt:32;
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs#else
fe930412c257f961ae67039de3b164b83717976aqs uint32_t rx_byte_cnt:32;
fe930412c257f961ae67039de3b164b83717976aqs uint32_t rsrvd:32;
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs#endif
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs } bits;
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs} vmac_rx_byte_cnt_t;
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs/*
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs * Register: VmacRxDropFrCnt
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs * VMAC dropped frame counter
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs * Description:
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs * Fields:
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs * Indicates the number of frame dropped by Rx VMAC. The counter
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs * will This counter increments for every frame dropped for the
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs * following: - crc mismatch & crc check is enabled - failed the
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs * L2 address match & Vmac is not in promiscuous mode - pause
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs * packet & Vmac is not programmed to pass these frames The
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs * counter will saturate at max value. The counter is stalled
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs * when Rx VMAC is disabled by vmacRxCfg::rxEn=0.
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs */
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qstypedef union {
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs uint64_t value;
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs struct {
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs#if defined(_BIG_ENDIAN)
fe930412c257f961ae67039de3b164b83717976aqs uint32_t rsrvd:32;
fe930412c257f961ae67039de3b164b83717976aqs uint32_t rx_drop_frame_cnt:32;
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs#else
fe930412c257f961ae67039de3b164b83717976aqs uint32_t rx_drop_frame_cnt:32;
fe930412c257f961ae67039de3b164b83717976aqs uint32_t rsrvd:32;
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs#endif
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs } bits;
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs} vmac_rx_drop_fr_cnt_t;
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs/*
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs * Register: VmacRxDropByteCnt
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs * VMAC dropped byte counter
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs * Description:
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs * Fields:
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs * Indicates the number of byte of data dropped by Rx VMAC.
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs * Frames are dropped for one of the follg conditions : - crc
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs * mismatch & crc check is enabled - failed the L2 address match
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs * & Vmac is not in promiscuous mode - pause packet & Vmac is not
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs * programmed to pass these frames The counter will saturate at
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs * max value. The counter is stalled when Rx VMAC is disabled by
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs * vmacRxCfg::rxEn=0.
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs */
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qstypedef union {
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs uint64_t value;
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs struct {
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs#if defined(_BIG_ENDIAN)
fe930412c257f961ae67039de3b164b83717976aqs uint32_t rsrvd:32;
fe930412c257f961ae67039de3b164b83717976aqs uint32_t rx_drop_byte_cnt:32;
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs#else
fe930412c257f961ae67039de3b164b83717976aqs uint32_t rx_drop_byte_cnt:32;
fe930412c257f961ae67039de3b164b83717976aqs uint32_t rsrvd:32;
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs#endif
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs } bits;
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs} vmac_rx_drop_byte_cnt_t;
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs/*
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs * Register: VmacRxCrcCnt
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs * VMAC received CRC error frame counter
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs * Description:
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs * Fields:
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs * Indicates the number of frames with invalid CRC. When NMAC
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs * truncates a packet, it asserts crcError indication to VMAC
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs * which then counts it towards CRC error. Thus the VMAC crc
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs * error counter reflects the CRC mismatches on all the packets
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs * going out of RxMAC while the NMAC crc error counter reflects
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs * the CRC mismatches on all the packets coming into RxMAC. The
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs * counter will saturate at max value The counter is stalled when
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs * Rx VMAC is disabled by vmacRxCfg::rxEn=0.
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs */
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qstypedef union {
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs uint64_t value;
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs struct {
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs#if defined(_BIG_ENDIAN)
fe930412c257f961ae67039de3b164b83717976aqs uint32_t rsrvd:32;
fe930412c257f961ae67039de3b164b83717976aqs uint32_t rx_crc_cnt:32;
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs#else
fe930412c257f961ae67039de3b164b83717976aqs uint32_t rx_crc_cnt:32;
fe930412c257f961ae67039de3b164b83717976aqs uint32_t rsrvd:32;
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs#endif
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs } bits;
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs} vmac_rx_crc_cnt_t;
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs/*
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs * Register: VmacRxPauseCnt
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs * VMAC received pause frame counter
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs * Description:
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs * Fields:
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs * Count the number of pause frames received by Rx VMAC. The
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs * counter is stalled when Rx VMAC is disabled by
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs * vmacRxCfg::rxEn=0.
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs */
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qstypedef union {
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs uint64_t value;
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs struct {
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs#if defined(_BIG_ENDIAN)
fe930412c257f961ae67039de3b164b83717976aqs uint32_t rsrvd:32;
fe930412c257f961ae67039de3b164b83717976aqs uint32_t rx_pause_cnt:32;
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs#else
fe930412c257f961ae67039de3b164b83717976aqs uint32_t rx_pause_cnt:32;
fe930412c257f961ae67039de3b164b83717976aqs uint32_t rsrvd:32;
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs#endif
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs } bits;
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs} vmac_rx_pause_cnt_t;
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs/*
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs * Register: VmacRxBcastFrCnt
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs * VMAC received broadcast frame counter
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs * Description:
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs * Fields:
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs * Indicates the number of broadcast frames received The counter
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs * is stalled when Rx VMAC is disabled by vmacRxCfg::rxEn=0.
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs */
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qstypedef union {
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs uint64_t value;
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs struct {
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs#if defined(_BIG_ENDIAN)
fe930412c257f961ae67039de3b164b83717976aqs uint32_t rsrvd:32;
fe930412c257f961ae67039de3b164b83717976aqs uint32_t rx_bcast_fr_cnt:32;
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs#else
fe930412c257f961ae67039de3b164b83717976aqs uint32_t rx_bcast_fr_cnt:32;
fe930412c257f961ae67039de3b164b83717976aqs uint32_t rsrvd:32;
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs#endif
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs } bits;
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs} vmac_rx_bcast_fr_cnt_t;
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs/*
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs * Register: VmacRxMcastFrCnt
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs * VMAC received multicast frame counter
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs * Description:
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs * Fields:
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs * Indicates the number of multicast frames received The counter
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs * is stalled when Rx VMAC is disabled by vmacRxCfg::rxEn=0.
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs */
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qstypedef union {
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs uint64_t value;
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs struct {
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs#if defined(_BIG_ENDIAN)
fe930412c257f961ae67039de3b164b83717976aqs uint32_t rsrvd:32;
fe930412c257f961ae67039de3b164b83717976aqs uint32_t rx_mcast_fr_cnt:32;
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs#else
fe930412c257f961ae67039de3b164b83717976aqs uint32_t rx_mcast_fr_cnt:32;
fe930412c257f961ae67039de3b164b83717976aqs uint32_t rsrvd:32;
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs#endif
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs } bits;
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs} vmac_rx_mcast_fr_cnt_t;
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs#ifdef __cplusplus
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs}
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs#endif
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs#endif /* _HXGE_VMAC_HW_H */