3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs * CDDL HEADER START
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs * The contents of this file are subject to the terms of the
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs * Common Development and Distribution License (the "License").
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs * You may not use this file except in compliance with the License.
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs * See the License for the specific language governing permissions
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs * and limitations under the License.
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs * When distributing Covered Code, include this CDDL HEADER in each
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs * If applicable, add the following below this CDDL HEADER, with the
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs * fields enclosed by brackets "[]" replaced with your own identifying
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs * information: Portions Copyright [yyyy] [name of copyright owner]
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs * CDDL HEADER END
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs * Copyright 2008 Sun Microsystems, Inc. All rights reserved.
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs * Use is subject to license terms.
b97d6ca7333c353b6ca20c20c99fb1be8d32a8deMilan Jurik * Copyright 2012 Milan Jurik. All rights reserved.
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qsstatic hxge_status_t hxge_get_mac_addr_properties(p_hxge_t);
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qsstatic void hxge_ldgv_setup(p_hxge_ldg_t *ldgp, p_hxge_ldv_t *ldvp, uint8_t ldv,
b97d6ca7333c353b6ca20c20c99fb1be8d32a8deMilan Jurikextern uint_t hxge_syserr_intr(caddr_t, caddr_t);
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs * Entry point to populate configuration parameters into the master hxge
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs * data structure and to update the NDD parameter list.
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs HXGE_DEBUG_MSG((hxgep, VPD_CTL, " ==> hxge_get_config_properties"));
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs " hxge_get_config_properties: common hardware not set"));
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs " hxge_get_config_properties: mac addr properties failed"));
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs " ==> hxge_get_config_properties: Hydra"));
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs HXGE_DEBUG_MSG((hxgep, VPD_CTL, " <== hxge_get_config_properties"));
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qsstatic void
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs HXGE_DEBUG_MSG((hxgep, CFG_CTL, " ==> hxge_set_hw_vlan_config"));
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs p_class_cfgp = (p_hxge_class_pt_cfg_t)&hxgep->class_config;
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs * uint32_t array, each array entry specifying a VLAN id
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs for (i = 0; i <= VLAN_ID_MAX; i++) {
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs if (ddi_prop_lookup_int_array(DDI_DEV_T_ANY, hxgep->dip, 0, prop,
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs for (i = 0; i < vlan_cnt; i++) {
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs if ((vmap->param_id) && (vmap->param_id <= VLAN_ID_MAX)) {
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs HXGE_DEBUG_MSG((hxgep, CFG_CTL, " <== hxge_set_hw_vlan_config"));
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs * Read param_vlan_ids and param_implicit_vlan_id properties from either
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs * hxge.conf or OBP. Update the soft properties. Populate these
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs * properties into the hxge data structure.
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qsstatic void
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs HXGE_DEBUG_MSG((hxgep, CFG_CTL, " ==> hxge_use_cfg_vlan_config"));
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs status = ddi_prop_lookup_int_array(DDI_DEV_T_ANY, hxgep->dip, 0, prop,
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs if (ddi_prop_lookup_int_array(DDI_DEV_T_ANY, hxgep->dip, 0, prop,
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs HXGE_DEBUG_MSG((hxgep, CFG_CTL, " <== hxge_use_cfg_vlan_config"));
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs * Read in the configuration parameters from either hxge.conf or OBP and
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs * populate the master data structure hxge.
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs * Use these parameters to update the soft properties and the ndd array.
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qsstatic void
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs HXGE_DEBUG_MSG((hxgep, CFG_CTL, " ==> hxge_use_cfg_hydra_properties"));
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs * Read in the hardware (fcode) properties and use these properties
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs * to update the ndd array.
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs HXGE_DEBUG_MSG((hxgep, CFG_CTL, " <== hxge_use_cfg_hydra_properties"));
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs * Read param_accept_jumbo, param_rxdma_intr_time, and param_rxdma_intr_pkts
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs * from either hxge.conf or OBP.
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs * Update the soft properties.
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs * Populate these properties into the hxge data structure for latter use.
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qsstatic void
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs HXGE_DEBUG_MSG((hxgep, CFG_CTL, " ==> hxge_use_cfg_dma_config"));
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs HXGE_DEBUG_MSG((hxgep, CFG_CTL, "==> hxge_use_cfg_dma_config: "
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs "p_cfgp 0x%llx max_tdcs %d hxgep->max_tdcs %d",
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs HXGE_DEBUG_MSG((hxgep, CFG_CTL, "==> hxge_use_default_dma_config: "
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs "p_cfgp 0x%llx max_rdcs %d hxgep->max_rdcs %d",
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs HXGE_DEBUG_MSG((hxgep, CFG_CTL, "==> hxge_use_cfg_dma_config: "
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs "p_cfgp 0x%016llx start_ldg %d hxgep->max_ldgs %d ",
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs * add code for individual rdc properties
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs if (ddi_prop_lookup_int_array(DDI_DEV_T_ANY, dip, 0, prop,
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs if (ddi_prop_lookup_int_array(DDI_DEV_T_ANY, dip, 0, prop,
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs if (ddi_prop_lookup_int_array(DDI_DEV_T_ANY, dip, 0, prop,
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs HXGE_DEBUG_MSG((hxgep, CFG_CTL, "<== hxge_use_cfg_dma_config"));
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qsstatic void
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qsstatic void
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs HXGE_DEBUG_MSG((hxgep, CFG_CTL, "==> hxge_set_hw_dma_config"));
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs /* Transmit DMA Channels */
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs /* Receive DMA Channels */
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs HXGE_DEBUG_MSG((hxgep, CFG_CTL, " <== hxge_set_hw_dma_config"));
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs HXGE_DEBUG_MSG((hxgep, CFG2_CTL, "==> hxge_check_rxdma_port_member"));
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs /* Receive DMA Channels */
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs HXGE_DEBUG_MSG((hxgep, CFG2_CTL, " <== hxge_check_rxdma_port_member"));
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs HXGE_DEBUG_MSG((hxgep, CFG2_CTL, "==> hxge_check_txdma_port_member"));
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs /* Receive DMA Channels */
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs HXGE_DEBUG_MSG((hxgep, CFG2_CTL, " <== hxge_check_txdma_port_member"));
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs * Read the L2 classes, L3 classes, and initial hash from either hxge.conf
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs * or OBP. Populate these properties into the hxge data structure for latter
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs * use. Note that we are not updating these soft properties.
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qsstatic void
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs HXGE_DEBUG_MSG((hxgep, CFG_CTL, " ==> hxge_set_hw_class_config"));
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs p_class_cfgp = (p_hxge_class_pt_cfg_t)&hxgep->class_config;
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs * L2 class configuration. User configurable ether types
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs 0, prop, &int_prop_val, &prop_cnt) == DDI_PROP_SUCCESS) {
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs * Use properties from either .conf or the NDD param array. Only bits
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs * 2 and 3 are significant
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs 0, prop, &int_prop_val, &prop_cnt) == DDI_PROP_SUCCESS) {
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs if (ddi_prop_lookup_int_array(DDI_DEV_T_ANY, hxgep->dip, 0, prop,
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs cfg_value = (uint32_t)param_arr[param_hash_init_value].value;
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs HXGE_DEBUG_MSG((hxgep, CFG_CTL, " <== hxge_set_hw_class_config"));
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs * Interrupts related interface functions.
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qshxge_ldgv_init(p_hxge_t hxgep, int *navail_p, int *nrequired_p)
e5d973912cb9a1626897da9ce2dca127ef476e54Qiyan Sun - Sun Microsystems - San Diego United States peu_intr_mask_t parity_err_mask;
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs "<== hxge_ldgv_init:no avail"));
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs /* each DMA channels */
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs /* vmac */
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs /* system error interrupts. */
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs /* No devices configured. */
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs HXGE_ERROR_MSG((hxgep, HXGE_ERR_CTL, "<== hxge_ldgv_init: "
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs "no logical devices or groups configured."));
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs "==> hxge_ldgv_init: maxldvs %d maxldgs %d nldvs %d",
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs for (i = 0; i < maxldgs; i++) {
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs "==> hxge_ldgv_init: maxldvs %d maxldgs %d ldg %d",
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs * Receive DMA channels.
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs * Start with RDC to configure logical devices for each group.
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs * If non-seq needs to change the following code
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs * Transmit DMA channels.
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs "==> hxge_ldgv_init: nldvs %d navail %d nrequired %d",
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs "==> hxge_ldgv_init: nldvs %d navail %d nrequired %d",
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs * System error interrupts.
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs /* Reset PEU error mask to allow PEU error interrupts */
e5d973912cb9a1626897da9ce2dca127ef476e54Qiyan Sun - Sun Microsystems - San Diego United States * Keep the msix parity error mask here and remove it
e5d973912cb9a1626897da9ce2dca127ef476e54Qiyan Sun - Sun Microsystems - San Diego United States * after ddi_intr_enable call to avoid a msix par err
e5d973912cb9a1626897da9ce2dca127ef476e54Qiyan Sun - Sun Microsystems - San Diego United States parity_err_mask.value = 0;
e5d973912cb9a1626897da9ce2dca127ef476e54Qiyan Sun - Sun Microsystems - San Diego United States parity_err_mask.bits.eic_msix_parerr_mask = 1;
e5d973912cb9a1626897da9ce2dca127ef476e54Qiyan Sun - Sun Microsystems - San Diego United States HXGE_REG_WR32(hxgep->hpi_handle, PEU_INTR_MASK, parity_err_mask.value);
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs * Unmask the system interrupt states.
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs (void) hxge_ldgv_setup(&ptr, &ldvp, ldv, endldg, nrequired_p);
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs "==> hxge_ldgv_init: nldvs %d navail %d nrequired %d",
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs HXGE_DEBUG_MSG((hxgep, INT_CTL, "==> hxge_ldgv_uninit"));
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs "<== hxge_ldgv_uninit: no logical group configured."));
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs KMEM_FREE(ldgvp->ldgp, sizeof (hxge_ldg_t) * ldgvp->maxldgs);
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs KMEM_FREE(ldgvp->ldvp, sizeof (hxge_ldv_t) * ldgvp->maxldvs);
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs HXGE_DEBUG_MSG((hxgep, INT_CTL, "<== hxge_ldgv_uninit"));
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs HXGE_DEBUG_MSG((hxgep, INT_CTL, "==> hxge_intr_ldgv_init"));
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs * Configure the logical device group numbers, state vectors
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs * and interrupt masks for each logical device.
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs * Configure logical device masks and timers.
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs HXGE_DEBUG_MSG((hxgep, INT_CTL, "<== hxge_intr_ldgv_init"));
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs HXGE_DEBUG_MSG((hxgep, INT_CTL, "==> hxge_intr_mask_mgmt"));
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs "<== hxge_intr_mask_mgmt: Null ldgvp"));
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs "<== hxge_intr_mask_mgmt: Null ldgp or ldvp"));
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs "==> hxge_intr_mask_mgmt: # of intrs %d ", ldgvp->ldg_intrs));
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs /* Initialize masks. */
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs "==> hxge_intr_mask_mgmt(Hydra): # intrs %d ", ldgvp->ldg_intrs));
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs "==> hxge_intr_mask_mgmt(Hydra): # ldv %d in group %d",
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs "==> hxge_intr_mask_mgmt: set ldv # %d "
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs "<== hxge_intr_mask_mgmt: set mask failed "
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs " rs 0x%x ldv %d mask 0x%x",
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs "==> hxge_intr_mask_mgmt: set mask OK "
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs " rs 0x%x ldv %d mask 0x%x",
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs /* Configure timer and arm bit */
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs "<== hxge_intr_mask_mgmt: set timer failed "
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs " rs 0x%x dg %d timer 0x%x",
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs "==> hxge_intr_mask_mgmt: set timer OK "
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs " rs 0x%x ldg %d timer 0x%x",
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs HXGE_DEBUG_MSG((hxgep, INT_CTL, "<== hxge_fzc_intr_mask_mgmt"));
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs "==> hxge_intr_mask_mgmt_set: Null ldgvp"));
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs "<== hxge_intr_mask_mgmt_set: Null ldgp or ldvp"));
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs /* set masks. */
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs "==> hxge_intr_mask_mgmt_set: flag %d ldg %d"
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs "==> hxge_intr_mask_mgmt_set: "
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs "==> hxge_intr_mask_mgmt_set: "
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs "ON mask off"));
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs "==> hxge_intr_mask_mgmt_set:mask on"));
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs "==> hxge_intr_mask_mgmt_set: "
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs "set mask failed rs 0x%x ldv %d mask 0x%x",
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs "==> hxge_intr_mask_mgmt_set: flag %d"
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs "set mask OK ldv %d mask 0x%x",
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs /* set the arm bit */
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs "<== hxge_intr_mask_mgmt_set: "
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs "set timer failed rs 0x%x ldg %d timer 0x%x",
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs "==> hxge_intr_mask_mgmt_set: OK (flag %d) "
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs "set timer ldg %d timer 0x%x",
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs HXGE_DEBUG_MSG((hxgep, INT_CTL, "<== hxge_intr_mask_mgmt_set"));
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs * For Big Endian systems, the mac address will be from OBP. For Little
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs * Endian (x64) systems, it will be retrieved from the card since it cannot
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs * be programmed into PXE.
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs * This function also populates the MMAC parameters.
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs HXGE_DEBUG_MSG((hxgep, DDI_CTL, "==> hxge_get_mac_addr_properties "));
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs HXGE_DEBUG_MSG((hxgep, DDI_CTL, "<== hxge_get_mac_addr_properties "));
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qsstatic void
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qshxge_ldgv_setup(p_hxge_ldg_t *ldgp, p_hxge_ldv_t *ldvp, uint8_t ldv,
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs /* Assign the group number for each device. */
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs "==> hxge_ldgv_setup: ldv %d endldg %d ldg %d, ldvp $%p",
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs "==> hxge_ldgv_setup: ldvp $%p ngrps %d",
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs HXGE_DEBUG_MSG((NULL, INT_CTL, "==> hxge_ldgv_setup(done): "
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs "ldv %d endldg %d ldg %d, ldvp $%p",
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs "ldg %d nldvs %d ldv %d ldvp $%p endldg %d ngrps %d",