hxge_txdma.c revision 1ed830817782694e7259ee818a2f8eee72233f1e
fa9e4066f08beec538e775443c5be79dd423fcabahrens * CDDL HEADER START
fa9e4066f08beec538e775443c5be79dd423fcabahrens * The contents of this file are subject to the terms of the
ea8dc4b6d2251b437950c0056bc626b311c73c27eschrock * Common Development and Distribution License (the "License").
ea8dc4b6d2251b437950c0056bc626b311c73c27eschrock * You may not use this file except in compliance with the License.
fa9e4066f08beec538e775443c5be79dd423fcabahrens * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
fa9e4066f08beec538e775443c5be79dd423fcabahrens * See the License for the specific language governing permissions
fa9e4066f08beec538e775443c5be79dd423fcabahrens * and limitations under the License.
fa9e4066f08beec538e775443c5be79dd423fcabahrens * When distributing Covered Code, include this CDDL HEADER in each
fa9e4066f08beec538e775443c5be79dd423fcabahrens * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
fa9e4066f08beec538e775443c5be79dd423fcabahrens * If applicable, add the following below this CDDL HEADER, with the
fa9e4066f08beec538e775443c5be79dd423fcabahrens * fields enclosed by brackets "[]" replaced with your own identifying
fa9e4066f08beec538e775443c5be79dd423fcabahrens * information: Portions Copyright [yyyy] [name of copyright owner]
fa9e4066f08beec538e775443c5be79dd423fcabahrens * CDDL HEADER END
06e0070d70ba2ee95f5aa2645423eb2cf1546788Mark Shellenbaum * Copyright 2009 Sun Microsystems, Inc. All rights reserved.
fa9e4066f08beec538e775443c5be79dd423fcabahrens * Use is subject to license terms.
fa9e4066f08beec538e775443c5be79dd423fcabahrensuint32_t hxge_reclaim_pending = TXDMA_RECLAIM_PENDING_DEFAULT;
fa9e4066f08beec538e775443c5be79dd423fcabahrensuint32_t hxge_tx_max_gathers = TX_MAX_GATHER_POINTERS;
fa9e4066f08beec538e775443c5be79dd423fcabahrens/* Device register access attributes for PIO. */
c717a56157ae0e6fca6a1e3689ae1edc385716a3maybee/* Device descriptor access attributes for DMA. */
fa9e4066f08beec538e775443c5be79dd423fcabahrensextern ddi_device_acc_attr_t hxge_dev_desc_dma_acc_attr;
c717a56157ae0e6fca6a1e3689ae1edc385716a3maybee/* Device buffer access attributes for DMA. */
fa9e4066f08beec538e775443c5be79dd423fcabahrensextern ddi_device_acc_attr_t hxge_dev_buf_dma_acc_attr;
c717a56157ae0e6fca6a1e3689ae1edc385716a3maybeestatic hxge_status_t hxge_map_txdma_channel(p_hxge_t hxgep, uint16_t channel,
fa9e4066f08beec538e775443c5be79dd423fcabahrens p_hxge_dma_common_t *dma_buf_p, p_tx_ring_t *tx_desc_p,
fa9e4066f08beec538e775443c5be79dd423fcabahrens uint32_t num_chunks, p_hxge_dma_common_t *dma_cntl_p,
c717a56157ae0e6fca6a1e3689ae1edc385716a3maybeestatic void hxge_unmap_txdma_channel(p_hxge_t hxgep, uint16_t channel,
c717a56157ae0e6fca6a1e3689ae1edc385716a3maybeestatic hxge_status_t hxge_map_txdma_channel_buf_ring(p_hxge_t hxgep, uint16_t,
c717a56157ae0e6fca6a1e3689ae1edc385716a3maybeestatic void hxge_unmap_txdma_channel_buf_ring(p_hxge_t hxgep,
c717a56157ae0e6fca6a1e3689ae1edc385716a3maybeestatic void hxge_map_txdma_channel_cfg_ring(p_hxge_t, uint16_t,
fa9e4066f08beec538e775443c5be79dd423fcabahrensstatic void hxge_unmap_txdma_channel_cfg_ring(p_hxge_t hxgep,
fa9e4066f08beec538e775443c5be79dd423fcabahrensstatic hxge_status_t hxge_txdma_start_channel(p_hxge_t hxgep, uint16_t channel,
c717a56157ae0e6fca6a1e3689ae1edc385716a3maybeestatic hxge_status_t hxge_txdma_stop_channel(p_hxge_t hxgep, uint16_t channel,
fa9e4066f08beec538e775443c5be79dd423fcabahrensstatic p_tx_ring_t hxge_txdma_get_ring(p_hxge_t hxgep, uint16_t channel);
fa9e4066f08beec538e775443c5be79dd423fcabahrensstatic hxge_status_t hxge_tx_err_evnts(p_hxge_t hxgep, uint_t index,
c717a56157ae0e6fca6a1e3689ae1edc385716a3maybeestatic p_tx_mbox_t hxge_txdma_get_mbox(p_hxge_t hxgep, uint16_t channel);
c717a56157ae0e6fca6a1e3689ae1edc385716a3maybeestatic hxge_status_t hxge_txdma_fatal_err_recover(p_hxge_t hxgep,
c717a56157ae0e6fca6a1e3689ae1edc385716a3maybeestatic hxge_status_t hxge_tx_port_fatal_err_recover(p_hxge_t hxgep);
c717a56157ae0e6fca6a1e3689ae1edc385716a3maybee HXGE_DEBUG_MSG((hxgep, MEM3_CTL, "==> hxge_init_txdma_channels"));
c717a56157ae0e6fca6a1e3689ae1edc385716a3maybee * Reset TDC block from PEU to cleanup any unknown configuration.
c717a56157ae0e6fca6a1e3689ae1edc385716a3maybee * This may be resulted from previous reboot.
fa9e4066f08beec538e775443c5be79dd423fcabahrens HXGE_REG_WR32(hxgep->hpi_handle, BLOCK_RESET, reset_reg.value);
c717a56157ae0e6fca6a1e3689ae1edc385716a3maybee "<== hxge_init_txdma_channels: status 0x%x", status));
fa9e4066f08beec538e775443c5be79dd423fcabahrens "<== hxge_init_txdma_channels: status 0x%x", status));
cdb0ab79ea1af7b8fc339a04d4bf7426dc77ec4emaybee HXGE_DEBUG_MSG((hxgep, MEM3_CTL, "==> hxge_uninit_txdma_channels"));
fa9e4066f08beec538e775443c5be79dd423fcabahrens HXGE_DEBUG_MSG((hxgep, MEM3_CTL, "<== hxge_uinit_txdma_channels"));
fa9e4066f08beec538e775443c5be79dd423fcabahrenshxge_setup_dma_common(p_hxge_dma_common_t dest_p, p_hxge_dma_common_t src_p,
fa9e4066f08beec538e775443c5be79dd423fcabahrenshxge_reset_txdma_channel(p_hxge_t hxgep, uint16_t channel, uint64_t reg_data)
fa9e4066f08beec538e775443c5be79dd423fcabahrens HXGE_DEBUG_MSG((hxgep, TX_CTL, " ==> hxge_reset_txdma_channel"));
fa9e4066f08beec538e775443c5be79dd423fcabahrens if ((reg_data & TDC_TDR_RST_MASK) == TDC_TDR_RST_MASK) {
fa9e4066f08beec538e775443c5be79dd423fcabahrens rs = hpi_txdma_channel_control(handle, TXDMA_RESET, channel);
c717a56157ae0e6fca6a1e3689ae1edc385716a3maybee * Reset the tail (kick) register to 0. (Hardware will not reset it. Tx
c717a56157ae0e6fca6a1e3689ae1edc385716a3maybee * overflow fatal error if tail is not set to 0 after reset!
fa9e4066f08beec538e775443c5be79dd423fcabahrens HXGE_DEBUG_MSG((hxgep, TX_CTL, " <== hxge_reset_txdma_channel"));
fa9e4066f08beec538e775443c5be79dd423fcabahrenshxge_init_txdma_channel_event_mask(p_hxge_t hxgep, uint16_t channel,
fa9e4066f08beec538e775443c5be79dd423fcabahrens "<== hxge_init_txdma_channel_event_mask"));
fa9e4066f08beec538e775443c5be79dd423fcabahrens * Mask off tx_rng_oflow since it is a false alarm. The driver
fa9e4066f08beec538e775443c5be79dd423fcabahrens * ensures not over flowing the hardware and check the hardware
ea8dc4b6d2251b437950c0056bc626b311c73c27eschrock rs = hpi_txdma_event_mask(handle, OP_SET, channel, mask_p);
cdb0ab79ea1af7b8fc339a04d4bf7426dc77ec4emaybee "==> hxge_init_txdma_channel_event_mask"));
fa9e4066f08beec538e775443c5be79dd423fcabahrens uint16_t channel, p_tx_ring_t tx_desc_p, p_tx_mbox_t mbox_p)
cdb0ab79ea1af7b8fc339a04d4bf7426dc77ec4emaybee HXGE_DEBUG_MSG((hxgep, MEM3_CTL, "==> hxge_enable_txdma_channel"));
cdb0ab79ea1af7b8fc339a04d4bf7426dc77ec4emaybee * Use configuration data composed at init time. Write to hardware the
cdb0ab79ea1af7b8fc339a04d4bf7426dc77ec4emaybee * transmit ring configurations.
fa9e4066f08beec538e775443c5be79dd423fcabahrens /* Write to hardware the mailbox */
fa9e4066f08beec538e775443c5be79dd423fcabahrens (uint64_t *)&mbox_p->tx_mbox.dma_cookie.dmac_laddress);
fa9e4066f08beec538e775443c5be79dd423fcabahrens /* Start the DMA engine. */
fa9e4066f08beec538e775443c5be79dd423fcabahrens HXGE_DEBUG_MSG((hxgep, MEM3_CTL, "<== hxge_enable_txdma_channel"));
fa9e4066f08beec538e775443c5be79dd423fcabahrenshxge_fill_tx_hdr(p_mblk_t mp, boolean_t fill_len, boolean_t l4_cksum,
fa9e4066f08beec538e775443c5be79dd423fcabahrens uint8_t hdrs_buf[sizeof (struct ether_header) + 64 + sizeof (uint32_t)];
cdb0ab79ea1af7b8fc339a04d4bf7426dc77ec4emaybee HXGE_DEBUG_MSG((NULL, TX_CTL, "==> hxge_fill_tx_hdr: mp $%p", mp));
23b1152649c9108566b32df4271af4e0af580480maybee * Caller should zero out the headers first.
fa9e4066f08beec538e775443c5be79dd423fcabahrens "==> hxge_fill_tx_hdr: pkt_len %d npads %d",
fa9e4066f08beec538e775443c5be79dd423fcabahrens hdrp->value |= (tmp << TX_PKT_HEADER_TOT_XFER_LEN_SHIFT);
cdb0ab79ea1af7b8fc339a04d4bf7426dc77ec4emaybee * mp is the original data packet (does not include the Neptune
fa9e4066f08beec538e775443c5be79dd423fcabahrens * transmit header).
fa9e4066f08beec538e775443c5be79dd423fcabahrens mblk_len = (size_t)nmp->b_wptr - (size_t)nmp->b_rptr;
fa9e4066f08beec538e775443c5be79dd423fcabahrens "==> hxge_fill_tx_hdr: mp $%p b_rptr $%p len %d",
fa9e4066f08beec538e775443c5be79dd423fcabahrens bcopy(nmp->b_rptr, &hdrs_buf[0], sizeof (struct ether_vlan_header));
fa9e4066f08beec538e775443c5be79dd423fcabahrens eth_type = ntohs(((p_ether_header_t)hdrs_buf)->ether_type);
fa9e4066f08beec538e775443c5be79dd423fcabahrens "==> : hxge_fill_tx_hdr: (value 0x%llx) ether type 0x%x",
fa9e4066f08beec538e775443c5be79dd423fcabahrens "==> hxge_tx_pkt_hdr_init: LLC value 0x%llx", hdrp->value));
fa9e4066f08beec538e775443c5be79dd423fcabahrens "==> hxge_tx_pkt_hdr_init: LLC ether type 0x%x",
fa9e4066f08beec538e775443c5be79dd423fcabahrens "==> hxge_tx_pkt_hdr_init: VLAN value 0x%llx",
d90a49d672f767313fb19463579f6fe92b3353a8maybee HXGE_DEBUG_MSG((NULL, TX_CTL, "==> hxge_fill_tx_hdr: IPv4 "
d90a49d672f767313fb19463579f6fe92b3353a8maybee " iph_len %d l3start %d eth_hdr_size %d proto 0x%x"
d90a49d672f767313fb19463579f6fe92b3353a8maybee "tmp 0x%x", iph_len, hdrp->bits.l3start, eth_hdr_size,
f82bfe17f53efa8e4aca04a764d0352539201fb5gw "==> hxge_tx_pkt_hdr_init: IP value 0x%llx", hdrp->value));
c543ec060d1359f6c8a9507242521f344a2ac3efahrens mblk_len = (size_t)nmp->b_wptr - (size_t)nmp->b_rptr;
c543ec060d1359f6c8a9507242521f344a2ac3efahrens /* byte 6 is the next header protocol */
c543ec060d1359f6c8a9507242521f344a2ac3efahrens HXGE_DEBUG_MSG((NULL, TX_CTL, "==> hxge_fill_tx_hdr: IPv6 "
c543ec060d1359f6c8a9507242521f344a2ac3efahrens " iph_len %d l3start %d eth_hdr_size %d proto 0x%x",
c543ec060d1359f6c8a9507242521f344a2ac3efahrens iph_len, hdrp->bits.l3start, eth_hdr_size, ipproto));
c543ec060d1359f6c8a9507242521f344a2ac3efahrens HXGE_DEBUG_MSG((NULL, TX_CTL, "==> hxge_tx_pkt_hdr_init: IPv6 "
ea8dc4b6d2251b437950c0056bc626b311c73c27eschrock HXGE_DEBUG_MSG((NULL, TX_CTL, "==> hxge_fill_tx_hdr: non-IP"));
fa9e4066f08beec538e775443c5be79dd423fcabahrens "==> hxge_fill_tx_hdr: TCP (cksum flag %d)", l4_cksum));
c717a56157ae0e6fca6a1e3689ae1edc385716a3maybee hdrp->value |= (tmp << TX_PKT_HEADER_PKT_TYPE_SHIFT);
c717a56157ae0e6fca6a1e3689ae1edc385716a3maybee "==> hxge_tx_pkt_hdr_init: TCP CKSUM"
b24ab6762772a3f6a89393947930c7fa61306783Jeff Bonwick "==> hxge_tx_pkt_hdr_init: TCP value 0x%llx", hdrp->value));
c717a56157ae0e6fca6a1e3689ae1edc385716a3maybee HXGE_DEBUG_MSG((NULL, TX_CTL, "==> hxge_fill_tx_hdr: UDP"));
fa9e4066f08beec538e775443c5be79dd423fcabahrens hdrp->value |= (tmp << TX_PKT_HEADER_PKT_TYPE_SHIFT);
c717a56157ae0e6fca6a1e3689ae1edc385716a3maybee "==> hxge_tx_pkt_hdr_init: UDP value 0x%llx",
c717a56157ae0e6fca6a1e3689ae1edc385716a3maybee "==> hxge_fill_tx_hdr: pkt_len %d npads %d value 0x%llx",
c717a56157ae0e6fca6a1e3689ae1edc385716a3maybee HXGE_DEBUG_MSG((NULL, TX_CTL, "<== hxge_fill_tx_hdr"));
cdb0ab79ea1af7b8fc339a04d4bf7426dc77ec4emaybee/*ARGSUSED*/
cdb0ab79ea1af7b8fc339a04d4bf7426dc77ec4emaybeehxge_tx_pkt_header_reserve(p_mblk_t mp, uint8_t *npads)
c717a56157ae0e6fca6a1e3689ae1edc385716a3maybee if ((newmp = allocb(TX_PKT_HEADER_SIZE, BPRI_MED)) == NULL) {
ea8dc4b6d2251b437950c0056bc626b311c73c27eschrock "<== hxge_tx_pkt_header_reserve: allocb failed"));
ea8dc4b6d2251b437950c0056bc626b311c73c27eschrock "==> hxge_tx_pkt_header_reserve: get new mp"));
fa9e4066f08beec538e775443c5be79dd423fcabahrens "==>hxge_tx_pkt_header_reserve: b_rptr $%p b_wptr $%p",
fa9e4066f08beec538e775443c5be79dd423fcabahrens "<== hxge_tx_pkt_header_reserve: use new mp"));
fa9e4066f08beec538e775443c5be79dd423fcabahrenshxge_tx_pkt_nmblocks(p_mblk_t mp, int *tot_xfer_len_p)
fa9e4066f08beec538e775443c5be79dd423fcabahrens "==> hxge_tx_pkt_nmblocks: mp $%p rptr $%p wptr $%p len %d",
fa9e4066f08beec538e775443c5be79dd423fcabahrens HXGE_DEBUG_MSG((NULL, TX_CTL, "==> hxge_tx_pkt_nmblocks: "
fa9e4066f08beec538e775443c5be79dd423fcabahrens "len %d pkt_len %d nmblks %d tot_xfer_len %d",
fa9e4066f08beec538e775443c5be79dd423fcabahrens if (len <= 0) {
c717a56157ae0e6fca6a1e3689ae1edc385716a3maybee "==> hxge_tx_pkt_nmblocks:"
c717a56157ae0e6fca6a1e3689ae1edc385716a3maybee HXGE_DEBUG_MSG((NULL, TX_CTL, "==> hxge_tx_pkt_nmblocks: "
148434217c040ea38dc844384f6ba68d9b325906Matthew Ahrens "len %d pkt_len %d nmblks %d tot_xfer_len %d",
148434217c040ea38dc844384f6ba68d9b325906Matthew Ahrens "==> hxge_tx_pkt_nmblocks: "
148434217c040ea38dc844384f6ba68d9b325906Matthew Ahrens "len %d (< thresh) pkt_len %d nmblks %d",
0a586cea3ceec7e5e50e7e54c745082a7a333ac2Mark Shellenbaum "==> hxge_tx_pkt_nmblocks: "
06e0070d70ba2ee95f5aa2645423eb2cf1546788Mark Shellenbaum "len %d (> thresh) pkt_len %d nmblks %d",
148434217c040ea38dc844384f6ba68d9b325906Matthew Ahrens * Hardware limits the transfer length to 4K. If len is
148434217c040ea38dc844384f6ba68d9b325906Matthew Ahrens * more than 4K, we need to break it up to at most 2
fa9e4066f08beec538e775443c5be79dd423fcabahrens * more blocks.
da03de9920a5a87150a121e9851479c6b3364d8aMark Maybee "==> hxge_tx_pkt_nmblocks: "
fa9e4066f08beec538e775443c5be79dd423fcabahrens "len %d pkt_len %d nmblks %d nsegs %d",
f676ed3419ae468da6c6831c143b0b54173e08d2ahrens return (0);
1934e92fc930c49429ad71a8ca97340f33227e78maybee * Hardware limits the transmit gather pointers to 15.
1934e92fc930c49429ad71a8ca97340f33227e78maybee if (nmp->b_cont && (nmblks + TX_GATHER_POINTERS_THRESHOLD) >
1934e92fc930c49429ad71a8ca97340f33227e78maybee "==> hxge_tx_pkt_nmblocks: pull msg - "
1934e92fc930c49429ad71a8ca97340f33227e78maybee "len %d pkt_len %d nmblks %d",
0a586cea3ceec7e5e50e7e54c745082a7a333ac2Mark Shellenbaum /* Pull all message blocks from b_cont */
0a586cea3ceec7e5e50e7e54c745082a7a333ac2Mark Shellenbaum if ((tmp = msgpullup(nmp->b_cont, -1)) == NULL) {
0a586cea3ceec7e5e50e7e54c745082a7a333ac2Mark Shellenbaum "<== hxge_tx_pkt_nmblocks: rptr $%p wptr $%p "
0a586cea3ceec7e5e50e7e54c745082a7a333ac2Mark Shellenbaum "nmblks %d len %d tot_xfer_len %d",
0a586cea3ceec7e5e50e7e54c745082a7a333ac2Mark Shellenbaum mp->b_rptr, mp->b_wptr, nmblks, MBLKL(mp), *tot_xfer_len_p));
fa9e4066f08beec538e775443c5be79dd423fcabahrenshxge_txdma_reclaim(p_hxge_t hxgep, p_tx_ring_t tx_ring_p, int nmblks)
cdb0ab79ea1af7b8fc339a04d4bf7426dc77ec4emaybee HXGE_DEBUG_MSG((hxgep, TX_CTL, "==> hxge_txdma_reclaim"));
cdb0ab79ea1af7b8fc339a04d4bf7426dc77ec4emaybee status = ((tx_ring_p->descs_pending < hxge_reclaim_pending) &&
fa9e4066f08beec538e775443c5be79dd423fcabahrens "==> hxge_txdma_reclaim: pending %d reclaim %d nmblks %d",
1934e92fc930c49429ad71a8ca97340f33227e78maybee tx_ring_p->descs_pending, hxge_reclaim_pending, nmblks));
da03de9920a5a87150a121e9851479c6b3364d8aMark Maybee tx_desc_ring_vp = (p_tx_desc_t)DMA_COMMON_VPTR(desc_area);
da03de9920a5a87150a121e9851479c6b3364d8aMark Maybee if (tx_ring_p->descs_pending > tdc_stats->tx_max_pend) {
da03de9920a5a87150a121e9851479c6b3364d8aMark Maybee tdc_stats->tx_max_pend = tx_ring_p->descs_pending;
da03de9920a5a87150a121e9851479c6b3364d8aMark Maybee * tdc_byte_cnt reg can be used to get bytes transmitted. It
da03de9920a5a87150a121e9851479c6b3364d8aMark Maybee * includes padding too in case of runt packets.
da03de9920a5a87150a121e9851479c6b3364d8aMark Maybee TXDMA_REG_READ64(handle, TDC_BYTE_CNT, tdc, &byte_cnt.value);
da03de9920a5a87150a121e9851479c6b3364d8aMark Maybee tdc_stats->obytes_with_pad += byte_cnt.bits.byte_count;
da03de9920a5a87150a121e9851479c6b3364d8aMark Maybee "==> hxge_txdma_reclaim: tdc %d tx_rd_index %d "
da03de9920a5a87150a121e9851479c6b3364d8aMark Maybee "tail_index %d tail_wrap %d tx_desc_p $%p ($%p) ",
fa9e4066f08beec538e775443c5be79dd423fcabahrens * Read the hardware maintained transmit head and wrap around
148434217c040ea38dc844384f6ba68d9b325906Matthew Ahrens TXDMA_REG_READ64(handle, TDC_TDR_HEAD, tdc, &tx_head.value);
c717a56157ae0e6fca6a1e3689ae1edc385716a3maybee "==> hxge_txdma_reclaim: "
c717a56157ae0e6fca6a1e3689ae1edc385716a3maybee "tx_rd_index %d tail %d tail_wrap %d head %d wrap %d",
c717a56157ae0e6fca6a1e3689ae1edc385716a3maybee tx_rd_index, tail_index, tail_wrap, head_index, head_wrap));
c717a56157ae0e6fca6a1e3689ae1edc385716a3maybee * For debug only. This can be used to verify the qlen and make
fa9e4066f08beec538e775443c5be79dd423fcabahrens * sure the hardware is wrapping the Tdr correctly.
return (B_TRUE);
tail_wrap)) {
return (B_FALSE);
if (status) {
return (status);
return (DDI_INTR_UNCLAIMED);
return (DDI_INTR_CLAIMED);
return (serviced);
int i, ndmas;
return (HXGE_ERROR);
return (HXGE_ERROR);
return (HXGE_ERROR);
if (!ndmas) {
return (HXGE_ERROR);
for (i = 0; i < ndmas; i++) {
if (enable) {
return (status);
int status;
return (status);
return (status);
if (!ndmas) {
channel);
if (!ndmas) {
channel);
return (B_FALSE);
if (!ndmas) {
return (B_FALSE);
return (B_FALSE);
return (B_TRUE);
return (B_FALSE);
return (B_FALSE);
return (B_TRUE);
return (B_FALSE);
if (!ndmas) {
channel);
if (!ndmas) {
channel));
static hxge_status_t
int i, ndmas;
return (HXGE_ERROR);
if (!ndmas) {
return (HXGE_ERROR);
for (i = 0; i < ndmas; i++) {
goto hxge_map_txdma_fail1;
goto hxge_map_txdma_exit;
tx_mbox_p[i]);
return (status);
int i, ndmas;
if (!ndmas) {
for (i = 0; i < ndmas; i++) {
static hxge_status_t
return (status);
sizeof (tx_desc_t));
static hxge_status_t
int i, j, index;
nmsgs = 0;
if (!nmsgs) {
TASKQ_DEFAULTPRI, 0);
for (i = 0; i < nmsgs; i++) {
if (i < nmsgs) {
if (!hxge_tx_intr_thres) {
index = 0;
for (j = 0; j < nblocks; j++) {
if (i < num_chunks) {
index--;
return (status);
static hxge_status_t
int i, ndmas;
(uint64_t)i);
tmp = 0;
&tmp);
tmp = 0;
&tmp);
i, (unsigned long long)tmp));
if (tmp != 0) {
if (tmp != 0) {
i, (unsigned long long)tmp));
if (tmp != 0) {
goto hxge_txdma_hw_start_exit;
return (HXGE_ERROR);
return (HXGE_ERROR);
if (!ndmas) {
return (HXGE_ERROR);
for (i = 0; i < ndmas; i++) {
goto hxge_txdma_hw_start_exit;
return (status);
int i, ndmas;
if (!ndmas) {
for (i = 0; i < ndmas; i++) {
static hxge_status_t
return (status);
static hxge_status_t
return (status);
static p_tx_ring_t
return (NULL);
if (!ndmas) {
return (NULL);
return (NULL);
return (NULL);
static p_tx_mbox_t
return (NULL);
return (NULL);
if (!ndmas) {
return (NULL);
return (NULL);
return (NULL);
static hxge_status_t
if (txchan_fatal) {
return (status);
return (status);
static hxge_status_t
channel));
goto fail;
channel));
channel));
HPI_SUCCESS) {
goto fail;
channel));
goto fail;
goto fail;
channel));
goto fail;
return (HXGE_OK);
fail:
return (status);
static hxge_status_t
int i, ndmas;
for (i = 0; i < ndmas; i++) {
for (i = 0; i < ndmas; i++) {
goto fail;
for (i = 0; i < ndmas; i++) {
goto fail;
for (i = 0; i < ndmas; i++) {
return (HXGE_OK);
fail:
for (i = 0; i < ndmas; i++) {
return (status);