hxge_send.c revision 0dc2366f7b9f9f36e10909b1e95edbf2a261c2ac
/*
* CDDL HEADER START
*
* The contents of this file are subject to the terms of the
* Common Development and Distribution License (the "License").
* You may not use this file except in compliance with the License.
*
* You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
* See the License for the specific language governing permissions
* and limitations under the License.
*
* When distributing Covered Code, include this CDDL HEADER in each
* file and include the License file at usr/src/OPENSOLARIS.LICENSE.
* If applicable, add the following below this CDDL HEADER, with the
* fields enclosed by brackets "[]" replaced with your own identifying
* information: Portions Copyright [yyyy] [name of copyright owner]
*
* CDDL HEADER END
*/
/*
* Copyright 2010 Sun Microsystems, Inc. All rights reserved.
* Use is subject to license terms.
*/
#include <hxge_impl.h>
extern uint32_t hxge_reclaim_pending;
extern uint32_t hxge_bcopy_thresh;
extern uint32_t hxge_dvma_thresh;
extern uint32_t hxge_dma_stream_thresh;
extern uint32_t hxge_tx_minfree;
extern uint32_t hxge_tx_intr_thres;
extern uint32_t hxge_tx_max_gathers;
extern uint32_t hxge_tx_tiny_pack;
extern uint32_t hxge_tx_use_bcopy;
void
hxge_tx_ring_task(void *arg)
{
}
static void
{
/*
* Kick the ring task to reclaim some buffers.
*/
}
mblk_t *
{
int status;
if (status != 0) {
return (mp);
}
}
static int
{
int dma_status, status = 0;
int last_bidx;
int len;
t_uscalar_t start_offset = 0;
t_uscalar_t stuff_offset = 0;
t_uscalar_t end_offset = 0;
t_uscalar_t value = 0;
t_uscalar_t cksum_flags = 0;
#ifdef HXGE_DEBUG
int dump_len;
int sad_len;
int xfer_len;
#endif
"==> hxge_start: Starting tdc %d desc pending %d",
"link not up or LB mode"));
goto hxge_start_fail1;
}
}
&cksum_flags);
start_offset += sizeof (ether_header_t);
stuff_offset += sizeof (ether_header_t);
} else {
start_offset += sizeof (struct ether_vlan_header);
stuff_offset += sizeof (struct ether_vlan_header);
}
if (cksum_flags & HCK_PARTIALCKSUM) {
"==> hxge_start: mp $%p len %d "
"cksum_flags 0x%x (partial checksum) ",
}
ngathers = 0;
#ifdef HXGE_DEBUG
if (tx_ring_p->descs_pending) {
"==> hxge_start: desc pending %d ",
}
"==> hxge_start: tdc %d: dumping ...: b_rptr $%p "
"(Before header reserve: ORIGINAL LEN %d)",
"==> hxge_start: dump packets (IP ORIGINAL b_rptr $%p): %s",
#endif
"TX Descriptor ring is channel %d mark mode %d",
tdc_stats->tx_no_desc++;
status = 1;
goto hxge_start_fail1;
}
nmblks = 0;
ngathers = 0;
pkt_len = 0;
pack_len = 0;
clen = 0;
last_bidx = -1;
#ifdef HXGE_DEBUG
#if defined(__i386)
#else
#endif
#endif
sop_index, i));
#ifdef HXGE_DEBUG
"==> hxge_start(1): wr_index %d i %d msgdsize %d",
#endif
/*
* The first 16 bytes of the premapped buffer are reserved
* for header. No padding will be used.
*/
if (hxge_tx_use_bcopy) {
} else {
}
while (nmp) {
if (len <= 0) {
continue;
}
nmblks++;
"len %d pkt_len %d pack_len %d",
/*
* Hardware limits the transfer length to 4K.
* If len is more than 4K, we need to break
* nmp into two chunks: Make first chunk smaller
* than 4K. The second chunk will be broken into
* less than 4K (if needed) during the next pass.
*/
} else {
goto hxge_start_fail2;
}
}
tx_desc_p = &tx_desc_ring_vp[i];
#ifdef HXGE_DEBUG
tx_desc_pp = &tx_desc_ring_pp[i];
#endif
tx_msg_p = &tx_msg_ring[i];
#if defined(__i386)
#else
#endif
if (!header_set &&
(len >= bcopy_thresh))) {
header_set = B_TRUE;
boff = 0;
pack_len = 0;
(void) ddi_dma_sync(dma_handle,
}
"==> hxge_start(3): desc entry %d DESC IOADDR $%p "
"desc_vp $%p tx_desc_p $%p desc_pp $%p tx_desc_pp $%p "
"len %d pkt_len %d pack_len %d",
i,
if (len < bcopy_thresh) {
"==> hxge_start(4): USE BCOPY: "));
if (hxge_tx_tiny_pack) {
"==> hxge_start(5): pack"));
if ((pack_len <= bcopy_thresh) &&
"==> hxge_start: pack(6) "
"(pkt_len %d pack_len %d)",
i = blst;
tx_desc_p = &tx_desc_ring_vp[i];
#ifdef HXGE_DEBUG
tx_desc_pp = &tx_desc_ring_pp[i];
#endif
tx_msg_p = &tx_msg_ring[i];
ngathers--;
} else if (pack_len > bcopy_thresh &&
header_set) {
boff = 0;
"==> hxge_start(7): > max NEW "
"bcopy thresh %d "
"pkt_len %d pack_len %d(next)",
}
last_bidx = i;
}
header_set = B_TRUE;
"==> hxge_start(7_x2): "
"pkt_len %d pack_len %d (new hdrp $%p)",
}
"==> hxge_start(8): USE BCOPY: before bcopy "
"DESC IOADDR $%p entry %d bcopy packets %d "
"bcopy kaddr $%p bcopy ioaddr (SAD) $%p "
"bcopy clen %d bcopy boff %d",
"==> hxge_start: 1USE BCOPY: "));
"==> hxge_start: 2USE BCOPY: "));
"last USE BCOPY: copy from b_rptr $%p "
"to KADDR $%p (len %d offset %d",
#ifdef HXGE_DEBUG
"==> hxge_start: dump packets "
"(After BCOPY len %d)"
dump_len)));
#endif
(void) ddi_dma_sync(dma_handle,
tdc_stats->tx_hdr_pkts++;
"USE BCOPY: DESC IOADDR $%p entry %d "
"bcopy packets %d bcopy kaddr $%p "
"bcopy ioaddr (SAD) $%p bcopy clen %d "
"bcopy boff %d",
} else {
"==> hxge_start(12): USE DVMA: len %d", len));
if (len < hxge_dma_stream_thresh) {
} else {
}
&dma_cookie, &ncookies);
if (dma_status == DDI_DMA_MAPPED) {
"==> hxge_start(12_1): "
"USE DVMA: len %d clen %d ngathers %d",
#if defined(__i386)
#else
#endif
while (ncookies > 1) {
ngathers++;
/*
* this is the fix for multiple
* cookies, which are basically
* a descriptor entry, we don't set
* SOP bit as well as related fields
*/
(void) hpi_txdma_desc_gather_set(
"==> hxge_start: DMA "
"ncookie %d ngathers %d "
"dma_ioaddr $%p len %d"
"desc $%p descp $%p (%d)",
&dma_cookie);
"==> hxge_start(12_2): "
"USE DVMA: len %d clen %d ",
i = TXDMA_DESC_NEXT_INDEX(i, 1,
tx_desc_p = &tx_desc_ring_vp[i];
#if defined(__i386)
#else
#endif
tx_msg_p = &tx_msg_ring[i];
ncookies--;
}
tdc_stats->tx_ddi_pkts++;
"==> hxge_start: DMA: ddi packets %d",
tdc_stats->tx_ddi_pkts));
} else {
"dma mapping failed for %d "
"bytes addr $%p flags %x (%d)",
status = 1;
goto hxge_start_fail2;
}
} /* ddi dvma */
#if defined(__i386)
#else
#endif
ngathers++;
if (ngathers == 1) {
#ifdef HXGE_DEBUG
#endif
sop_tx_desc_p->value = 0;
} else {
#ifdef HXGE_DEBUG
save_desc_p = &tx_desc;
#endif
tmp_desc_p = &tx_desc;
tmp_desc_p->value = 0;
}
"==> hxge_start(13): Desc_entry %d ngathers %d "
"desc_vp $%p tx_desc_p $%p "
"len %d clen %d pkt_len %d pack_len %d nmblks %d "
"dma_ioaddr (SAD) $%p mark %d",
dma_ioaddr, mark_mode));
#ifdef HXGE_DEBUG
"\t\tsad $%p\ttr_len %d len %d\tnptrs %d\t"
"mark %d sop %d\n",
#endif
if (ngathers > hxge_tx_max_gathers) {
"==> hxge_start(14): pull msg - "
"len %d pkt_len %d ngathers %d",
goto hxge_start_fail2;
}
} /* while (nmp) */
#if defined(__i386)
#else
#endif
/*
* Hardware header should not be counted as part of the frame
* when determining the frame size
*/
}
/* Assume we use bcopy to premapped buffers */
"==> hxge_start(14-1): < (msg_min + 16)"
"len %d pkt_len %d min_len %d bzero %d ngathers %d",
"==> hxge_start(14-2): < msg_min - "
"len %d pkt_len %d min_len %d ngathers %d",
}
cksum_flags));
if (cksum_flags & HCK_PARTIALCKSUM) {
"==> hxge_start: cksum_flags 0x%x (partial checksum) ",
cksum_flags));
"==> hxge_start: from IP cksum_flags 0x%x "
"(partial checksum) "
"start_offset %d stuff_offset %d",
"==> hxge_start: from IP cksum_flags 0x%x "
"(partial checksum) "
"after SHIFT start_offset %d stuff_offset %d",
}
/*
* pkt_len already includes 16 + paddings!!
* Update the control header length
*/
/*
* Note that Hydra is different from Neptune where
* tot_xfer_len = (pkt_len - TX_PKT_HEADER_SIZE);
*/
"==> hxge_start(15_x1): setting SOP "
"tot_xfer_len 0x%llx (%d) pkt_len %d tmp_len "
"0x%llx hdrp->value 0x%llx",
#if defined(_BIG_ENDIAN)
#else
#endif
TX_CTL, "==> hxge_start(15_x2): setting SOP "
"after SWAP: tot_xfer_len 0x%llx pkt_len %d "
"tmp_len 0x%llx hdrp->value 0x%llx",
"wr_index %d tot_xfer_len (%d) pkt_len %d npads %d",
if (mark_mode)
#ifdef HXGE_DEBUG
"\t\tsad $%p\ttr_len %d len %d\tnptrs %d\tmark %d sop %d\n",
"==> hxge_start: dump packets(17) (after sop set, len "
" (len/dump_len/pkt_len/tot_xfer_len) %d/%d/%d/%d):\n"
"==> hxge_start(18): TX desc sync: sop_index %d", sop_index));
#endif
(void) ddi_dma_sync(tx_desc_dma_handle,
"cs_off = 0x%02X cs_s_off = 0x%02X "
"pkt_len %d ngathers %d sop_index %d\n",
} else { /* more than one descriptor and wrap around */
(void) ddi_dma_sync(tx_desc_dma_handle,
"cs_off = 0x%02X cs_s_off = 0x%02X "
"pkt_len %d ngathers %d sop_index %d\n",
(void) ddi_dma_sync(tx_desc_dma_handle, 0,
"cs_off = 0x%02X cs_s_off = 0x%02X "
"pkt_len %d ngathers %d sop_index %d\n",
}
}
"channel %d wr_index %d wrap %d ngathers %d desc_pend %d",
/* Kick start the Transmit kick register */
return (status);
if (good_packet == B_FALSE) {
for (i = 0; i < ngathers; i++) {
#if defined(__i386)
#else
#endif
"tx_desc_p = %X index = %d",
0, -1);
if (tx_ring_p->dvma_wr_index ==
tx_ring_p->dvma_wr_index = 0;
else
tx_msg_p->dma_handle)) {
"ddi_dma_unbind_handle failed");
}
}
}
}
/* Add FMA to check the access handle hxge_hregh */
return (status);
}