hxge_rxdma.h revision 8ad8db65d4781f61f1fd519144f555e6045100e1
/*
* CDDL HEADER START
*
* The contents of this file are subject to the terms of the
* Common Development and Distribution License (the "License").
* You may not use this file except in compliance with the License.
*
* You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
* See the License for the specific language governing permissions
* and limitations under the License.
*
* When distributing Covered Code, include this CDDL HEADER in each
* file and include the License file at usr/src/OPENSOLARIS.LICENSE.
* If applicable, add the following below this CDDL HEADER, with the
* fields enclosed by brackets "[]" replaced with your own identifying
* information: Portions Copyright [yyyy] [name of copyright owner]
*
* CDDL HEADER END
*/
/*
* Copyright 2008 Sun Microsystems, Inc. All rights reserved.
* Use is subject to license terms.
*/
#ifndef _SYS_HXGE_HXGE_RXDMA_H
#define _SYS_HXGE_HXGE_RXDMA_H
#ifdef __cplusplus
extern "C" {
#endif
#include <hxge_rdc_hw.h>
#include <hpi_rxdma.h>
#define RXDMA_RCR_PTHRES_DEFAULT 0x20
#define RXDMA_RCR_TO_DEFAULT 0x8
#define RXDMA_HDR_SIZE_DEFAULT 2
/*
* Receive Completion Ring (RCR)
*/
#define RCR_PKT_BUF_ADDR_SHIFT 0 /* bit 37:0 */
#define RCR_PKT_BUF_ADDR_MASK 0x0000003FFFFFFFFFULL
#define RCR_PKTBUFSZ_MASK 0x000000C000000000ULL
#define RCR_L2_LEN_MASK 0x003fff0000000000ULL
#define RCR_ERROR_MASK 0x03C0000000000000ULL
#define RCR_PKT_TYPE_MASK 0x6000000000000000ULL
#define RCR_MULTI_MASK 0x8000000000000000ULL
#define RCR_PKTBUFSZ_0 0x00
#define RCR_PKTBUFSZ_1 0x01
#define RCR_PKTBUFSZ_2 0x02
#define RCR_SINGLE_BLOCK 0x03
#define RCR_NO_ERROR 0x0
#define RCR_CTRL_FIFO_DED 0x1
#define RCR_DATA_FIFO_DED 0x2
#define RCR_ERROR_RESERVE 0x4
#define RCR_PKT_IS_TCP 0x2000000000000000ULL
#define RCR_PKT_IS_UDP 0x4000000000000000ULL
#define RCR_PKT_IS_SCTP 0x6000000000000000ULL
#define RDC_INT_MASK_RBRFULL_SHIFT 34
#define RDC_INT_MASK_RBRFULL_MASK 0x0000000400000000ULL
#define RDC_INT_MASK_RBREMPTY_SHIFT 35
#define RDC_INT_MASK_RBREMPTY_MASK 0x0000000800000000ULL
#define RDC_INT_MASK_RCRFULL_SHIFT 36
#define RDC_INT_MASK_RCRFULL_MASK 0x0000001000000000ULL
#define RDC_INT_MASK_RCRSH_FULL_SHIFT 39
#define RDC_INT_MASK_RCRSH_FULL_MASK 0x0000008000000000ULL
#define RDC_INT_MASK_RBR_PRE_EMPTY_SHIFT 40
#define RDC_INT_MASK_RBR_PRE_EMPTY_MASK 0x0000010000000000ULL
#define RDC_INT_MASK_RBR_PRE_PAR_SHIFT 43
#define RDC_INT_MASK_RBR_PRE_PAR_MASK 0x0000080000000000ULL
#define RDC_INT_MASK_RCR_SHA_PAR_SHIFT 44
#define RDC_INT_MASK_RCR_SHA_PAR_MASK 0x0000100000000000ULL
#define RDC_INT_MASK_RCRTO_SHIFT 45
#define RDC_INT_MASK_RCRTO_MASK 0x0000200000000000ULL
#define RDC_INT_MASK_THRES_SHIFT 46
#define RDC_INT_MASK_THRES_MASK 0x0000400000000000ULL
#define RDC_INT_MASK_PEU_ERR_SHIFT 52
#define RDC_INT_MASK_PEU_ERR_MASK 0x0010000000000000ULL
#define RDC_INT_MASK_RBR_CPL_SHIFT 53
#define RDC_INT_MASK_RBR_CPL_MASK 0x0020000000000000ULL
#define RDC_INT_MASK_ALL (RDC_INT_MASK_RBRFULL_MASK | \
#define RDC_STAT_PKTREAD_SHIFT 0 /* WO, bit 15:0 */
#define RDC_STAT_PKTREAD_MASK 0x000000000000ffffULL
#define RDC_STAT_PTRREAD_MASK 0x00000000FFFF0000ULL
#define RDC_STAT_RBRFULL 0x0000000400000000ULL
#define RDC_STAT_RBRFULL_MASK 0x0000000400000000ULL
#define RDC_STAT_RBREMPTY 0x0000000800000000ULL
#define RDC_STAT_RBREMPTY_MASK 0x0000000800000000ULL
#define RDC_STAT_RCR_FULL 0x0000001000000000ULL
#define RDC_STAT_RCR_FULL_MASK 0x0000001000000000ULL
#define RDC_STAT_RCR_SHDW_FULL 0x0000008000000000ULL
#define RDC_STAT_RCR_SHDW_FULL_MASK 0x0000008000000000ULL
#define RDC_STAT_RBR_PRE_EMPTY 0x0000010000000000ULL
#define RDC_STAT_RBR_PRE_EMPTY_MASK 0x0000010000000000ULL
#define RDC_STAT_RBR_PRE_PAR 0x0000080000000000ULL
#define RDC_STAT_RBR_PRE_PAR_MASK 0x0000080000000000ULL
#define RDC_STAT_RCR_SHA_PAR 0x0000100000000000ULL
#define RDC_STAT_RCR_SHA_PAR_MASK 0x0000100000000000ULL
#define RDC_STAT_RCR_TO 0x0000200000000000ULL
#define RDC_STAT_RCR_TO_MASK 0x0000200000000000ULL
#define RDC_STAT_RCR_THRES 0x0000400000000000ULL
#define RDC_STAT_RCR_THRES_MASK 0x0000400000000000ULL
#define RDC_STAT_RCR_MEX 0x0000800000000000ULL
#define RDC_STAT_RCR_MEX_MASK 0x0000800000000000ULL
#define RDC_STAT_PEU_ERR 0x0010000000000000ULL
#define RDC_STAT_PEU_ERR_MASK 0x0010000000000000ULL
#define RDC_STAT_RBR_CPL 0x0020000000000000ULL
#define RDC_STAT_RBR_CPL_MASK 0x0020000000000000ULL
#define RDC_STAT_ERROR RDC_INT_MASK_ALL
/* the following are write 1 to clear bits */
#define RDC_STAT_WR1C (RDC_STAT_RBREMPTY | \
RDC_STAT_RCR_TO | \
RDC_STAT_RBR_CPL | \
typedef union _rcr_entry_t {
struct {
#if defined(_BIG_ENDIAN)
#else
#endif
} bits;
} rcr_entry_t, *p_rcr_entry_t;
#define RX_DMA_MAILBOX_BYTE_LENGTH 64
typedef struct _rxdma_mailbox_t {
/*
* hardware workarounds: kick 16 (was 8 before)
*/
#define HXGE_RXDMA_POST_BATCH 16
#define RXBUF_64B_ALIGNED 64
#define HXGE_RXBUF_EXTRA 34
/*
* Receive buffer thresholds and buffer types
*/
typedef enum {
HXGE_RX_COPY_ALL = 0, /* do bcopy on every packet */
HXGE_RX_COPY_1, /* bcopy on 1/8 of buffer posted */
HXGE_RX_COPY_2, /* bcopy on 2/8 of buffer posted */
HXGE_RX_COPY_3, /* bcopy on 3/8 of buffer posted */
HXGE_RX_COPY_4, /* bcopy on 4/8 of buffer posted */
HXGE_RX_COPY_5, /* bcopy on 5/8 of buffer posted */
HXGE_RX_COPY_6, /* bcopy on 6/8 of buffer posted */
HXGE_RX_COPY_7, /* bcopy on 7/8 of buffer posted */
HXGE_RX_COPY_NONE /* don't do bcopy at all */
typedef enum {
typedef struct _rdc_errlog {
} rdc_errlog_t;
/*
* Receive Statistics.
*/
typedef struct _hxge_rx_ring_stats_t {
/*
* Error event stats.
*/
/*
* RCR invalids: when processing RCR entries, can
* run into invalid RCR entries. This counter provides
* a means to account for invalid RCR entries.
*/
typedef struct _hxge_rdc_sys_stats {
typedef struct _rx_msg_t {
struct _rx_rbr_ring_t *rx_rbr_p;
} rx_msg_t, *p_rx_msg_t;
/* Receive Completion Ring */
typedef struct _rx_rcr_ring_t {
struct _rx_rbr_ring_t *rx_rbr_p;
/* Buffer index information */
typedef struct _rxbuf_index_info_t {
/* Buffer index information */
typedef struct _rxring_info_t {
typedef enum {
RBR_UNMAPPING, /* We are in the process of unmapping. */
RBR_UNMAPPED /* The ring is unmapped. */
} rbr_state_t;
/* Receive Buffer Block Ring */
typedef struct _rx_rbr_ring_t {
/*
* <rbr_ref_cnt> is a count of those receive buffers which
* have been loaned to the kernel. We will not free this
* ring until the reference count reaches zero (0).
*/
int pages_to_post;
int pages_to_skip;
/* Receive Mailbox */
typedef struct _rx_mbox_t {
} rx_mbox_t, *p_rx_mbox_t;
typedef struct _rx_rbr_rings_t {
typedef struct _rx_rcr_rings_t {
typedef struct _rx_mbox_areas_t {
/*
* Receive DMA Prototypes.
*/
#ifdef __cplusplus
}
#endif
#endif /* _SYS_HXGE_HXGE_RXDMA_H */