hxge_main.c revision 3dec9fcdd56adf1b4a563137b4915c8f2d83b881
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs * CDDL HEADER START
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3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs * Copyright 2008 Sun Microsystems, Inc. All rights reserved.
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs * Use is subject to license terms.
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs#pragma ident "%Z%%M% %I% %E% SMI"
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs * SunOs MT STREAMS Hydra 10Gb Ethernet Device Driver.
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs * PSARC/2007/453 MSI-X interrupt limit override
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs * (This PSARC case is limited to MSI-X vectors
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs * and SPARC platforms only).
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs * Globals: tunable parameters (/etc/system or adb)
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qsstatic int hxge_debug_init = 0;
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs * Debugging flags:
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs * hxge_no_tx_lb : transmit load balancing
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs * hxge_tx_lb_policy: 0 - TCP/UDP port (default)
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs * 1 - From the Stack
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs * 2 - Destination IP Address
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs * Add tunable to reduce the amount of time spent in the
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs * ISR doing Rx Processing.
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs * Tunables to manage the receive buffer blocks.
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs * hxge_rx_threshold_hi: copy all buffers.
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs * hxge_rx_bcopy_size_type: receive buffer block size type.
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs * hxge_rx_threshold_lo: copy only up to tunable block size type.
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qshxge_rxbuf_threshold_t hxge_rx_threshold_hi = HXGE_RX_COPY_6;
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qshxge_rxbuf_threshold_t hxge_rx_threshold_lo = HXGE_RX_COPY_3;
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs * Function Prototypes
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qsstatic hxge_status_t hxge_setup_system_dma_pages(p_hxge_t);
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qsstatic hxge_status_t hxge_add_intrs_adv_type(p_hxge_t, uint32_t);
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qsstatic hxge_status_t hxge_add_intrs_adv_type_fix(p_hxge_t, uint32_t);
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qsstatic hxge_status_t hxge_dma_mem_alloc(p_hxge_t, dma_method_t,
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs struct ddi_dma_attr *, size_t, ddi_device_acc_attr_t *, uint_t,
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qsstatic hxge_status_t hxge_alloc_rx_buf_dma(p_hxge_t, uint16_t,
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qsstatic void hxge_free_rx_buf_dma(p_hxge_t, p_hxge_dma_common_t, uint32_t);
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qsstatic hxge_status_t hxge_alloc_rx_cntl_dma(p_hxge_t, uint16_t,
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qsstatic void hxge_free_rx_cntl_dma(p_hxge_t, p_hxge_dma_common_t);
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qsstatic hxge_status_t hxge_alloc_tx_buf_dma(p_hxge_t, uint16_t,
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qsstatic void hxge_free_tx_buf_dma(p_hxge_t, p_hxge_dma_common_t, uint32_t);
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qsstatic hxge_status_t hxge_alloc_tx_cntl_dma(p_hxge_t, uint16_t,
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qsstatic void hxge_free_tx_cntl_dma(p_hxge_t, p_hxge_dma_common_t);
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs * The next declarations are for the GLDv3 interface.
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qsstatic int hxge_m_start(void *);
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qsstatic void hxge_m_stop(void *);
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qsstatic int hxge_m_multicst(void *, boolean_t, const uint8_t *);
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qsstatic void hxge_m_resources(void *);
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qsstatic int hxge_m_mmac_add(void *arg, mac_multi_addr_t *maddr);
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qsstatic int hxge_m_mmac_remove(void *arg, mac_addr_slot_t slot);
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qsstatic int hxge_m_mmac_modify(void *arg, mac_multi_addr_t *maddr);
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qsstatic int hxge_m_mmac_get(void *arg, mac_multi_addr_t *maddr);
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qsstatic boolean_t hxge_m_getcapab(void *, mac_capab_t, void *);
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs#define HXGE_M_CALLBACK_FLAGS (MC_RESOURCES | MC_IOCTL | MC_GETCAPAB)
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qsextern hxge_status_t hxge_pfc_set_default_mac_addr(p_hxge_t hxgep);
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs/* Enable debug messages as necessary. */
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs * This list contains the instance structures for the Hydra
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs * devices present in the system. The lock exists to guarantee
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs * mutually exclusive access to the list.
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qsextern void hxge_fm_init(p_hxge_t hxgep, ddi_device_acc_attr_t *reg_attr,
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs ddi_device_acc_attr_t *desc_attr, ddi_dma_attr_t *dma_attr);
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs * Count used to maintain the number of buffers being used
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs * by Hydra instances and loaned up to the upper layers.
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs * Device register access attributes for PIO.
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs * Device descriptor access attributes for DMA.
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qsstatic ddi_device_acc_attr_t hxge_dev_desc_dma_acc_attr = {
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs * Device buffer access attributes for DMA.
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qsstatic ddi_device_acc_attr_t hxge_dev_buf_dma_acc_attr = {
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs 0, /* low address */
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs 0 /* attribute flags */
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs 0, /* low address */
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs 0 /* attribute flags */
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs 0, /* low address */
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs (uint_t)0xfc00fc, /* dlim_burstsizes for 32 and 64 bit xfers */
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs * dma chunk sizes.
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs * Try to allocate the largest possible size
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs * so that fewer number of dma chunks would be managed
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs * Translate "dev_t" to a pointer to the associated "dev_info_t".
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs * Get the device instance since we'll need to setup or retrieve a soft
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs * state for this instance.
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs switch (cmd) {
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs hxgep = (p_hxge_t)ddi_get_soft_state(hxge_list, instance);
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs hxgep = (p_hxge_t)ddi_get_soft_state(hxge_list, instance);
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs if (ddi_soft_state_zalloc(hxge_list, instance) == DDI_FAILURE) {
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs "ddi_soft_state_zalloc failed"));
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs "ddi_get_soft_state failed"));
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs hxge_fm_init(hxgep, &hxge_dev_reg_acc_attr, &hxge_dev_desc_dma_acc_attr,
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs HXGE_ERROR_MSG((hxgep, HXGE_ERR_CTL, "hxge_map_regs failed"));
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs "hxge_init_common_dev failed"));
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs * Setup the Ndd parameters for this instance.
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs * Setup Register Tracing Buffer.
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs /* init stats ptr */
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs HXGE_ERROR_MSG((hxgep, HXGE_ERR_CTL, "get_hw create failed"));
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs * Setup the Kstats for the driver.
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs HXGE_ERROR_MSG((hxgep, HXGE_ERR_CTL, "set dma page failed"));
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs HXGE_DEBUG_MSG((hxgep, HXGE_ERR_CTL, "add_soft_intr failed"));
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs * Enable interrupts.
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs HXGE_DEBUG_MSG((hxgep, DDI_CTL, "registered to mac (instance %d)",
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs * Tear down the ndd parameters setup.
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs * Tear down the kstat setup.
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs * Unmap the register setup.
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs HXGE_DEBUG_MSG((hxgep, DDI_CTL, "<== hxge_attach status = 0x%08x",
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs switch (cmd) {
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs HXGE_DEBUG_MSG((hxgep, DDI_CTL, "doing DDI_PM_SUSPEND"));
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs * Stop the xcvr polling.
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs if (hxgep->mach && (status = mac_unregister(hxgep->mach)) != 0) {
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs "<== hxge_detach (mac_unregister) status = 0x%08X", status));
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs HXGE_DEBUG_MSG((hxgep, DDI_CTL, "<== hxge_detach status = 0x%08X",
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qsstatic void
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs /* Stop any further interrupts. */
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs /* Remove soft interrups */
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs /* Stop the device and free resources. */
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs /* Tear down the ndd parameters setup. */
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs /* Tear down the kstat setup. */
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs /* Destroy all mutexes. */
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs * Remove the list of ndd parameters which were setup during attach.
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs " hxge_unattach: remove all properties"));
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs * Unmap the register setup.
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs * Free the soft state data structures allocated with this instance.
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs HXGE_DEBUG_MSG((hxgep, DDI_CTL, "hxge_map_regs: nregs: %d", nregs));
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs "ddi_map_regs, hxge bus config regs failed"));
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs "hxge_map_reg: PCI config addr 0x%0llx handle 0x%0llx",
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs /* set up the device mapped register */
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs "ddi_map_regs for Hydra global reg failed"));
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs /* set up the msi/msi-x mapped register */
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs "ddi_map_regs for msi reg failed"));
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs HPI_PCI_ADD_HANDLE_SET(hxgep, (hpi_reg_ptr_t)dev_regs->hxge_pciregp);
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs HPI_MSI_ADD_HANDLE_SET(hxgep, (hpi_reg_ptr_t)dev_regs->hxge_msix_regp);
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs HPI_ADD_HANDLE_SET(hxgep, (hpi_reg_ptr_t)dev_regs->hxge_regp);
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs HPI_REG_ADD_HANDLE_SET(hxgep, (hpi_reg_ptr_t)dev_regs->hxge_regp);
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs HXGE_DEBUG_MSG((hxgep, DDI_CTL, "hxge_map_reg: hardware addr 0x%0llx "
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs " handle 0x%0llx", dev_regs->hxge_regp, dev_regs->hxge_regh));
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs HXGE_DEBUG_MSG((hxgep, DDI_CTL, "Freeing register set memory"));
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qsstatic void
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs "==> hxge_unmap_regs: bus"));
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs "==> hxge_unmap_regs: device registers"));
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs "==> hxge_unmap_regs: device interrupts"));
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs HXGE_DEBUG_MSG((hxgep, DDI_CTL, "==> hxge_setup_mutexes"));
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs * Get the interrupt cookie so the mutexes can be Initialised.
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs * Initialize mutex's for this device.
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qsstatic void
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs HXGE_DEBUG_MSG((hxgep, DDI_CTL, "==> hxge_destroy_mutexes"));
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs HXGE_DEBUG_MSG((hxgep, DDI_CTL, "<== hxge_destroy_mutexes"));
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs * Allocate system memory for the receive/transmit buffer blocks and
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs * receive/transmit descriptor rings.
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs HXGE_ERROR_MSG((hxgep, HXGE_ERR_CTL, "alloc mem failed\n"));
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs * Initialize and enable TXDMA channels.
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs HXGE_ERROR_MSG((hxgep, HXGE_ERR_CTL, "init txdma failed\n"));
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs * Initialize and enable RXDMA channels.
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs HXGE_ERROR_MSG((hxgep, HXGE_ERR_CTL, "init rxdma failed\n"));
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs * Initialize TCAM
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs HXGE_ERROR_MSG((hxgep, HXGE_ERR_CTL, "init classify failed\n"));
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs * Initialize the VMAC block.
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs HXGE_ERROR_MSG((hxgep, HXGE_ERR_CTL, "init MAC failed\n"));
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs /* Bringup - this may be unnecessary when PXE and FCODE available */
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs "Default Address Failure\n"));
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs * Enable hardware interrupts.
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs HXGE_DEBUG_MSG((hxgep, DDI_CTL, "<== hxge_init status = 0x%08x",
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs if ((hxgep->suspended == 0) || (hxgep->suspended == DDI_RESUME)) {
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs/*ARGSUSED*/
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs "==> hxge_uninit: not initialized"));
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs /* Stop timer */
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs /* Reset the receive VMAC side. */
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs /* Free classification resources */
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs /* Reset the transmit/receive DMA side. */
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs /* Reset the transmit VMAC side. */
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs#if defined(__i386)
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs bcopy((char *)mp->b_rptr, (char *)®, sizeof (uint64_t));
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs for (i = 0; i < retry; i++) {
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs bcopy((char *)®data, (char *)mp->b_rptr, sizeof (uint64_t));
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs#if defined(__i386)
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs bcopy((char *)mp->b_rptr, (char *)&buf[0], 2 * sizeof (uint64_t));
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs#if defined(__i386)
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs/*ARGSUSED*/
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs/*VARARGS*/
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qshxge_debug_msg(p_hxge_t hxgep, uint64_t level, char *fmt, ...)
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs /* do the msg processing */
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs cmn_err(cmn_level, "%s %s\n", prefix_buffer, msg_buffer);
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs /* Dump the leading bytes */
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs for (i = 0; i < 20; i++)
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs /* Dump the last MAX_DUMP_SZ/2 bytes */
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs for (i = 0; i < size; i++) {
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qsstatic void
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs if (fm_check_acc_handle(hxgep->dev_regs->hxge_regh) != DDI_FM_OK) {
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs "Bad register acc handle"));
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qsstatic void
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs HXGE_DEBUG_MSG((hxgep, DDI_CTL, "==> hxge_destroy_dev"));
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs HXGE_DEBUG_MSG((hxgep, DDI_CTL, "<== hxge_destroy_dev"));
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs HXGE_DEBUG_MSG((hxgep, DDI_CTL, "==> hxge_setup_system_dma_pages"));
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs " hxge_setup_system_dma_pages: page %d (ddi_ptob %d) "
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs " default_block_size %d iommu_pagesize %d",
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs /* Hydra support up to 8K pages */
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs "==> hxge_setup_system_dma_pages: page %d (ddi_ptob %d) "
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs "default_block_size %d page mask %d",
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs case 0x1000:
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs case 0x2000:
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs * Get the system DMA burst size.
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs ddi_status = ddi_dma_alloc_handle(hxgep->dip, &hxge_tx_dma_attr,
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs "ddi_dma_alloc_handle: failed status 0x%x", ddi_status));
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs ddi_status = ddi_dma_addr_bind_handle(hxgep->dmasparehandle, NULL,
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs (caddr_t)hxgep->dmasparehandle, sizeof (hxgep->dmasparehandle),
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs "Binding spare handle to find system burstsize failed."));
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs hxgep->sys_burst_sz = ddi_dma_burstsizes(hxgep->dmasparehandle);
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs "<== hxge_setup_system_dma_pages status = 0x%08x", status));
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs HXGE_DEBUG_MSG((hxgep, DDI_CTL, "==> hxge_alloc_mem_pool"));
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs HXGE_DEBUG_MSG((hxgep, DDI_CTL, "<== hxge_alloc_mem_pool"));
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qsstatic void
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs HXGE_DEBUG_MSG((hxgep, MEM_CTL, "==> hxge_free_mem_pool"));
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs HXGE_DEBUG_MSG((hxgep, MEM_CTL, "<== hxge_free_mem_pool"));
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs HXGE_DEBUG_MSG((hxgep, DMA_CTL, "==> hxge_alloc_rx_mem_pool"));
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs " hxge_alloc_rx_mem_pool st_rdc %d ndmas %d", st_rdc, ndmas));
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs * Allocate memory for each receive DMA channel.
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs dma_poolp = (p_hxge_dma_pool_t)KMEM_ZALLOC(sizeof (hxge_dma_pool_t),
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs num_chunks = (uint32_t *)KMEM_ZALLOC(sizeof (uint32_t) * ndmas,
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs * Assume that each DMA channel will be configured with default block
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs * size. rbr block counts are mod of batch count (16).
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs * Addresses of receive block ring, receive completion ring and the
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs * mailbox must be all cache-aligned (64 bytes).
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs rx_cntl_alloc_size = hxge_port_rbr_size + hxge_port_rbr_spare_size;
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs rx_cntl_alloc_size += (sizeof (rcr_entry_t) * hxge_port_rcr_size);
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs HXGE_DEBUG_MSG((hxgep, MEM2_CTL, "==> hxge_alloc_rx_mem_pool: "
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs "hxge_port_rbr_size = %d hxge_port_rbr_spare_size = %d "
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs "hxge_port_rcr_size = %d rx_cntl_alloc_size = %d",
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs * Allocate memory for receive buffers and descriptor rings. Replace
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs * allocation functions with interface functions provided by the
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs * partition manager when it is available.
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs * Allocate memory for the receive buffer blocks.
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs for (i = 0; i < ndmas; i++) {
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs " hxge_alloc_rx_mem_pool to alloc mem: "
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs " dma %d dma_buf_p %llx &dma_buf_p %llx",
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs status = hxge_alloc_rx_buf_dma(hxgep, st_rdc, &dma_buf_p[i],
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs " hxge_alloc_rx_mem_pool DONE alloc mem: "
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs "dma %d dma_buf_p %llx &dma_buf_p %llx", i,
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs if (i < ndmas) {
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs * Allocate memory for descriptor rings and mailbox.
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs for (j = 0; j < ndmas; j++) {
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs status = hxge_alloc_rx_cntl_dma(hxgep, st_rdc, &dma_cntl_p[j],
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs if (j < ndmas) {
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs /* Free control buffers */
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs "==> hxge_alloc_rx_mem_pool: freeing control bufs (%d)", j));
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs for (; j >= 0; j--) {
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs "==> hxge_alloc_rx_mem_pool: control bufs freed (%d)", j));
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs "==> hxge_alloc_rx_mem_pool: control bufs freed (%d)", j));
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs /* Free data buffers */
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs "==> hxge_alloc_rx_mem_pool: freeing data bufs (%d)", i));
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs for (; i >= 0; i--) {
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs hxge_free_rx_buf_dma(hxgep, (p_hxge_dma_common_t)dma_buf_p[i],
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs "==> hxge_alloc_rx_mem_pool: data bufs freed (%d)", i));
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs KMEM_FREE(dma_buf_p, ndmas * sizeof (p_hxge_dma_common_t));
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs KMEM_FREE(dma_cntl_p, ndmas * sizeof (p_hxge_dma_common_t));
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qsstatic void
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs HXGE_DEBUG_MSG((hxgep, MEM2_CTL, "==> hxge_free_rx_mem_pool"));
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs HXGE_DEBUG_MSG((hxgep, MEM2_CTL, "<== hxge_free_rx_mem_pool "
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs "(null rx buf pool or buf not allocated"));
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs if (dma_cntl_poolp == NULL || (!dma_cntl_poolp->buf_allocated)) {
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs "<== hxge_free_rx_mem_pool "
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs "(null rx cntl buf pool or cntl buf not allocated"));
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs for (i = 0; i < ndmas; i++) {
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs hxge_free_rx_buf_dma(hxgep, dma_buf_p[i], num_chunks[i]);
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs for (i = 0; i < ndmas; i++) {
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs for (i = 0; i < ndmas; i++) {
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs KMEM_FREE(dma_cntl_p, ndmas * sizeof (p_hxge_dma_common_t));
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs KMEM_FREE(dma_buf_p, ndmas * sizeof (p_hxge_dma_common_t));
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs HXGE_DEBUG_MSG((hxgep, MEM2_CTL, "<== hxge_free_rx_mem_pool"));
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qshxge_alloc_rx_buf_dma(p_hxge_t hxgep, uint16_t dma_channel,
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs size_t alloc_size, size_t block_size, uint32_t *num_chunks)
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs HXGE_DEBUG_MSG((hxgep, DMA_CTL, "==> hxge_alloc_rx_buf_dma"));
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs KMEM_ZALLOC(sizeof (hxge_dma_common_t) * HXGE_DMA_BLOCK, KM_SLEEP);
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs " alloc_rx_buf_dma rdc %d asize %x bsize %x bbuf %llx ",
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs rx_dmap[i].nblocks = alloc_sizes[size_index] / block_size;
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs "alloc_rx_buf_dma rdc %d chunk %d bufp %llx size %x "
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs "i %d nblocks %d alength %d",
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs " hxge_alloc_rx_buf_dma: Alloc Failed: "
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs " alloc_rx_buf_dma allocated rdc %d "
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs "chunk %d size %x dvma %x bufp %llx ",
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs " hxge_alloc_rx_buf_dma failed due to"
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs " allocated(%d) < required(%d)",
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs " alloc_rx_buf_dma rdc %d allocated %d chunks", dma_channel, i));
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs KMEM_FREE(rx_dmap, sizeof (hxge_dma_common_t) * HXGE_DMA_BLOCK);
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs/*ARGSUSED*/
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qsstatic void
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qshxge_free_rx_buf_dma(p_hxge_t hxgep, p_hxge_dma_common_t dmap,
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs "==> hxge_free_rx_buf_dma: # of chunks %d", num_chunks));
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs for (i = 0; i < num_chunks; i++) {
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs "==> hxge_free_rx_buf_dma: chunk %d dmap 0x%llx", i, dmap));
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs HXGE_DEBUG_MSG((hxgep, MEM2_CTL, "<== hxge_free_rx_buf_dma"));
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs/*ARGSUSED*/
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qshxge_alloc_rx_cntl_dma(p_hxge_t hxgep, uint16_t dma_channel,
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs HXGE_DEBUG_MSG((hxgep, DMA_CTL, "==> hxge_alloc_rx_cntl_dma"));
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs " hxge_alloc_rx_cntl_dma: Alloc Failed: "
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs/*ARGSUSED*/
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qsstatic void
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qshxge_free_rx_cntl_dma(p_hxge_t hxgep, p_hxge_dma_common_t dmap)
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs HXGE_DEBUG_MSG((hxgep, DMA_CTL, "==> hxge_free_rx_cntl_dma"));
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs HXGE_DEBUG_MSG((hxgep, DMA_CTL, "<== hxge_free_rx_cntl_dma"));
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs HXGE_DEBUG_MSG((hxgep, MEM_CTL, "==> hxge_alloc_tx_mem_pool"));
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs HXGE_DEBUG_MSG((hxgep, MEM_CTL, "==> hxge_alloc_tx_mem_pool: "
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs "p_cfgp 0x%016llx start_tdc %d ndmas %d hxgep->max_tdcs %d",
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs p_cfgp, p_cfgp->start_tdc, p_cfgp->max_tdcs, hxgep->max_tdcs));
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs * Allocate memory for each transmit DMA channel.
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs dma_poolp = (p_hxge_dma_pool_t)KMEM_ZALLOC(sizeof (hxge_dma_pool_t),
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs * Assume that each DMA channel will be configured with default
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs * transmit bufer size for copying transmit data. (For packet payload
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs * over this limit, packets will not be copied.)
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs tx_buf_alloc_size = (hxge_bcopy_thresh * hxge_tx_ring_size);
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs * Addresses of transmit descriptor ring and the mailbox must be all
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs * cache-aligned (64 bytes).
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs num_chunks = (uint32_t *)KMEM_ZALLOC(sizeof (uint32_t) * ndmas,
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs * Allocate memory for transmit buffers and descriptor rings. Replace
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs * allocation functions with interface functions provided by the
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs * partition manager when it is available.
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs * Allocate memory for the transmit buffer pool.
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs for (i = 0; i < ndmas; i++) {
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs status = hxge_alloc_tx_buf_dma(hxgep, st_tdc, &dma_buf_p[i],
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs if (i < ndmas) {
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs * Allocate memory for descriptor rings and mailbox.
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs for (j = 0; j < ndmas; j++) {
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs status = hxge_alloc_tx_cntl_dma(hxgep, st_tdc, &dma_cntl_p[j],
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs if (j < ndmas) {
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs "==> hxge_alloc_tx_mem_pool: start_tdc %d "
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs "ndmas %d poolp->ndmas %d", st_tdc, ndmas, dma_poolp->ndmas));
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs /* Free control buffers */
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs for (; j >= 0; j--) {
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs /* Free data buffers */
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs for (; i >= 0; i--) {
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs hxge_free_tx_buf_dma(hxgep, (p_hxge_dma_common_t)dma_buf_p[i],
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs KMEM_FREE(dma_buf_p, ndmas * sizeof (p_hxge_dma_common_t));
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs KMEM_FREE(dma_cntl_p, ndmas * sizeof (p_hxge_dma_common_t));
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qshxge_alloc_tx_buf_dma(p_hxge_t hxgep, uint16_t dma_channel,
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs HXGE_DEBUG_MSG((hxgep, DMA_CTL, "==> hxge_alloc_tx_buf_dma"));
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs KMEM_ZALLOC(sizeof (hxge_dma_common_t) * HXGE_DMA_BLOCK, KM_SLEEP);
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs tx_dmap[i].nblocks = alloc_sizes[size_index] / block_size;
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs " hxge_alloc_tx_buf_dma: Alloc Failed: "
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs " hxge_alloc_tx_buf_dma: failed due to"
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs " allocated(%d) < required(%d)",
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs "==> hxge_alloc_tx_buf_dma dmap 0x%016llx num chunks %d",
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs KMEM_FREE(tx_dmap, sizeof (hxge_dma_common_t) * HXGE_DMA_BLOCK);
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs/*ARGSUSED*/
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qsstatic void
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qshxge_free_tx_buf_dma(p_hxge_t hxgep, p_hxge_dma_common_t dmap,
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs HXGE_DEBUG_MSG((hxgep, MEM_CTL, "==> hxge_free_tx_buf_dma"));
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs for (i = 0; i < num_chunks; i++) {
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs HXGE_DEBUG_MSG((hxgep, MEM_CTL, "<== hxge_free_tx_buf_dma"));
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs/*ARGSUSED*/
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qshxge_alloc_tx_cntl_dma(p_hxge_t hxgep, uint16_t dma_channel,
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs HXGE_DEBUG_MSG((hxgep, DMA_CTL, "==> hxge_alloc_tx_cntl_dma"));
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs tx_dmap = (p_hxge_dma_common_t)KMEM_ZALLOC(sizeof (hxge_dma_common_t),
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs " hxge_alloc_tx_cntl_dma: Alloc Failed: "
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs/*ARGSUSED*/
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qsstatic void
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qshxge_free_tx_cntl_dma(p_hxge_t hxgep, p_hxge_dma_common_t dmap)
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs HXGE_DEBUG_MSG((hxgep, DMA_CTL, "==> hxge_free_tx_cntl_dma"));
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs HXGE_DEBUG_MSG((hxgep, DMA_CTL, "<== hxge_free_tx_cntl_dma"));
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qsstatic void
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs HXGE_DEBUG_MSG((hxgep, MEM3_CTL, "==> hxge_free_tx_mem_pool"));
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs "<== hxge_free_tx_mem_pool "
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs "(null rx buf pool or buf not allocated"));
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs if (dma_cntl_poolp == NULL || (!dma_cntl_poolp->buf_allocated)) {
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs "<== hxge_free_tx_mem_pool "
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs "(null tx cntl buf pool or cntl buf not allocated"));
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs for (i = 0; i < ndmas; i++) {
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs hxge_free_tx_buf_dma(hxgep, dma_buf_p[i], num_chunks[i]);
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs for (i = 0; i < ndmas; i++) {
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs for (i = 0; i < ndmas; i++) {
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs KMEM_FREE(dma_cntl_p, ndmas * sizeof (p_hxge_dma_common_t));
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs KMEM_FREE(dma_buf_p, ndmas * sizeof (p_hxge_dma_common_t));
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs HXGE_DEBUG_MSG((hxgep, MEM3_CTL, "<== hxge_free_tx_mem_pool"));
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs/*ARGSUSED*/
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs size_t length, ddi_device_acc_attr_t *acc_attr_p, uint_t xfer_flags,
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs "hxge_dma_mem_alloc:ddi_dma_alloc_handle failed."));
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs ddi_status = ddi_dma_mem_alloc(dma_p->dma_handle, length, acc_attr_p,
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs xfer_flags, DDI_DMA_DONTWAIT, 0, &kaddrp, &dma_p->alength,
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs /* The caller will decide whether it is fatal */
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs "hxge_dma_mem_alloc:ddi_dma_mem_alloc failed"));
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs "hxge_dma_mem_alloc:ddi_dma_mem_alloc < length."));
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs ddi_status = ddi_dma_addr_bind_handle(dma_p->dma_handle, NULL,
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs "hxge_dma_mem_alloc:di_dma_addr_bind failed "
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs "(staus 0x%x ncookies %d.)", ddi_status, dma_p->ncookies));
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs "hxge_dma_mem_alloc:ddi_dma_addr_bind > 1 cookie"
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs "(staus 0x%x ncookies %d.)", ddi_status, dma_p->ncookies));
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs#if defined(__i386)
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs (unsigned char *)(uint32_t)dma_p->dma_cookie.dmac_laddress;
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs dma_p->ioaddr_pp = (unsigned char *) dma_p->dma_cookie.dmac_laddress;
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs HXGE_DEBUG_MSG((hxgep, DMA_CTL, "<== hxge_dma_mem_alloc: "
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs "dma buffer allocated: dma_p $%p "
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs "return dmac_ladress from cookie $%p dmac_size %d "
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs "dma_p->ioaddr_p $%p "
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs "dma_p->orig_ioaddr_p $%p "
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs "orig_vatopa $%p "
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs "alength %d (0x%x) "
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs "kaddrp $%p "
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs "length %d (0x%x)",
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qsstatic void
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs * hxge_m_start() -- start transmitting and receiving.
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs * This function is called by the MAC layer when the first
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs * stream is open to prepare the hardware ready for sending
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs * and transmitting packets.
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs "<== hxge_m_start: initialization failed"));
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs * Start timer to check the system error and tx hangs
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs return (0);
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs * hxge_m_stop(): stop transmitting and receiving.
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qsstatic void
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs "<== hxge_m_unicst: set unitcast failed"));
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs return (0);
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qshxge_m_multicst(void *arg, boolean_t add, const uint8_t *mca)
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs HXGE_DEBUG_MSG((hxgep, MAC_CTL, "==> hxge_m_multicst: add %d", add));
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs "<== hxge_m_multicst: add multicast failed"));
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs "<== hxge_m_multicst: del multicast failed"));
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs return (0);
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs HXGE_DEBUG_MSG((hxgep, MAC_CTL, "==> hxge_m_promisc: on %d", on));
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs "<== hxge_m_promisc: set promisc failed"));
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs HXGE_DEBUG_MSG((hxgep, MAC_CTL, "<== hxge_m_promisc: on %d", on));
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs return (0);
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qsstatic void
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs HXGE_DEBUG_MSG((hxgep, NEMO_CTL, "==> hxge_m_ioctl: cmd 0x%08x", cmd));
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs switch (cmd) {
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs HXGE_DEBUG_MSG((hxgep, NEMO_CTL, "<== hxge_m_ioctl: invalid"));
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs if (err != 0) {
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs "<== hxge_m_ioctl: no priv"));
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs switch (cmd) {
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qsextern void hxge_rx_hw_blank(void *arg, time_t ticks, uint_t count);
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qsstatic void
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs "hxge_init failed"));
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs * Export our receive resources to the MAC layer.
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs for (i = 0; i < ndmas; i++) {
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs "==> hxge_m_resources: vdma %d dma %d "
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs "rcrptr 0x%016llx mac_handle 0x%016llx",
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs * Set an alternate MAC address
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qshxge_altmac_set(p_hxge_t hxgep, uint8_t *maddr, mac_addr_slot_t slot)
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs * Convert a byte array to a 48 bit value.
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs * Need to check endianess if in doubt
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs for (i = 0; i < ETHERADDRL; i++) {
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs status = hpi_pfc_set_mac_address(hxgep->hpi_handle, addrn, address);
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs return (0);
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qsstatic void
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qshxge_mmac_kstat_update(p_hxge_t hxgep, mac_addr_slot_t slot)
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs for (i = 0; i < ETHERADDRL; i++) {
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs * Find an unused address slot, set the address value to the one specified,
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs * enable the port to start filtering on the new MAC address.
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs * Returns: 0 on success.
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs * Make sure that hxge is initialized, if _start() has
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs * not been called.
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs * Search for the first available slot. Because naddrfree
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs * is not zero, we are guaranteed to find one.
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs * Slot 0 is for unique (primary) MAC. The first alternate
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs * MAC slot is slot 1.
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs if ((err = hxge_altmac_set(hxgep, maddr->mma_addr, slot)) != 0) {
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs bcopy(maddr->mma_addr, mmac_info->mac_pool[slot].addr, ETHERADDRL);
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs return (0);
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs * Remove the specified mac address and update
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs * the h/w not to filter the mac address anymore.
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs * Returns: 0, on success.
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs * Make sure that hxge is initialized, if _start() has
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs * not been called.
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs * Clear mac_pool[slot].addr so that kstat shows 0
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs * alternate MAC address if the slot is not used.
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs * Modify a mac address added by hxge_mmac_add().
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs * Returns: 0, on success.
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs * Make sure that hxge is initialized, if _start() has
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs * not been called.
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs * static int
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs * hxge_m_mmac_get() - Get the MAC address and other information
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs * related to the slot. mma_flags should be set to 0 in the call.
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs * Note: although kstat shows MAC address as zero when a slot is
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs * not used, Crossbow expects hxge_m_mmac_get to copy factory MAC
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs * to the caller as long as the slot is not using a user MAC address.
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs * The following table shows the rules,
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs * USED VENDOR mma_addr
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs * ------------------------------------------------------------
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs * (1) Slot uses a user MAC: yes no user MAC
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs * (2) Slot uses a factory MAC: yes yes factory MAC
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs * (3) Slot is not used but is
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs * factory MAC capable: no yes factory MAC
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs * (4) Slot is not used and is
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs * not factory MAC capable: no no 0
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs * ------------------------------------------------------------
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs * Make sure that hxge is initialized, if _start() has
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs * not been called.
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs return (0);
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs/*ARGSUSED*/
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qshxge_m_getcapab(void *arg, mac_capab_t cap, void *cap_data)
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs switch (cap) {
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs * There's nothing for us to fill in, simply returning B_TRUE
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs * stating that we support polling is sufficient.
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs * The number of MAC addresses made available by
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs * this capability is one less than the total as
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs * the primary address in slot 0 is counted in
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs * the total.
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs mmacp->maddr_naddrfree = hxgep->hxge_mmac_info.naddrfree;
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs mmacp->maddr_reserve = NULL; /* No multiple factory macs */
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs * Module loading and removing entry points.
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qsDDI_DEFINE_STREAM_OPS(hxge_dev_ops, nulldev, nulldev, hxge_attach, hxge_detach,
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs * Module linkage information for the kernel.
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs status = ddi_soft_state_init(&hxge_list, sizeof (hxge_t), 0);
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs if (status != 0) {
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs "failed to init device soft state"));
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs if (status != 0) {
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs HXGE_ERROR_MSG((NULL, HXGE_ERR_CTL, "Mod install failed"));
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs HXGE_DEBUG_MSG((NULL, MOD_CTL, "_init status = 0x%X", status));
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs HXGE_DEBUG_MSG((NULL, MOD_CTL, "==> _fini: mod_remove"));
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs HXGE_DEBUG_MSG((NULL, MOD_CTL, "_fini status = 0x%08x", status));
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs HXGE_DEBUG_MSG((NULL, MOD_CTL, " _info status = 0x%X", status));
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs/*ARGSUSED*/
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs /* Get the supported interrupt types */
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs if ((ddi_status = ddi_intr_get_supported_types(hxgep->dip, &intr_types))
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs HXGE_ERROR_MSG((hxgep, HXGE_ERR_CTL, "<== hxge_add_intrs: "
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs "ddi_intr_get_supported_types failed: status 0x%08x",
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs * Pick the interrupt type to use MSIX, MSI, INTX hxge_msi_enable:
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs * (1): 1 - MSI
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs * (2): 2 - MSI-X
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs * others - FIXED
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs "==> hxge_add_intrs: "
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs "==> hxge_add_intrs: "
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs "==> hxge_add_intrs: "
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs "==> hxge_add_intrs: "
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs "==> hxge_add_intrs: "
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs if ((type == DDI_INTR_TYPE_MSIX || type == DDI_INTR_TYPE_MSI ||
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs if ((status = hxge_add_intrs_adv(hxgep)) != DDI_SUCCESS) {
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs " hxge_add_intrs: "
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs " hxge_add_intrs_adv failed: status 0x%08x",
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs "\nAdded advanced hxge add_intr_adv "
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs "==> hxge_add_intrs: failed to register interrupts"));
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs/*ARGSUSED*/
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs HXGE_DEBUG_MSG((hxgep, DDI_CTL, "==> hxge_add_soft_intrs"));
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs ddi_status = ddi_add_softintr(hxgep->dip, DDI_SOFTINT_LOW,
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs &hxgep->resched_id, NULL, NULL, hxge_reschedule, (caddr_t)hxgep);
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs HXGE_ERROR_MSG((hxgep, HXGE_ERR_CTL, "<== hxge_add_soft_intrs: "
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs HXGE_DEBUG_MSG((hxgep, DDI_CTL, "<== hxge_ddi_add_soft_intrs"));
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs/*ARGSUSED*/
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs HXGE_DEBUG_MSG((hxgep, INT_CTL, "==> hxge_add_intrs_adv"));
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs HXGE_DEBUG_MSG((hxgep, INT_CTL, "==> hxge_add_intrs_adv: type 0x%x",
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs HXGE_DEBUG_MSG((hxgep, INT_CTL, "<== hxge_add_intrs_adv"));
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs/*ARGSUSED*/
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qshxge_add_intrs_adv_type(p_hxge_t hxgep, uint32_t int_type)
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs HXGE_DEBUG_MSG((hxgep, INT_CTL, "==> hxge_add_intrs_adv_type"));
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs ddi_status = ddi_intr_get_nintrs(dip, int_type, &nintrs);
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs "ddi_intr_get_nintrs() failed, status: 0x%x%, "
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs ddi_status = ddi_intr_get_navail(dip, int_type, &navail);
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs "ddi_intr_get_navail() failed, status: 0x%x%, "
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs "ddi_intr_get_navail() returned: intr type %d nintrs %d, navail %d",
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs /* MSI must be power of 2 */
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs "ddi_intr_get_navail(): (msi power of 2) nintrs %d, "
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs "requesting: intr type %d nintrs %d, navail %d",
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs behavior = ((int_type == DDI_INTR_TYPE_FIXED) ? DDI_INTR_ALLOC_STRICT :
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs ddi_status = ddi_intr_alloc(dip, intrp->htable, int_type, inum,
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs "ddi_intr_alloc() returned: navail %d nactual %d",
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs /* Free already allocated interrupts */
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs for (y = 0; y < nactual; y++) {
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs "hxge_add_intrs_adv_typ:hxge_ldgv_init "
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs /* Free already allocated interrupts */
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs for (y = 0; y < nactual; y++) {
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs "After hxge_ldgv_init(): nreq %d nactual %d", nrequired, nactual));
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs "hxge_add_intrs_adv_type: arg1 0x%x arg2 0x%x: "
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs "1-1 int handler (entry %d)\n",
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs "hxge_add_intrs_adv_type: arg1 0x%x arg2 0x%x: "
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs "nldevs %d int handler (entry %d)\n",
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs "==> hxge_add_intrs_adv_type: ddi_add_intr(inum) #%d "
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs "==> hxge_add_intrs_adv_type: failed #%d "
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs /* Free already allocated intr */
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs for (y = 0; y < nactual; y++) {
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs "Requested: %d, Allowed: %d msi_intx_cnt %d intr_added %d",
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs navail, nactual, intrp->msi_intx_cnt, intrp->intr_added));
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs (void) ddi_intr_get_cap(intrp->htable[0], &intrp->intr_cap);
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs HXGE_DEBUG_MSG((hxgep, INT_CTL, "<== hxge_add_intrs_adv_type"));
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs/*ARGSUSED*/
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qshxge_add_intrs_adv_type_fix(p_hxge_t hxgep, uint32_t int_type)
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs HXGE_DEBUG_MSG((hxgep, INT_CTL, "==> hxge_add_intrs_adv_type_fix"));
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs ddi_status = ddi_intr_get_nintrs(dip, int_type, &nintrs);
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs "ddi_intr_get_nintrs() failed, status: 0x%x%, "
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs ddi_status = ddi_intr_get_navail(dip, int_type, &navail);
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs "ddi_intr_get_navail() failed, status: 0x%x%, "
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs "ddi_intr_get_navail() returned: nintrs %d, naavail %d",
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs behavior = ((int_type == DDI_INTR_TYPE_FIXED) ? DDI_INTR_ALLOC_STRICT :
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs ddi_status = ddi_intr_alloc(dip, intrp->htable, int_type, inum,
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs /* Free already allocated interrupts */
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs for (y = 0; y < nactual; y++) {
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs "hxge_add_intrs_adv_type_fix:hxge_ldgv_init "
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs /* Free already allocated interrupts */
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs for (y = 0; y < nactual; y++) {
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs "hxge_add_intrs_adv_type_fix: "
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs "1-1 int handler(%d) ldg %d ldv %d "
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs "arg1 $%p arg2 $%p\n",
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs "hxge_add_intrs_adv_type_fix: "
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs "shared ldv %d int handler(%d) ldv %d ldg %d"
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs "arg1 0x%016llx arg2 0x%016llx\n",
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs "==> hxge_add_intrs_adv_type_fix: failed #%d "
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs for (y = 0; y < nactual; y++) {
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs /* Free already allocated intr */
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs (void) ddi_intr_get_cap(intrp->htable[0], &intrp->intr_cap);
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs HXGE_DEBUG_MSG((hxgep, INT_CTL, "<== hxge_add_intrs_adv_type_fix"));
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs/*ARGSUSED*/
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qsstatic void
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs HXGE_DEBUG_MSG((hxgep, INT_CTL, "==> hxge_remove_intrs"));
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs "<== hxge_remove_intrs: interrupts not registered"));
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs HXGE_DEBUG_MSG((hxgep, INT_CTL, "==> hxge_remove_intrs:advanced"));
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs "hxge_remove_intrs: ddi_intr_free inum %d "
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs "msi_intx_cnt %d intr_added %d",
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs HXGE_DEBUG_MSG((hxgep, INT_CTL, "<== hxge_remove_intrs"));
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs/*ARGSUSED*/
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qsstatic void
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs HXGE_DEBUG_MSG((hxgep, INT_CTL, "==> hxge_remove_soft_intrs"));
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs "==> hxge_remove_soft_intrs: removed"));
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs HXGE_DEBUG_MSG((hxgep, INT_CTL, "<== hxge_remove_soft_intrs"));
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs/*ARGSUSED*/
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs HXGE_DEBUG_MSG((hxgep, INT_CTL, "==> hxge_intrs_enable"));
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs HXGE_ERROR_MSG((hxgep, HXGE_ERR_CTL, "<== hxge_intrs_enable: "
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs "interrupts are not registered"));
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs "<== hxge_intrs_enable: already enabled"));
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs "block enable - status 0x%x total inums #%d\n",
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs "ddi_intr_enable:enable - status 0x%x "
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs "total inums %d enable inum #%d\n",
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs HXGE_DEBUG_MSG((hxgep, INT_CTL, "<== hxge_intrs_enable"));
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs/*ARGSUSED*/
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qsstatic void
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs HXGE_DEBUG_MSG((hxgep, INT_CTL, "==> hxge_intrs_disable"));
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs HXGE_DEBUG_MSG((hxgep, INT_CTL, "<== hxge_intrs_disable: "
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs "interrupts are not registered"));
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs HXGE_DEBUG_MSG((hxgep, INT_CTL, "<== hxge_intrs_disable"));
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs HXGE_DEBUG_MSG((hxgep, DDI_CTL, "==> hxge_mac_register"));
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs "hxge_mac_register: ether addr is %x:%x:%x:%x:%x:%x",
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs sizeof (struct ether_header) - ETHERFCSL - 4 - TX_PKT_HEADER_SIZE;
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs if (status != 0) {
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs "hxge_mac_register failed (status %d instance %d)",
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs HXGE_DEBUG_MSG((hxgep, DDI_CTL, "<== hxge_mac_register success "
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs HXGE_DEBUG_MSG((hxgep, MOD_CTL, "==> hxge_init_common_dev"));
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs * Loop through existing per Hydra hardware list.
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs "==> hxge_init_common_dev: hw_p $%p parent dip $%p",
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs "==> hxge_init_common_device: "
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs "hw_p $%p parent dip $%p ndevs %d (found)",
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs "==> hxge_init_common_dev: parent dip $%p (new)", p_dip));
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs MUTEX_INIT(&hw_p->hxge_cfg_lock, NULL, MUTEX_DRIVER, NULL);
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs MUTEX_INIT(&hw_p->hxge_tcam_lock, NULL, MUTEX_DRIVER, NULL);
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs MUTEX_INIT(&hw_p->hxge_vlan_lock, NULL, MUTEX_DRIVER, NULL);
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs "==> hxge_init_common_dev (hxge_hw_list) $%p", hxge_hw_list));
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs HXGE_DEBUG_MSG((hxgep, MOD_CTL, "<== hxge_init_common_dev"));
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qsstatic void
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs HXGE_DEBUG_MSG((hxgep, MOD_CTL, "==> hxge_uninit_common_dev"));
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs "<== hxge_uninit_common_dev (no common)"));
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs "==> hxge_uninit_common_dev: "
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs "hw_p $%p parent dip $%p ndevs %d (found)",
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs "==> hxge_uninit_common_dev: "
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs "hw_p $%p parent dip $%p ndevs %d (last)",
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs "==> hxge_uninit_common_dev:"
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs "remove head "
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs "hw_p $%p parent dip $%p "
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs "ndevs %d (head)",
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs "==> hxge_uninit_common_dev:"
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs "remove middle "
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs "hw_p $%p parent dip $%p "
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs "ndevs %d (middle)",
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs "==> hxge_uninit_common_dev (hxge_hw_list) $%p", hxge_hw_list));
3dec9fcdd56adf1b4a563137b4915c8f2d83b881qs HXGE_DEBUG_MSG((hxgep, MOD_CTL, "<= hxge_uninit_common_dev"));