pciehpc.c revision 4eacc76344d8a749f63e6a7c1de72a44b79ead22
/*
* CDDL HEADER START
*
* The contents of this file are subject to the terms of the
* Common Development and Distribution License (the "License").
* You may not use this file except in compliance with the License.
*
* You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
* See the License for the specific language governing permissions
* and limitations under the License.
*
* When distributing Covered Code, include this CDDL HEADER in each
* file and include the License file at usr/src/OPENSOLARIS.LICENSE.
* If applicable, add the following below this CDDL HEADER, with the
* fields enclosed by brackets "[]" replaced with your own identifying
* information: Portions Copyright [yyyy] [name of copyright owner]
*
* CDDL HEADER END
*/
/*
* Copyright 2006 Sun Microsystems, Inc. All rights reserved.
* Use is subject to license terms.
*/
#pragma ident "%Z%%M% %I% %E% SMI"
/*
* PCIEHPC - The Standard PCI Express HotPlug Controller driver module. This
* driver can be used with PCI Express HotPlug controllers that
* are compatible with the PCI Express ver 1.0a specification.
*/
#include <sys/autoconf.h>
#include <sys/ddi_impldefs.h>
#if defined(__sparc)
#include <sys/pcie_impl.h>
#endif
/*
*/
/* mutex to protect pciehpc_head list */
static kmutex_t pciehpc_list_mutex;
/* pointer to linked list of pciehpc structures */
static kmutex_t pciehpc_init_mutex;
static int pciehpc_init_count = 0; /* count of pciehpc instances in use */
#if defined(__sparc)
#endif
#ifdef DEBUG
int pciehpc_debug = 0;
#endif
/*
* Module linkage information for the kernel.
*/
extern struct mod_ops mod_miscops;
{
"PCIe hotplug driver v%I%",
};
static struct modlinkage modlinkage =
{
&modlmisc,
};
int
_init(void)
{
int error;
}
return (error);
}
int
_fini(void)
{
int error;
if (pciehpc_init_count != 0) {
return (EBUSY);
}
if (error != 0) {
return (error);
}
return (0);
}
int
{
}
/*
* pciehpc_init()
*
* Initialize Hot Plug Controller if present. The arguments are:
* dip - Devinfo node pointer to the hot plug bus node
* regops - register ops to access HPC registers for non-standard
* HPC hw implementations (e.g: HPC in host PCI-E brdiges)
* This is NULL for standard HPC in PCIe bridges.
* Returns:
* DDI_SUCCESS for successful HPC initialization
* DDI_FAILURE for errors or if HPC hw not found
*/
int
{
(void *)dip));
/* Make sure that it is not already initialized */
"%s%d: pciehpc instance already initialized!",
return (DDI_SUCCESS);
}
/* allocate a new soft state structure */
/* get PCI device info */
/* setup access handle for HPC regs */
/* HPC access is non-standard; use the supplied reg ops */
} else {
/* standard HPC in a PCIe bridge */
goto cleanup;
}
/*
* Set the platform specific hot plug mode.
*/
#endif
/* make sure we really have a hot plug controller */
goto cleanup1;
}
/* initialize hot plug controller hw */
goto cleanup1;
/* initialize slot information soft state structure */
goto cleanup2;
/* register the hot plug slot with HPS framework */
goto cleanup3;
/* HPC initialization is complete now */
#ifdef DEBUG
/* For debug, dump the HPC registers */
if (pciehpc_debug > 2)
#endif
/* enable hot plug interrupts/event */
return (DDI_SUCCESS);
/* free up the HPC register mapping if applicable */
return (DDI_FAILURE);
}
/*
* Uninitialize HPC soft state structure and free up any resources
* used for the HPC instance.
*/
int
{
(void *)dip));
/* get the soft state structure for this dip */
return (DDI_FAILURE);
}
/* disable interrupts */
/* unregister the slot */
(void) pciehpc_unregister_slot(ctrl_p);
/* uninit any slot info data structures */
/* uninitialize hpc, remove interrupt handler, etc. */
/* free up the HPC register mapping if applicable */
/* destroy the soft state structure */
ASSERT(pciehpc_init_count != 0);
return (DDI_SUCCESS);
}
/*
* Probe for the inband PCI-E hot plug controller. Returns DDI_SUCCESS
* if found. This function works only for the standard PCI-E bridge
* that has inband hot plug controller.
*
* NOTE: This won't work for Host-PCIE bridges.
*/
int
{
/* Read the PCI configuration status register. */
/* check for capabilities list */
if (!(status & PCI_STAT_CAP)) {
/* no capabilities list */
return (DDI_FAILURE);
}
/* Get a pointer to the PCI capabilities list. */
/*
* Walk thru the capabilities list looking for PCI Express capability
* structure.
*/
while (cap_ptr != PCI_CAP_NEXT_PTR_NULL) {
if (cap_id == PCI_CAP_ID_PCI_E) {
/* Read the PCI Express Slot Capabilities Register */
/* Does it have PCI Express HotPlug capability? */
if (slot_cap & PCIE_SLOTCAP_HP_CAPABLE) {
/* Save the offset to PCI Express Capabilities structure */
return (DDI_SUCCESS);
}
}
/* Get the pointer to the next capability */
cap_ptr &= 0xFC;
}
return (DDI_FAILURE);
}
/*
* Setup slot information for use with HPS framework.
*/
int
{
/*
* setup HPS framework slot ops structure
*/
/*
* setup HPS framework slot information structure
*/
p->slot_info.slot_flags =
/* the device number is fixed as 0 as per the spec */
p->slot_info.pci_dev_num = 0;
/* read Slot Capabilities Register */
/* set slot-name/slot-number info */
/* check if Attn Button present */
/* check if Manual Retention Latch sensor present */
/*
* PCI-E version 1.1 defines EMI Lock Present bit
* in Slot Capabilities register. Check for it.
*/
if (ctrl_p->dll_active_rep)
/* initialize synchronization conditional variable */
/* setup thread for handling ATTN button events */
"pciehpc_slotinfo_init: setting up ATTN button event "
}
/* get current slot state from the hw */
return (DDI_SUCCESS);
}
/*ARGSUSED*/
int
{
"pciehpc_slotinfo_uninit: waiting for ATTN thread exit\n"));
"pciehpc_slotinfo_uninit: ATTN thread exit\n"));
}
if (ctrl_p->dll_active_rep)
return (DDI_SUCCESS);
}
/*
* Get the current state of the slot from the hw.
*/
void
{
/* read the Slot Control Register */
/* read the current Slot Status Register */
/* get POWER led state */
p->power_led_state =
/* get ATTN led state */
p->attn_led_state =
if (!(status & PCIE_SLOTSTS_PRESENCE_DETECTED))
/* no device present; slot is empty */
p->slot_state = HPC_SLOT_EMPTY;
else if (!(control & PCIE_SLOTCTL_PWR_CONTROL))
/* device is present and powered up */
p->slot_state = HPC_SLOT_CONNECTED;
else
/* device is present and powered down */
}
/*
* pciehpc_regs_setup()
*
* Setup PCI-E config registers for DDI access functions.
*
* Note: This is same as pci_config_setup() except that this may be
* used to map specific reg set with an offset in the case of host
* PCI-E bridges.
*/
int
{
/* Check for fault management capabilities */
}
/*
* pciehpc_regs_teardown()
*
* Unmap config register set.
*
* Note: This is same as pci_config_teardown() function.
*/
void
{
}
/*
* Find the soft state structure for the HPC associated with the dip.
*/
static pciehpc_t *
{
while (ctrl_p) {
return (ctrl_p);
}
}
return (NULL);
}
/*
* Allocate a soft state structure for the HPC associated with this dip.
*/
static pciehpc_t *
{
return (ctrl_p);
}
/*
* Remove the HPC soft state structure from the linked list.
*/
static void
{
pciehpc_t *p;
pp = &pciehpc_head;
break;
}
}
}
/*
* convert LED state from PCIE HPC definition to hpc_led_state_t
* definition.
*/
{
switch (state) {
return (HPC_LED_ON);
return (HPC_LED_BLINK);
default:
return (HPC_LED_OFF);
}
}
/*
* convert LED state from hpc_led_state_t definition to PCIE HPC
* definition.
*/
{
switch (state) {
case HPC_LED_ON:
return (PCIE_SLOTCTL_INDICATOR_STATE_ON);
case HPC_LED_BLINK:
return (PCIE_SLOTCTL_INDICATOR_STATE_BLINK);
case HPC_LED_OFF:
default:
return (PCIE_SLOTCTL_INDICATOR_STATE_OFF);
}
}
/*
* Initialize HPC hardware, install interrupt handler, etc. It doesn't
* enable hot plug interrupts.
*
* (Note: It is called only from pciehpc_init().)
*/
int
{
/* read the Slot Control Register */
/* disable all interrupts */
reg &= ~(SLOTCTL_SUPPORTED_INTRS_MASK);
PCIE_SLOTCTL, reg);
/* clear any interrupt status bits */
/* initialize the interrupt mutex */
(void *)PCIEHPC_INTR_PRI);
return (DDI_SUCCESS);
}
/*
* Uninitialize HPC hardware, uninstall interrupt handler, etc.
*
* (Note: It is called only from pciehpc_uninit().)
*/
int
{
/* disable interrupts */
(void) pciehpc_disable_intr(ctrl_p);
/* destroy the mutex */
return (DDI_SUCCESS);
}
/*
* Disable hot plug interrupts.
* Note: this is only for Native hot plug mode.
*/
int
{
/* read the Slot Control Register */
/* disable all interrupts */
reg &= ~(SLOTCTL_SUPPORTED_INTRS_MASK);
PCIE_SLOTCTL, reg);
/* clear any interrupt status bits */
return (DDI_SUCCESS);
}
/*
* Enable hot plug interrupts.
* Note: this is only for Native hot plug mode.
*/
int
{
/* clear any interrupt status bits */
/* read the Slot Control Register */
/*
* enable interrupts: power fault detection interrupt is enabled
* only when the slot is 'connected', i.e. power is ON
*/
else
return (DDI_SUCCESS);
}
/*
* Register the PCI-E hot plug slot with HPS framework.
*/
int
{
char nexus_path[MAXNAMELEN];
/* get nexus path name */
/* register the slot with HPS framework */
&p->slot_info, &p->slot_handle,
"pciehpc_register_slot() failed to register slot %d\n",
p->slotNum));
return (DDI_FAILURE);
}
"pciehpc_register_slot(): registered slot %d\n", p->slotNum));
return (DDI_SUCCESS);
}
/*
* Unregister the PCI-E hot plug slot from the HPS framework.
*/
int
{
if (hpc_slot_unregister(&p->slot_handle) != 0) {
"pciehpc_unregister_slot() failed to unregister slot %d\n",
p->slotNum));
return (DDI_FAILURE);
}
"pciehpc_unregister_slot(): unregistered slot %d\n", p->slotNum));
return (DDI_SUCCESS);
}
/*
* pciehpc_intr()
*
* Interrupt handler for PCI-E Hot plug controller interrupts.
*
* Note: This is only for native mode hot plug. This is called
* by the nexus driver at interrupt context. Interrupt Service Routine
* registration is done by the nexus driver for both hot plug and
* non-hot plug interrupts. This function is called from the ISR
* of the nexus driver to handle hot-plug interrupts.
*/
int
{
/* get the soft state structure for this dip */
return (DDI_INTR_UNCLAIMED);
/* make sure the controller soft state is initialized */
return (DDI_INTR_UNCLAIMED);
}
/* if it is not NATIVE hot plug mode then return */
return (DDI_INTR_UNCLAIMED);
}
/* read the current slot status register */
/* check if there are any hot plug interrupts occurred */
if (!(status & SLOT_STATUS_EVENTS)) {
/* no hot plug events occurred */
return (DDI_INTR_UNCLAIMED);
}
/* clear the interrupt status bits */
/* check for CMD COMPLETE interrupt */
if (status & PCIE_SLOTSTS_COMMAND_COMPLETED) {
"pciehpc_intr(): CMD COMPLETED interrupt received\n"));
/* wake up any one waiting for Command Completion event */
}
/* check for ATTN button interrupt */
if (status & PCIE_SLOTSTS_ATTN_BTN_PRESSED) {
"pciehpc_intr(): ATTN BUTTON interrupt received\n"));
/* if ATTN button event is still pending then cancel it */
else
/* wake up the ATTN event handler */
}
/* check for power fault interrupt */
if (status & PCIE_SLOTSTS_PWR_FAULT_DETECTED) {
"pciehpc_intr(): POWER FAULT interrupt received"
if (control & PCIE_SLOTCTL_PWR_FAULT_EN) {
/* disable power fault detction interrupt */
/* send the event to HPS framework */
}
}
/* check for MRL SENSOR CHANGED interrupt */
if (status & PCIE_SLOTSTS_MRL_SENSOR_CHANGED) {
"pciehpc_intr(): MRL SENSOR CHANGED interrupt received"
/* For now (phase-I), no action is taken on this event */
}
/* check for PRESENCE CHANGED interrupt */
if (status & PCIE_SLOTSTS_PRESENCE_CHANGED) {
"pciehpc_intr(): PRESENCE CHANGED interrupt received"
if (status & PCIE_SLOTSTS_PRESENCE_DETECTED) {
/* card is inserted into the slot */
/* send the event to HPS framework */
} else {
/* card is removed from the slot */
/* make sure to disable power fault detction interrupt */
if (control & PCIE_SLOTCTL_PWR_FAULT_EN)
/* send the event to HPS framework */
}
}
/* check for DLL state changed interrupt */
if (ctrl_p->dll_active_rep &&
"pciehpc_intr(): DLL STATE CHANGED interrupt received"
}
return (DDI_INTR_CLAIMED);
}
#ifdef DEBUG
/*
* Dump PCI-E Hot Plug registers.
*/
static void
{
}
static char *
{
switch (state) {
case HPC_LED_ON:
return ("on");
case HPC_LED_OFF:
return ("off");
case HPC_LED_BLINK:
default:
return ("blink");
}
}
#endif /* DEBUG */
/*
* pciehpc_slot_connect()
*
* Connect power to the PCI-E slot.
*
* Returns: HPC_SUCCESS if the slot is powered up and enabled.
* HPC_ERR_FAILED if the slot can't be enabled.
*
* (Note: This function is called by HPS framework at kernel context only.)
*/
/*ARGSUSED*/
int
{
/* get the current state of the slot */
/* check if the slot is already in the 'connected' state */
/* slot is already in the 'connected' state */
"pciehpc_slot_connect() slot %d already connected\n",
return (HPC_SUCCESS);
}
/* read the Slot Status Register */
/* make sure the MRL switch is closed if present */
/* MRL switch is open */
goto cleanup;
}
/* make sure the slot has a device present */
if (!(status & PCIE_SLOTSTS_PRESENCE_DETECTED)) {
/* slot is empty */
goto cleanup;
}
/* get the current state of Slot Control Register */
/* check if the slot's power state is ON */
if (!(control & PCIE_SLOTCTL_PWR_CONTROL)) {
/* slot is already powered up */
"pciehpc_slot_connect() slot %d already connected\n",
return (HPC_SUCCESS);
}
/*
* Enable power to the slot involves:
* 1. Set power LED to blink and ATTN led to OFF.
* 2. Set power control ON in Slot Control Reigster and
* wait for Command Completed Interrupt or 1 sec timeout.
* 3. If Data Link Layer State Changed events are supported
* then wait for the event to indicate Data Layer Link
* is active. The time out value for this event is 1 second.
* This is specified in PCI-E version 1.1.
* 4. Set power LED to be ON.
*/
/* 1. set power LED to blink & ATTN led to OFF */
/* 2. set power control to ON */
/* 3. wait for DLL State Change event, if it's supported */
if (ctrl_p->dll_active_rep) {
if (!(status & PCIE_LINKSTS_DLL_LINK_ACTIVE)) {
/* wait 1 sec for the DLL State Changed event */
ddi_get_lbolt() +
/* check Link status */
if (!(status & PCIE_LINKSTS_DLL_LINK_ACTIVE))
goto cleanup2;
}
/* wait 100ms after DLL_LINK_ACTIVE field reads 1b */
} else {
/* wait 1 sec for link to come up */
}
/* check power is really turned ON */
if (control & PCIE_SLOTCTL_PWR_CONTROL) {
"slot %d fails to turn on power on connect\n",
goto cleanup1;
}
/* enable power fault detection interrupt */
/* 4. Set power LED to be ON */
/* if EMI is present, turn it ON */
if (ctrl_p->has_emi_lock) {
if (!(status & PCIE_SLOTSTS_EMI_LOCK_SET)) {
/* wait 1 sec after toggling the state of EMI lock */
}
}
return (HPC_SUCCESS);
/* if power is ON, set power control to OFF */
if (!(control & PCIE_SLOTCTL_PWR_CONTROL)) {
}
/* set power led to OFF */
return (HPC_ERR_FAILED);
}
/*
* pciehpc_slot_disconnect()
*
* Disconnect power to the slot.
*
* Returns: HPC_SUCCESS if the slot is powered up and enabled.
* HPC_ERR_FAILED if the slot can't be enabled.
*
* (Note: This function is called by HPS framework at kernel context only.)
*/
/*ARGSUSED*/
int
{
/* get the current state of the slot */
/* check if the slot is already in the 'disconnected' state */
/* slot is in the 'disconnected' state */
"pciehpc_slot_disconnect(): slot %d already disconnected\n",
return (HPC_SUCCESS);
}
/* read the Slot Status Register */
/* make sure the slot has a device present */
if (!(status & PCIE_SLOTSTS_PRESENCE_DETECTED)) {
/* slot is empty */
"pciehpc_slot_disconnect(): slot %d is empty\n",
goto cleanup;
}
/*
* Disable power to the slot involves:
* 1. Set power LED to blink.
* 2. Set power control OFF in Slot Control Reigster and
* wait for Command Completed Interrupt or 1 sec timeout.
* 3. Set POWER led and ATTN led to be OFF.
*/
/* 1. set power LED to blink */
/* disable power fault detection interrupt */
/* 2. set power control to OFF */
#ifdef DEBUG
/* check for power control bit to be OFF */
#endif
/* 3. Set power LED to be OFF */
/* if EMI is present, turn it OFF */
if (ctrl_p->has_emi_lock) {
if (status & PCIE_SLOTSTS_EMI_LOCK_SET) {
/* wait 1 sec after toggling the state of EMI lock */
}
}
return (HPC_SUCCESS);
return (HPC_ERR_FAILED);
}
/*ARGSUSED*/
int
{
int ret = HPC_SUCCESS;
/* get the current slot state */
switch (request) {
case HPC_CTRL_GET_SLOT_STATE:
break;
case HPC_CTRL_GET_BOARD_TYPE:
else
break;
case HPC_CTRL_GET_LED_STATE:
case HPC_ATTN_LED:
break;
case HPC_POWER_LED:
break;
case HPC_FAULT_LED:
case HPC_ACTIVE_LED:
break;
default:
" unknown led state\n"));
break;
}
break;
case HPC_CTRL_SET_LED_STATE:
case HPC_ATTN_LED:
break;
case HPC_POWER_LED:
" LED control is not allowed on slot #%d\n",
break;
case HPC_FAULT_LED:
case HPC_ACTIVE_LED:
break;
default:
break;
}
break;
/* turn the ATTN led ON for configure failure */
/* if power to the slot is still on then set Power led to ON */
break;
/* if power to the slot is still on then set Power led to ON */
break;
case HPC_CTRL_ENABLE_AUTOCFG:
case HPC_CTRL_DISABLE_AUTOCFG:
/* no action is needed here */
break;
case HPC_CTRL_DISABLE_SLOT:
case HPC_CTRL_ENABLE_SLOT:
/* no action is needed here */
break;
/* no action is needed here */
break;
case HPC_CTRL_DEV_CONFIGURED:
/* no action is needed here */
if (request == HPC_CTRL_DEV_CONFIGURED) {
/*EMPTY*/
}
break;
default:
"pciehpc_slot_control: unsupported operation\n"));
}
return (ret);
}
/*
* Get the state of an LED.
*/
{
/* get the current state of Slot Control register */
switch (led) {
case HPC_POWER_LED:
break;
case HPC_ATTN_LED:
break;
default:
"pciehpc_get_led_state() invalid LED %d\n", led));
return (HPC_LED_OFF);
}
switch (state) {
return (HPC_LED_ON);
return (HPC_LED_BLINK);
default:
return (HPC_LED_OFF);
}
}
/*
* Set the state of an LED. It updates both hw and sw state.
*/
void
{
/* get the current state of Slot Control register */
switch (led) {
case HPC_POWER_LED:
/* clear led mask */
break;
case HPC_ATTN_LED:
/* clear led mask */
break;
default:
"pciehpc_set_led_state() invalid LED %d\n", led));
return;
}
switch (state) {
case HPC_LED_ON:
if (led == HPC_POWER_LED)
else if (led == HPC_ATTN_LED)
break;
case HPC_LED_OFF:
if (led == HPC_POWER_LED)
else if (led == HPC_ATTN_LED)
break;
case HPC_LED_BLINK:
if (led == HPC_POWER_LED)
else if (led == HPC_ATTN_LED)
break;
default:
"pciehpc_set_led_state() invalid LED state %d\n", state));
return;
}
/* update the Slot Control Register */
#ifdef DEBUG
/* get the current state of Slot Control register */
"slot %d power-led %s attn-led %s\n",
#endif
}
/*
* Send a command to the PCI-E Hot Plug Controller.
*
* NOTES: The PCI-E spec defines the following semantics for issuing hot plug
* commands.
* 1) If Command Complete events/interrupts are supported then software
* waits for Command Complete event after issuing a command (i.e writing
* to the Slot Control register). The command completion could take as
* long as 1 second so software should be prepared to wait for 1 second
* before issuing another command.
*
* 2) If Command Complete events/interrupts are not supported then
* software could issue multiple Slot Control writes without any delay
* between writes.
*/
void
{
/*
* PCI-E version 1.1 spec defines No Command Completed
* Support bit (bit#18) in Slot Capabilities register. If this
* bit is set then slot doesn't support notification of command
* completion events.
*/
/*
* If no Command Completion event is supported or it is ACPI
* hot plug mode then just issue the command and return.
*/
if ((slot_cap & PCIE_SLOTCAP_NO_CMD_COMP_SUPP) ||
return;
}
/*
* **************************************
* Command Complete events are supported.
* **************************************
*/
/*
* If HPC is not yet initialized then just poll for the Command
* Completion interrupt.
*/
int retry = PCIEHPC_CMD_WAIT_RETRY;
/* write the command to the HPC */
control);
/* poll for status completion */
while (retry--) {
/* wait for 10 msec before checking the status */
if (status & PCIE_SLOTSTS_COMMAND_COMPLETED) {
/* clear the status bits */
status);
break;
}
}
return;
}
/* HPC is already initialized */
/*
* If previous command is still pending then wait for its
* completion. i.e cv_wait()
*/
/*
* Issue the command and wait for Command Completion or
* the 1 sec timeout.
*/
/* it is a timeout */
"pciehpc_issue_hpc_command: Command Complete"
" interrupt is not received for slot %d\n",
/* clear the status info in case interrupts are disabled? */
if (status & PCIE_SLOTSTS_COMMAND_COMPLETED) {
/* clear the status bits */
status);
}
}
/* wake up any one waiting for issuing another command to HPC */
}
/*
* pciehcp_attn_btn_handler()
*
* This handles ATTN button pressed event as per the PCI-E 1.1 spec.
*/
static void
{
"pciehpc_attn_btn_handler");
/* wait for ATTN button event */
/* get the current state of power LED */
/* Blink the Power LED while we wait for 5 seconds */
/* wait for 5 seconds before taking any action */
/*
* It is a time out; make sure the ATTN pending flag is
* still ON before sending the event to HPS framework.
*/
/* send the ATTN button event to HPS framework */
(void) hpc_slot_event_notify(
}
}
/* restore the power LED state */
continue;
}
/* wait for another ATTN button event */
}
thread_exit();
}
/*
*/
{
else
}
{
else
}
{
else
}
void
{
else
}
void
{
else
}
void
{
else
}
static void
{
int reglen;
/*
* Check if it is a PCIe fabric hotplug nexus. This is specially
* not so for Rootcomplex nodes supporting PCIe hotplug.
* We save this information so as to implement hardening for
* fabric nodes only via pcie services.
*/
/* Get the device number. */
return;
}
}
/*
* setup slot name/slot-number info.
*/
void
{
int *slotnum;
int len;
int invalid_slotnum = 0;
} else {
}
if (!p->slotNum) { /* platform may not have initialized it */
invalid_slotnum = 1;
}
/*
* construct the slot_name:
* if "slot-names" property exists then use that name
* else if valid slot number exists then it is "pcie<slot-num>".
* else it will be "pcie<sec-bus-number>dev0"
*/
&len) == DDI_PROP_SUCCESS) {
/*
* Note: for PCI-E slots, the device number is always 0 so the
* first (and only) string is the slot name for this slot.
*/
(char *)slotname_data + 4);
} else {
if (invalid_slotnum) /* use device number ie. 0 */
else
p->slotNum);
}
}
/*ARGSUSED*/
static int
{
/* get parent device's device_type property */
char *device_type;
int rc;
!= DDI_PROP_SUCCESS) {
return (DDI_FAILURE);
}
rc = DDI_FAILURE;
rc = DDI_SUCCESS;
return (rc);
}
#if defined(__sparc)
static void
{
}
}
static void
{
}
}
#endif