oce_intr.c revision 4d0e50075058332ce0cd62bc2669a8a4dea45da0
/*
* CDDL HEADER START
*
* The contents of this file are subject to the terms of the
* Common Development and Distribution License (the "License").
* You may not use this file except in compliance with the License.
*
* You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
* See the License for the specific language governing permissions
* and limitations under the License.
*
* When distributing Covered Code, include this CDDL HEADER in each
* file and include the License file at usr/src/OPENSOLARIS.LICENSE.
* If applicable, add the following below this CDDL HEADER, with the
* fields enclosed by brackets "[]" replaced with your own identifying
* information: Portions Copyright [yyyy] [name of copyright owner]
*
* CDDL HEADER END
*/
/*
* Copyright 2009 Emulex. All rights reserved.
* Use is subject to license terms.
*/
/*
* Source file interrupt registration
* and related helper functions
*/
#include <oce_impl.h>
/*
* top level function to setup interrupts
*
* dev - software handle to the device
*
* return DDI_SUCCESS => success, failure otherwise
*/
int
{
int ret;
if (ret == 0)
return (ret);
}
if (ret == 0)
return (ret);
}
return (DDI_FAILURE);
}
/*
* top level function to undo initialization in oce_setup_intr
*
* dev - software handle to the device
*
* return DDI_SUCCESS => success, failure otherwise
*/
int
{
return (oce_teardown_msix(dev));
}
return (oce_teardown_intx(dev));
}
return (DDI_FAILURE);
}
/*
* helper function to add ISR based on interrupt type
*
* dev - software handle to the device
*
* return DDI_SUCCESS => success, failure otherwise
*/
int
{
return (oce_add_msix_handlers(dev));
}
return (oce_add_intx_handlers(dev));
}
return (DDI_FAILURE);
}
/*
* helper function to remove ISRs added in oce_setup_handlers
*
* dev - software handle to the device
*
* return DDI_SUCCESS => success, failure otherwise
*/
void
{
}
}
}
void
{
reg |= HOSTINTR_MASK;
}
/*
* function to enable interrupts
*
* dev - software handle to the device
*
* return DDI_SUCCESS => success, failure otherwise
*/
void
{
int i;
int ret;
} else {
for (i = 0; i < dev->num_vectors; i++) {
if (ret != DDI_SUCCESS) {
for (i--; i >= 0; i--) {
}
}
}
}
} /* oce_ei */
void
{
reg &= ~HOSTINTR_MASK;
}
/*
* function to disable interrupts
*
* dev - software handle to the device
*
* return DDI_SUCCESS => success, failure otherwise
*/
void
{
int i;
int ret;
} else {
for (i = 0; i < dev->num_vectors; i++) {
if (ret != DDI_SUCCESS) {
"Failed to disable interrupts 0x%x", ret);
}
}
}
} /* oce_di */
/*
* function to setup the MSIX vectors
*
* dev - software handle to the device
*
* return 0=>success, failure otherwise
*/
static int
{
int navail = 0;
int ret = 0;
if (ret != DDI_SUCCESS) {
"Could not get nintrs:0x%x %d",
return (DDI_FAILURE);
}
/* get the number of vectors available */
if (ret != DDI_SUCCESS) {
"Could not get msix vectors:0x%x",
navail);
return (DDI_FAILURE);
}
if (navail < OCE_NUM_USED_VECTORS)
return (DDI_FAILURE);
/* allocate htable */
sizeof (ddi_intr_handle_t), KM_SLEEP);
/* allocate interrupt handlers */
"Alloc intr failed: %d %d",
return (DDI_FAILURE);
}
/* update the actual number of interrupts allocated */
/*
* get the interrupt priority. Assumption is that all handlers have
* equal priority
*/
if (ret != DDI_SUCCESS) {
int i;
"Unable to get intr priority: 0x%x",
for (i = 0; i < dev->num_vectors; i++) {
}
return (DDI_FAILURE);
}
return (DDI_SUCCESS);
} /* oce_setup_msix */
/*
* helper function to teardown MSIX interrupts
*
* dev - software handle to the device
*
* return 0 => success, failure otherwise
*/
static int
{
int i;
/* release handlers */
for (i = 0; i < dev->num_vectors; i++) {
}
/* release htable */
return (DDI_SUCCESS);
} /* oce_teardown_msix */
/*
* function to add MSIX handlers to vectors
*
* dev - software handle to the device
*
* return DDI_SUCCESS => success, failure otherwise
*/
static int
{
int ret;
int i;
return (DDI_FAILURE);
}
if (ret != DDI_SUCCESS) {
"Failed to add interrupt handlers");
for (i--; i >= 0; i--) {
}
return (DDI_FAILURE);
}
}
return (DDI_SUCCESS);
} /* oce_add_msix_handlers */
/*
* function to disassociate msix handlers added in oce_add_msix_handlers
*
* dev - software handle to the device
*
* return DDI_SUCCESS => success, failure otherwise
*/
static void
{
int nvec;
}
} /* oce_del_msix_handlers */
/*
* command interrupt handler routine added to all vectors
*
* arg1 = callback data
* arg2 - callback data
*
* return DDI_INTR_CLAIMED => interrupt was claimed by the ISR
*/
static uint_t
{
return (DDI_INTR_UNCLAIMED);
}
/* If device is getting suspended or closing, then return */
return (DDI_INTR_UNCLAIMED);
}
/* if not CQ then continue else flag an error */
"NOT a CQ event. 0x%x",
}
/* get the cq from the eqe */
/* Call the completion handler */
/* clear valid bit and progress eqe */
num_eqe++;
} /* for all EQEs */
/* ring the eq doorbell, signify that it's done processing */
if (num_eqe > 0) {
return (DDI_INTR_CLAIMED);
} else {
return (DDI_INTR_UNCLAIMED);
}
} /* oce_msix_handler */
static int
{
int navail = 0;
int nintr = 0;
int ret = 0;
if (ret != DDI_SUCCESS) {
"could not get nintrs:0x%x %d",
return (DDI_FAILURE);
}
/* get the number of vectors available */
if (ret != DDI_SUCCESS) {
"could not get intx vectors:0x%x",
navail);
return (DDI_FAILURE);
}
/* always 1 */
return (DDI_FAILURE);
/* allocate htable */
/* allocate interrupt handlers */
"alloc intr failed: %d %d",
return (DDI_FAILURE);
}
/* update the actual number of interrupts allocated */
/*
* get the interrupt priority. Assumption is that all handlers have
* equal priority
*/
if (ret != DDI_SUCCESS) {
int i;
"Unable to get intr priority: 0x%x",
for (i = 0; i < dev->num_vectors; i++) {
}
return (DDI_FAILURE);
}
return (DDI_SUCCESS);
} /* oce_setup_intx */
static int
{
/* release handlers */
/* release htable */
return (DDI_FAILURE);
} /* oce_teardown_intx */
static int
{
int ret;
if (ret != DDI_SUCCESS) {
"failed to add intr handlers");
return (DDI_FAILURE);
}
return (DDI_SUCCESS);
} /* oce_add_intx_handlers */
static void
{
} /* oce_del_intx_handlers */