oce_hw.c revision 5b9d3151a4426af9ad6ef2c2a178f13476b884b3
/*
* CDDL HEADER START
*
* The contents of this file are subject to the terms of the
* Common Development and Distribution License (the "License").
* You may not use this file except in compliance with the License.
*
* You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
* See the License for the specific language governing permissions
* and limitations under the License.
*
* When distributing Covered Code, include this CDDL HEADER in each
* file and include the License file at usr/src/OPENSOLARIS.LICENSE.
* If applicable, add the following below this CDDL HEADER, with the
* fields enclosed by brackets "[]" replaced with your own identifying
* information: Portions Copyright [yyyy] [name of copyright owner]
*
* CDDL HEADER END
*/
/*
* Copyright 2010 Emulex. All rights reserved.
* Use is subject to license terms.
*/
/*
* Source file containing the implementation of the Hardware specific
* functions
*/
#include <oce_impl.h>
#include <oce_stat.h>
#include <oce_ioctl.h>
static ddi_device_acc_attr_t reg_accattr = {
};
static int
{
int ret = 0;
/* get number of supported bars */
if (ret != DDI_SUCCESS) {
"%d: could not retrieve num_bars", MOD_CONFIG);
return (DDI_FAILURE);
}
/* verify each bar and map it accordingly */
/* PCI CFG */
if (ret != DDI_SUCCESS) {
"Could not get sizeof BAR %d",
return (DDI_FAILURE);
}
if (ret != DDI_SUCCESS) {
"Could not map bar %d",
return (DDI_FAILURE);
}
/* CSR */
if (ret != DDI_SUCCESS) {
"Could not get sizeof BAR %d",
return (DDI_FAILURE);
}
if (ret != DDI_SUCCESS) {
"Could not map bar %d",
return (DDI_FAILURE);
}
/* Doorbells */
if (ret != DDI_SUCCESS) {
"%d Could not get sizeof BAR %d",
return (DDI_FAILURE);
}
if (ret != DDI_SUCCESS) {
"Could not map bar %d", OCE_PCI_DB_BAR);
return (DDI_FAILURE);
}
return (DDI_SUCCESS);
}
static void
{
}
/*
* function to map the device memory
*
* dev - handle to device private data structure
*
*/
int
{
int ret = 0;
if (ret != DDI_SUCCESS) {
return (DDI_FAILURE);
}
if (ret != DDI_SUCCESS) {
return (DDI_FAILURE);
}
}
return (DDI_FAILURE);
}
return (DDI_SUCCESS);
} /* oce_pci_init */
/*
* function to free device memory mapping mapped using
* oce_pci_init
*
* dev - handle to device private data
*/
void
{
} /* oce_pci_fini */
/*
* function to check if a reset is required
*
* dev - software handle to the device
*
*/
{
post_status.dw0 = 0;
return (B_FALSE);
}
return (B_TRUE);
} /* oce_is_reset_pci */
/*
* function to do a soft reset on the device
*
* dev - software handle to the device
*
*/
int
{
/* struct mpu_ep_control ep_control; */
/* struct pcicfg_online1 online1; */
/* issue soft reset */
/* wait till soft reset bit deasserts */
do {
tmo = 0;
break;
}
drv_usecwait(100);
"0x%x soft_reset"
"bit asserted[1]. Reset failed",
return (DDI_FAILURE);
}
} /* oce_pci_soft_reset */
/*
* function to trigger a POST on the device
*
* dev - software handle to the device
*
*/
int
{
/* read semaphore CSR */
return (DDI_FAILURE);
}
/* if host is ready then wait for fw ready else send POST */
DDI_FM_OK) {
return (DDI_FAILURE);
}
}
/* wait for FW ready */
for (;;) {
tmo = 0;
break;
}
DDI_FM_OK) {
return (DDI_FAILURE);
}
return (DDI_FAILURE);
}
return (DDI_SUCCESS);
drv_usecwait(100);
}
return (DDI_FAILURE);
} /* oce_POST */
/*
* function to modify register access attributes corresponding to the
* FM capabilities configured by the user
*
* fm_caps - fm capability configured by the user and accepted by the driver
*/
void
{
if (fm_caps == DDI_FM_NOT_CAPABLE) {
return;
}
if (DDI_FM_ACC_ERR_CAP(fm_caps)) {
} else {
}
} /* oce_set_fma_flags */
int
{
int ret;
if (dev->rss_enable) {
}
/* create an interface for the device with out mac */
if (ret != 0) {
"Interface creation failed: 0x%x", ret);
return (ret);
}
/* Enable VLAN Promisc on HW */
if (ret != 0) {
"Config vlan failed: %d", ret);
return (ret);
}
/* set default flow control */
if (ret != 0) {
"Set flow control failed: %d", ret);
}
if (ret != 0) {
"Set Promisc failed: %d", ret);
}
return (0);
}
void
/* currently only single interface is implmeneted */
}
}
static void
{
int i;
/* fill the indirection table rq 0 is default queue */
for (i = 0; i < OCE_ITBL_SIZE; i++) {
}
}
int
{
int ret;
char itbl[OCE_ITBL_SIZE];
char hkey[OCE_HKEY_SIZE];
/* disable the interrupts here and enable in start */
if (ret != DDI_SUCCESS) {
return (DDI_FAILURE);
}
if (ret != DDI_SUCCESS) {
return (DDI_FAILURE);
}
if (dev->rss_enable) {
if (ret != DDI_SUCCESS) {
"Failed to Configure RSS");
return (ret);
}
}
if (ret != DDI_SUCCESS) {
"Failed to Setup handlers");
return (ret);
}
return (DDI_SUCCESS);
}
void
{
if (dev->rss_enable) {
char itbl[OCE_ITBL_SIZE] = {0};
char hkey[OCE_HKEY_SIZE] = {0};
int ret = 0;
if (ret != DDI_SUCCESS) {
"Failed to Disable RSS");
}
}
}
int
{
int ret;
struct mac_address_format mac_addr;
if (ret != DDI_SUCCESS) {
"!!!HW POST1 FAILED");
/* ADD FM FAULT */
return (DDI_FAILURE);
}
/* create bootstrap mailbox */
"Failed to allocate bmbx: size = %u",
return (DDI_FAILURE);
}
if (ret != 0) {
"!!!FUNCTION RESET FAILED");
goto init_fail;
}
/* reset the Endianess of BMBX */
if (ret != 0) {
"Mailbox initialization2 Failed with %d", ret);
goto init_fail;
}
/* read the firmware version */
if (ret != 0) {
"Firmaware version read failed with %d", ret);
goto init_fail;
}
/* read the fw config */
if (ret != 0) {
"Firmware configuration read failed with %d", ret);
goto init_fail;
}
/* read the Factory MAC address */
if (ret != 0) {
"MAC address read failed with %d", ret);
goto init_fail;
}
return (DDI_SUCCESS);
return (DDI_FAILURE);
}
void
{
}
}