oce_hw.c revision 4d0e50075058332ce0cd62bc2669a8a4dea45da0
/*
* CDDL HEADER START
*
* The contents of this file are subject to the terms of the
* Common Development and Distribution License (the "License").
* You may not use this file except in compliance with the License.
*
* You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
* See the License for the specific language governing permissions
* and limitations under the License.
*
* When distributing Covered Code, include this CDDL HEADER in each
* file and include the License file at usr/src/OPENSOLARIS.LICENSE.
* If applicable, add the following below this CDDL HEADER, with the
* fields enclosed by brackets "[]" replaced with your own identifying
* information: Portions Copyright [yyyy] [name of copyright owner]
*
* CDDL HEADER END
*/
/*
* Copyright 2009 Emulex. All rights reserved.
* Use is subject to license terms.
*/
/*
* Source file containing the implementation of the Hardware specific
* functions
*/
#include <oce_impl.h>
#include <oce_stat.h>
#include <oce_ioctl.h>
static ddi_device_acc_attr_t reg_accattr = {
};
/*
* function to map the device memory
*
* dev - handle to device private data structure
*
*/
int
{
int ret = 0;
/* get number of supported bars */
if (ret != DDI_SUCCESS) {
"%d: could not retrieve num_bars", MOD_CONFIG);
return (DDI_FAILURE);
}
/* verify each bar and map it accordingly */
/* PCI CFG */
if (ret != DDI_SUCCESS) {
"Could not get sizeof BAR %d",
return (DDI_FAILURE);
}
if (ret != DDI_SUCCESS) {
"Could not map bar %d",
return (DDI_FAILURE);
}
/* CSR */
if (ret != DDI_SUCCESS) {
"Could not get sizeof BAR %d",
return (DDI_FAILURE);
}
if (ret != DDI_SUCCESS) {
"Could not map bar %d",
return (DDI_FAILURE);
}
/* Doorbells */
if (ret != DDI_SUCCESS) {
"%d Could not get sizeof BAR %d",
return (DDI_FAILURE);
}
if (ret != DDI_SUCCESS) {
"Could not map bar %d", OCE_PCI_DB_BAR);
return (DDI_FAILURE);
}
return (DDI_FAILURE);
}
return (DDI_SUCCESS);
} /* oce_pci_init */
/*
* function to free device memory mapping mapped using
* oce_pci_init
*
* dev - handle to device private data
*/
void
{
} /* oce_pci_fini */
/*
* function to initailise the hardware. This includes creation of queues,
* interfaces and associated buffers for data movement
*
* dev - software handle to the device
*
*/
int
{
int ret = DDI_SUCCESS;
/* create an interface for the device with out mac */
if (ret != 0) {
"Interface creation failed: 0x%x", ret);
goto init_fail;
}
/* Enable VLAN Promisc on HW */
if (ret != 0) {
"Config vlan failed: %d", ret);
goto init_fail;
}
/* set default flow control */
if (ret != 0) {
"Set flow control failed: %d", ret);
}
/* set to promiscuous mode */
if (ret != 0) {
"Set Promisc failed: %d", ret);
}
/* this could happen if the driver is resuming after suspend */
if (ret != 0) {
"Set Multicast failed: %d", ret);
}
}
/* we are done. Now return */
return (DDI_SUCCESS);
return (DDI_FAILURE);
} /* oce_hw_init */
/*
* function to return resources allocated in oce_hw_init
*
* dev - software handle to the device
*
*/
void
{
int i;
/* release OS resources */
}
}
for (i = 0; i < dev->num_vectors; i++) {
"eq[%d] del failed", i);
}
}
}
}
}
} /* oce_hw_fini */
int
{
int i = 0;
/*
* create Event Queues. One event queue per available vector. In
* case of INTX, only one vector is available and will handle
* event notification for Write Queue (WQ), Receive Queue (RQ) and
* Mbox Queue (MQ).
*
* The EQ is not directly used by the WQ, RQ and MQ. The WQ, RQ and
* MQ is composed of a Completion Queue (CQ) that is created per
* queue and is dependent on the queue type. The EQ passed is
* associated with the CQ at the time of creation.
*
* In the case of MSIX, there will be one EQ for the RQ and one EQ
* shared between the WQ and MQ.
*/
for (i = 0; i < dev->num_vectors; i++) {
"EQ creation(%d) failed ", i);
goto chip_fail;
}
/* Save the eq pointer */
}
/*
* create the Write Queue (WQ). The WQ is the low level sructure for
* queueing send packets. It maintains a ring buffer to queue packets
* to be sent out on the wire and return the context to the host
* when there is a send complete event.
*
* The WQ uses a Completion Queue (CQ) with an associated EQ for
* handling send completion events.
*/
"WQ creation failed ");
goto chip_fail;
}
/* store the WQ pointer */
/*
* create the Receive Queue (RQ). The RQ is the low level structure
* for receiving data from the wire, It implements a ring buffer
* that allows the adpater to DMA data onto host buffers.
*
* The RQ uses a Completion Queue (CQ) with an associated EQ for
* handling recieve events when packets are received by the adapter
*/
"RQ creation failed ");
goto chip_fail;
}
/*
* create the Mailbox Queue (MQ). Only one per adapter instance can
* be created. The MQ is used for receiving asynchronous adapter
* events, like link status updates.
*
* The MQ uses an Asynchronous CQ (ACQ) with an associated EQ for
* handling asynchronous event notification to the host.
*/
"MQ creation failed ");
goto chip_fail;
}
return (DDI_SUCCESS);
return (DDI_FAILURE);
} /* oce_chip_hw_init */
void
{
struct mbx_destroy_common_mq *mq_cmd;
struct mbx_delete_nic_rq *rq_cmd;
struct mbx_delete_nic_wq *wq_cmd;
struct mbx_destroy_common_cq *cq_cmd;
struct mbx_destroy_common_eq *eq_cmd;
int i;
/* send a command to delete the MQ */
sizeof (struct mbx_destroy_common_cq), QTYPE_MQ);
/* send a command to delete the MQ_CQ */
sizeof (struct mbx_destroy_common_cq), QTYPE_CQ);
}
/* send a command to delete the RQ */
sizeof (struct mbx_delete_nic_rq), QTYPE_RQ);
/* send a command to delete the RQ_CQ */
sizeof (struct mbx_destroy_common_cq), QTYPE_CQ);
}
/* send a command to delete the WQ */
/* now fill the command */
sizeof (struct mbx_delete_nic_wq), QTYPE_WQ);
/* send a command to delete the WQ_CQ */
sizeof (struct mbx_destroy_common_cq), QTYPE_CQ);
}
for (i = 0; i < dev->num_vectors; i++) {
/* send a command to delete the EQ */
sizeof (struct mbx_destroy_common_eq), QTYPE_EQ);
}
}
}
/*
* function to check if a reset is required
*
* dev - software handle to the device
*
*/
{
post_status.dw0 = 0;
return (B_FALSE);
return (B_TRUE);
}
return (B_TRUE);
} /* oce_is_reset_pci */
/*
* function to do a soft reset on the device
*
* dev - software handle to the device
*
*/
int
{
/* struct mpu_ep_control ep_control; */
/* struct pcicfg_online1 online1; */
/* issue soft reset */
/* wait till soft reset bit deasserts */
do {
tmo = 0;
break;
}
drv_usecwait(100);
"0x%x soft_reset"
"bit asserted[1]. Reset failed",
return (DDI_FAILURE);
}
} /* oce_pci_soft_reset */
/*
* function to trigger a POST on the device
*
* dev - software handle to the device
*
*/
int
{
/* read semaphore CSR */
/* if host is ready then wait for fw ready else send POST */
}
/* wait for FW ready */
for (;;) {
tmo = 0;
break;
}
break;
drv_usecwait(100);
}
return (DDI_FAILURE);
"0x%x POST SUCCESSFUL",
return (DDI_SUCCESS);
} else {
return (DDI_FAILURE);
}
} /* oce_POST */
/*
* function to modify register access attributes corresponding to the
* FM capabilities configured by the user
*
* fm_caps - fm capability configured by the user and accepted by the driver
*/
void
{
if (fm_caps == DDI_FM_NOT_CAPABLE) {
return;
}
if (DDI_FM_ACC_ERR_CAP(fm_caps)) {
} else {
}
} /* oce_set_fma_flags */