/*
* Copyright (c) 2010 Steven Stallion. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are
* met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above
* copyright notice, this list of conditions and the following
* disclaimer in the documentation and/or other materials provided * with the distribution.
* 3. Neither the name of the copyright owner nor the names of any
* contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
* CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
* PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
extern "C" {
#endif
/*
*/
#
define CSR_INTSTAT 0x04 /* Interrupt Status Register */#
define CSR_GENCTL 0x0C /* General Control Register */#
define CSR_NVCTL 0x10 /* Non-volatile Control Register */#
define CSR_EECTL 0x14 /* EEPROM Control Register */#
define CSR_PBLCNT 0x18 /* Programmable Burst Length Counter */#
define CSR_TEST 0x1C /* Test Register */#
define CSR_ALICNT 0x24 /* Frame Alignment Error Counter */#
define CSR_MPCNT 0x28 /* Missed Packet Counter */#
define CSR_RXFIFO 0x2C /* Receive FIFO Contents */#
define CSR_MMCTL 0x30 /* MII Control Register */#
define CSR_MMDATA 0x34 /* MII Interface Register */#
define CSR_MMCFG 0x38 /* MII Configuration Register */#
define CSR_IPG 0x3C /* Interpacket Gap Register */#
define CSR_LAN0 0x40 /* LAN Address Register 0 */#
define CSR_LAN1 0x44 /* LAN Address Register 1 */#
define CSR_LAN2 0x48 /* LAN Address Register 2 */#
define CSR_MC0 0x50 /* Multicast Address Register 0 */#
define CSR_MC1 0x54 /* Multicast Address Register 1 */#
define CSR_MC2 0x58 /* Multicast Address Register 2 */#
define CSR_MC3 0x5C /* Multicast Address Register 3 */#
define CSR_RXCON 0x60 /* Receive Control Register */#
define CSR_RXSTAT 0x64 /* Receive Status Register */#
define CSR_RXCNT 0x68 /* Receive Byte Count */#
define CSR_TXCON 0x70 /* Transmit Control Register */#
define CSR_TXSTAT 0x74 /* Transmit Status Register */#
define CSR_TDPAR 0x78 /* Transmit Packet Address */#
define CSR_PRFDAR 0x80 /* PCI Receive First Descriptor Address */#
define CSR_PRCDAR 0x84 /* PCI Receive Current Descriptor Address */#
define CSR_PRHDAR 0x88 /* PCI Receive Host Data Address */#
define CSR_PRFLAR 0x8C /* PCI Receive Fragment List Address */#
define CSR_PRFCNT 0x94 /* PCI Receive Fragment Count */#
define CSR_PRLCAR 0x98 /* PCI Receive RAM Current Address */#
define CSR_PRLPAR 0x9C /* PCI Receive RAM Packet Address */#
define CSR_PREFAR 0xA0 /* PCI Receive End of Frame Address */#
define CSR_PRSTAT 0xA4 /* PCI Receive DMA Status Register */#
define CSR_PRBUF 0xA8 /* Receive RAM Buffer */#
define CSR_RDNCAR 0xAC /* Receive MTU Current Address */#
define CSR_PRCPTHR 0xB0 /* PCI Receive Copy Threshold Register */#
define CSR_PTFDAR 0xC0 /* PCI Transmit First Descriptor Address */#
define CSR_PTCDAR 0xC4 /* PCI Transmit Current Descriptor Address */#
define CSR_PTHDAR 0xC8 /* PCI Transmit Host Data Address */#
define CSR_PTFLAR 0xCC /* PCI Transmit Fragment List Address */#
define CSR_PTFCNT 0xD4 /* PCI Transmit Fragment Count */#
define CSR_PTLCAR 0xD8 /* PCI Transmit RAM Current Address */#
define CSR_ETXTHR 0xDC /* PCI Early Transmit Threshold Register */#
define CSR_PTETXC 0xE0 /* PCI Early Transmit Count */#
define CSR_PTSTAT 0xE4 /* PCI Transmit DMA Status */#
define CSR_PTBUF 0xE8 /* Transmit RAM Buffer */#
define CSR_PTFDAR2 0xEC /* PCI Transmit 2 First Descriptor Address */#
define CSR_FEVTR 0xF0 /* CardBus (UNUSED) */
/*
* Register fields.
*/
#
define INTSTAT_RCC (
1UL << 0)
/* Receive Copy Complete */#
define INTSTAT_HCC (
1UL <<
1)
/* Header Copy Complete */#
define INTSTAT_RQE (
1UL <<
2)
/* Receive Queue Empty */#
define INTSTAT_TCC (
1UL <<
6)
/* Transmit Chain Complete */#
define INTSTAT_TQE (
1UL <<
7)
/* Transmit Queue Empty */#
define INTSTAT_RCT (
1UL <<
11)
/* Receive Copy Threshold */#
define INTSTAT_PME (
1UL <<
14)
/* Power Management Event */#
define INTSTAT_RCIP (
1UL <<
19)
/* Receive Copy in Progress */#
define INTSTAT_TCIP (
1UL <<
20)
/* Transmit Copy in Progress */#
define INTSTAT_RBE (
1UL <<
21)
/* Receive Buffers Empty */#
define INTSTAT_RCTS (
1UL <<
22)
/* Receive Copy Threshold Status */#
define INTSTAT_RSV (
1UL <<
23)
/* Receive Status Valid */#
define INTSTAT_DPE (
1UL <<
24)
/* PCI Data Parity Error */#
define INTSTAT_APE (
1UL <<
25)
/* PCI Address Parity Error */
#
define INTMASK_RCC (
1UL << 0)
/* Receive Copy Complete */#
define INTMASK_HCC (
1UL <<
1)
/* Header Copy Complete */#
define INTMASK_RQE (
1UL <<
2)
/* Receive Queue Empty */#
define INTMASK_TCC (
1UL <<
6)
/* Transmit Chain Complete */#
define INTMASK_TQE (
1UL <<
7)
/* Transmit Queue Empty */#
define INTMASK_RCT (
1UL <<
11)
/* Receive Copy Threshold */#
define INTMASK_PME (
1UL <<
14)
/* Power Management Event */
#
define GENCTL_INT (
1UL <<
1)
/* Interrupt Enable */#
define GENCTL_BE (
1UL <<
5)
/* Big Endian */#
define GENCTL_RDP (
1UL <<
6)
/* Receive DMA Priority */#
define GENCTL_TDP (
1UL <<
7)
/* Transmit DMA Priority */#
define GENCTL_RFT_64 (
1UL <<
8)
/* Receive FIFO Threshold (1/2) */#
define GENCTL_RFT_96 (
2UL <<
8)
/* Receive FIFO Threshold (3/4) */#
define GENCTL_MRM (
1UL <<
10)
/* Memory Read Multiple */#
define GENCTL_MRL (
1UL <<
11)
/* Memory Read Line */#
define GENCTL_RD (
1UL <<
17)
/* Reset Disable */#
define GENCTL_MPE (
1UL <<
18)
/* Magic Packet Enable */#
define GENCTL_PME (
1UL <<
19)
/* PME Interrupt Enable */#
define GENCTL_OPLE (
1UL <<
22)
/* On Power Loss Enable */
#
define NVCTL_EMM (
1UL << 0)
/* Enable Memory Map */#
define NVCTL_CRS (
1UL <<
1)
/* Clock Run Supported */#
define NVCTL_GPOE1 (
1UL <<
2)
/* General Purpose Output Enable 1 */#
define NVCTL_GPOE2 (
1UL <<
3)
/* General Purpose Output Enable 2 */#
define NVCTL_GPIO1 (
1UL <<
4)
/* General Purpose I/O 1 */#
define NVCTL_GPIO2 (
1UL <<
5)
/* General Purpose I/O 2 */
#
define EECTL_EECS (
1UL <<
1)
/* EEPROM Chip Select */#
define EECTL_EEDI (
1UL <<
3)
/* EEPROM Data Input */#
define EECTL_EEDO (
1UL <<
4)
/* EEPROM Data Output */
#
define MMCFG_SME (
1UL << 0)
/* Serial Mode Enable */#
define MMCFG_PHY (
1UL <<
3)
/* PHY Present */#
define MMCFG_SMI (
1UL <<
4)
/* Enable Serial Management */#
define MMCFG_ALTCS (
1UL <<
5)
/* Alternate Clock Source */#
define MMCFG_STXC (
1UL <<
14)
/* Select TX Clock */
#
define RXCON_SEP (
1UL << 0)
/* Save Errored Packets */#
define RXCON_RRF (
1UL <<
1)
/* Receive Runt Frames */#
define RXCON_RBF (
1UL <<
2)
/* Receive Broadcast Frames */#
define RXCON_RMF (
1UL <<
3)
/* Receive Multicast Frames */#
define RXCON_RIIA (
1UL <<
4)
/* Receive Inverse Addresses */#
define RXCON_ERE (
1UL <<
7)
/* Early Receive Enable */
#
define RXSTAT_PRI (
1UL << 0)
/* Packet Received Intact */#
define RXSTAT_FAE (
1UL <<
1)
/* Frame Alignment Error */#
define RXSTAT_MP (
1UL <<
3)
/* Missed Packet */#
define RXSTAT_MAR (
1UL <<
4)
/* Multicast Address Recognized */#
define RXSTAT_BAR (
1UL <<
5)
/* Broadcast Address Recognized */#
define RXSTAT_RD (
1UL <<
6)
/* Receiver Disabled */#
define RXSTAT_NSV (
1UL <<
12)
/* Network Status Valid */#
define RXSTAT_FLE (
1UL <<
13)
/* Fragment List Error */#
define RXSTAT_HC (
1UL <<
14)
/* Header Copied */#
define RXSTAT_OWNER (
1UL <<
15)
/* Descriptor Ownership Bit */
#
define TXCON_ETE (
1UL << 0)
/* Early Transmit Enable */#
define TXCON_LB_1 (
1UL <<
1)
/* Internal Loopback */#
define TXCON_LB_2 (
2UL <<
1)
/* External Loopback */#
define TXCON_LB_3 (
3UL <<
1)
/* Full Duplex Mode */
#
define TXSTAT_PTX (
1UL << 0)
/* Packet Transmitted */#
define TXSTAT_ND (
1UL <<
1)
/* Non-deferred Transmission */#
define TXSTAT_CSL (
1UL <<
3)
/* Carrier Sense Lost */#
define TXSTAT_CDH (
1UL <<
5)
/* Collision Detect Heartbeat */#
define TXSTAT_OWC (
1UL <<
6)
/* Out of Window Collision */#
define TXSTAT_OWNER (
1UL <<
15)
/* Descriptor Ownership Bit */
#
define TXCTL_IAF (
1UL <<
2)
/* Interrupt After Frame */#
define TXCTL_NOCRC (
1UL <<
3)
/* Disable CRC Generation */
/*
* Register access.
*/
/*
* DMA access.
*/
/*
* Soft state.
*/
typedef struct {
typedef struct {
typedef struct {
typedef struct {
/*
* Driver statistics.
*/
}
#endif
#endif /* _EFE_H */