ecpp.c revision 193974072f41a843678abf5f61979c748687e66b
/*
* CDDL HEADER START
*
* The contents of this file are subject to the terms of the
* Common Development and Distribution License (the "License").
* You may not use this file except in compliance with the License.
*
* You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
* See the License for the specific language governing permissions
* and limitations under the License.
*
* When distributing Covered Code, include this CDDL HEADER in each
* file and include the License file at usr/src/OPENSOLARIS.LICENSE.
* If applicable, add the following below this CDDL HEADER, with the
* fields enclosed by brackets "[]" replaced with your own identifying
* information: Portions Copyright [yyyy] [name of copyright owner]
*
* CDDL HEADER END
*/
/*
* Copyright 2008 Sun Microsystems, Inc. All rights reserved.
* Use is subject to license terms.
*/
/*
*
* IEEE 1284 Parallel Port Device Driver
*
*/
#include <sys/ddi_impldefs.h>
#include <sys/dma_engine.h>
#include <sys/dma_i8237A.h>
/*
* Background
* ==========
* IEEE 1284-1994 standard defines "a signalling method for asynchronous,
* fully interlocked, bidirectional parallel communications between hosts
* and printers or other peripherals." (1.1) The standard defines 5 modes
* of operation - Compatibility, Nibble, Byte, ECP and EPP - which differ
* in direction, bandwidth, pins assignment, DMA capability, etc.
*
* Negotiation is a mechanism for moving between modes. Compatibility mode
* is a default mode, from which negotiations to other modes occur and
* to which both host and peripheral break in case of interface errors.
* Compatibility mode provides a unidirectional (forward) channel for
* communicating with old pre-1284 peripherals.
*
* Each mode has a number of phases. [Mode, phase] pair represents the
* interface state. Host initiates all transfers, though peripheral can
* request backchannel transfer by asserting nErr pin.
*
* Ecpp driver implements an IEEE 1284-compliant host using a combination
* of hardware and software. Hardware part is represented by a controller,
* which is a part of the SuperIO chip. Ecpp supports the following SuperIOs:
* Struct ecpp_hw describes each SuperIO and is determined in ecpp_attach().
*
* Negotiation is performed in software. Transfer may be performed either
* in software by driving output pins for each byte (PIO method), or with
* hardware assistance - SuperIO has a 16-byte FIFO, which is filled by
* the driver (normally using DMA), while the chip performs the actual xfer.
* PIO is used for Nibble and Compat, DMA is used for ECP and Compat modes.
*
* Driver currently supports the following modes:
*
* pp->io_mode defines PIO or DMA method of transfer;
*
* Theory of operation
* ===================
* The manner in which ecpp drives 1284 interface is that of a state machine.
* State is a combination of 1284 mode {ECPP_*_MODE}, 1284 phase {ECPP_PHASE_*}
* and transfer method {PIO, DMA}. State is a function of application actions
* {write(2), ioctl(2)} and peripheral reaction.
*
* 1284 interface state is described by the following variables:
* pp->current_mode -- 1284 mode used for forward transfers;
* pp->backchannel -- 1284 mode used for backward transfers;
* pp->curent_phase -- 1284 phase;
*
* Bidirectional operation in Compatibility mode is provided by a combination:
* pp->current_mode == ECPP_COMPAT_MODE && pp->backchannel == ECPP_NIBBLE_MODE
* ECPP_CENTRONICS means no backchannel
*
* Driver internal state is defined by pp->e_busy as follows:
* ECPP_IDLE -- idle, no active transfers;
* ECPP_BUSY -- transfer is in progress;
* ECPP_ERR -- have data to transfer, but peripheral can`t receive data;
* ECPP_FLUSH -- flushing the queues;
*
* When opened, driver is in ECPP_IDLE state, current mode is ECPP_CENTRONICS
* Default negotiation tries to negotiate to the best mode supported by printer,
* sets pp->current_mode and pp->backchannel accordingly.
*
* When output data arrives in M_DATA mblks ecpp_wput() puts them on the queue
* to let ecpp_wsrv() concatenate small blocks into one big transfer
* by copying them into pp->ioblock. If first the mblk data is bigger than
* pp->ioblock, then it is used instead of i/o block (pointed by pp->msg)
*
* Before starting the transfer the driver will check if peripheral is ready
* by calling ecpp_check_status() and if it is not, driver goes ECPP_ERR state
* and schedules ecpp_wsrv_timer() which would qenable() the wq, effectively
* rechecking the peripheral readiness and restarting itself until it is ready.
* The transfer is then started by calling ecpp_start(), driver goes ECPP_BUSY
*
* While transfer is in progress all arriving messages will be queued up.
* Transfer can end up in either of two ways:
* - interrupt occurs, ecpp_isr() checks if all the data was transferred, if so
* cleanup and go ECPP_IDLE, otherwise putback untransferred and qenable();
* - ecpp_xfer_timeout() cancels the transfer and puts back untransferred data;
*
* PIO transfer method is very CPU intensive: for each sent byte the peripheral
* state is checked, then the byte is transfered and driver waits for an nAck
* interrupt; ecpp_isr() will then look if there is more data and if so
* triggers the soft interrupt, which transfers the next byte. PIO method
* is needed only for legacy printers which are sensitive to strobe problem
* (Bugid 4192788).
*
* ecpp_wsrv() is responsible for both starting transfers (ecpp_start()) and
* going idle (ecpp_idle_phase()). Many routines qenable() the write queue,
* meaning "check if there are pending requests, process them and go idle".
*
* In it`s idle state the driver will always try to listen to the backchannel
* (as advised by 1284).
*
* The mechanism for handling backchannel requests is as follows:
* - when the peripheral has data to send it asserts nErr pin
* (and also nAck in Nibble Mode) which results in an interrupt on the host;
* - ISR creates M_CTL message containing an ECPP_BACKCHANNEL byte and
* puts it back on the write queue;
* - ecpp_wsrv() gets M_CTL and calls ecpp_peripheral2host(), which kicks off
* the transfer;
*
* This way Nibble and ECP mode backchannel are implemented.
* If the read queue gets full, backchannel request is rejected.
* As the application reads data and queue size falls below the low watermark,
* ecpp_rsrv() gets called and enables the backchannel again.
*
* Future enhancements
* ===================
*
* Support new modes: Byte and EPP.
*/
#ifndef ECPP_DEBUG
#define ECPP_DEBUG 0
#endif /* ECPP_DEBUG */
int ecpp_debug = ECPP_DEBUG;
int noecp = 0; /* flag not to use ECP mode */
/* driver entry point fn definitions */
/* configuration entry point fn definitions */
/* isr support routines */
/* configuration support routines */
static void ecpp_get_props(struct ecppunit *);
/* Streams Routines */
static void ecpp_flush(struct ecppunit *, int);
/* ioctl handling */
struct ecpp_device_id *, int *);
/* kstat routines */
static void ecpp_kstat_init(struct ecppunit *);
static int ecpp_kstat_update(kstat_t *, int);
static int ecpp_kstatintr_update(kstat_t *, int);
/* dma routines */
/* pio routines */
static void ecpp_pio_writeb(struct ecppunit *);
static void ecpp_xfer_cleanup(struct ecppunit *);
/* misc */
static void ecpp_xfer_timeout(void *);
static void ecpp_fifo_timer(void *);
static void ecpp_wsrv_timer(void *);
static int ecpp_backchan_req(struct ecppunit *);
/* stubs */
static void empty_config_mode(struct ecppunit *);
static void empty_mask_intr(struct ecppunit *);
/* PC87332 support */
static int pc87332_map_regs(struct ecppunit *);
static void pc87332_unmap_regs(struct ecppunit *);
static int pc87332_config_chip(struct ecppunit *);
static void pc87332_config_mode(struct ecppunit *);
static void cheerio_mask_intr(struct ecppunit *);
static void cheerio_unmask_intr(struct ecppunit *);
static int cheerio_dma_start(struct ecppunit *);
static void cheerio_reset_dcsr(struct ecppunit *);
/* PC97317 support */
static int pc97317_map_regs(struct ecppunit *);
static void pc97317_unmap_regs(struct ecppunit *);
static int pc97317_config_chip(struct ecppunit *);
static void pc97317_config_mode(struct ecppunit *);
/* M1553 Southbridge support */
static int m1553_config_chip(struct ecppunit *);
/* M1553 Southbridge DMAC 8237 support routines */
static int dma8237_dma_start(struct ecppunit *);
#ifdef INCLUDE_DMA8237_READ_ADDR
#endif
/* i86 PC support rountines */
#if defined(__x86)
static int x86_dma_start(struct ecppunit *);
static int x86_map_regs(struct ecppunit *);
static void x86_unmap_regs(struct ecppunit *);
static int x86_config_chip(struct ecppunit *);
#endif
/* IEEE 1284 phase transitions */
static void ecpp_1284_init_interface(struct ecppunit *);
static int ecpp_1284_termination(struct ecppunit *);
static int ecp_forward2reverse(struct ecppunit *);
static int ecp_reverse2forward(struct ecppunit *);
static int read_nibble_backchan(struct ecppunit *);
/* reverse transfers */
static void ecpp_ecp_read_timeout(void *);
static void ecpp_ecp_read_completion(struct ecppunit *);
/* IEEE 1284 mode transitions */
static void ecpp_default_negotiation(struct ecppunit *);
static int ecp_negotiation(struct ecppunit *);
static int nibble_negotiation(struct ecppunit *);
static int devidnib_negotiation(struct ecppunit *);
/* IEEE 1284 utility routines */
/* debugging functions */
static void ecpp_error(dev_info_t *, char *, ...);
/*
* Chip-dependent structures
*/
static ddi_dma_attr_t cheerio_dma_attr = {
DMA_ATTR_VERSION, /* version */
0x00000000ull, /* dlim_addr_lo */
0xfffffffeull, /* dlim_addr_hi */
0xffffff, /* DMA counter register */
1, /* DMA address alignment */
0x74, /* burst sizes */
0x0001, /* min effective DMA size */
0xffff, /* maximum transfer size */
0xffff, /* segment boundary */
1, /* s/g list length */
1, /* granularity of device */
0 /* DMA flags */
};
};
};
static ddi_dma_attr_t i8237_dma_attr = {
DMA_ATTR_VERSION, /* version */
0x00000000ull, /* dlim_addr_lo */
0xfffffffeull, /* dlim_addr_hi */
0xffff, /* DMA counter register */
1, /* DMA address alignment */
0x01, /* burst sizes */
0x0001, /* min effective DMA size */
0xffff, /* maximum transfer size */
0x7fff, /* segment boundary */
1, /* s/g list length */
1, /* granularity of device */
0 /* DMA flags */
};
empty_config_mode, /* no config_mode */
empty_mask_intr, /* no mask_intr */
empty_mask_intr, /* no unmask_intr */
};
#if defined(__x86)
static ddi_dma_attr_t sb_dma_attr = {
DMA_ATTR_VERSION, /* version */
0x00000000ull, /* dlim_addr_lo */
0xffffff, /* dlim_addr_hi */
0xffff, /* DMA counter register */
1, /* DMA address alignment */
0x01, /* burst sizes */
0x0001, /* min effective DMA size */
0xffffffff, /* maximum transfer size */
0xffff, /* segment boundary */
1, /* s/g list length */
1, /* granularity of device */
0 /* DMA flags */
};
empty_config_mode, /* no config_mode */
empty_mask_intr, /* no mask_intr */
empty_mask_intr, /* no unmask_intr */
};
#endif
/*
* list of supported devices
*/
struct ecpp_hw_bind ecpp_hw_bind[] = {
#if defined(__x86)
#endif
};
static ddi_device_acc_attr_t acc_attr = {
};
static struct ecpp_transfer_parms default_xfer_parms = {
FWD_TIMEOUT_DEFAULT, /* write timeout in seconds */
ECPP_CENTRONICS /* supported mode */
};
/* prnio interface info string */
static const char prn_ifinfo[] = PRN_PARALLEL;
/* prnio timeouts */
static const struct prn_timeouts prn_timeouts_default = {
FWD_TIMEOUT_DEFAULT, /* forward timeout */
REV_TIMEOUT_DEFAULT /* reverse timeout */
};
static int ecpp_isr_max_delay = ECPP_ISR_MAX_DELAY;
static void *ecppsoft_statep;
/*
* STREAMS framework manages locks for these structures
*/
struct module_info ecppinfo = {
/* id, name, min pkt siz, max pkt siz, hi water, low water */
};
static struct qinit ecpp_rinit = {
};
};
struct streamtab ecpp_str_info = {
};
static struct cb_ops ecpp_cb_ops = {
nodev, /* cb_open */
nodev, /* cb_close */
nodev, /* cb_strategy */
nodev, /* cb_print */
nodev, /* cb_dump */
nodev, /* cb_read */
nodev, /* cb_write */
nodev, /* cb_ioctl */
nodev, /* cb_devmap */
nodev, /* cb_mmap */
nodev, /* cb_segmap */
nochpoll, /* cb_chpoll */
ddi_prop_op, /* cb_prop_op */
&ecpp_str_info, /* cb_stream */
};
/*
* Declare ops vectors for auto configuration.
*/
DEVO_REV, /* devo_rev */
0, /* devo_refcnt */
ecpp_getinfo, /* devo_getinfo */
nulldev, /* devo_identify */
nulldev, /* devo_probe */
ecpp_attach, /* devo_attach */
ecpp_detach, /* devo_detach */
nodev, /* devo_reset */
&ecpp_cb_ops, /* devo_cb_ops */
nulldev, /* devo_power */
ddi_quiesce_not_needed, /* devo_quiesce */
};
extern struct mod_ops mod_driverops;
static struct modldrv ecppmodldrv = {
&mod_driverops, /* type of module - driver */
"parallel port driver",
&ecpp_ops,
};
static struct modlinkage ecppmodlinkage = {
0
};
/*
*
*
*/
int
_init(void)
{
int error;
(void) ddi_soft_state_init(&ecppsoft_statep,
sizeof (struct ecppunit), 1);
}
return (error);
}
int
_fini(void)
{
int error;
}
return (error);
}
int
{
}
static int
{
int instance;
char name[16];
struct ecpp_hw_bind *hw_bind;
switch (cmd) {
case DDI_ATTACH:
break;
case DDI_RESUME:
return (DDI_FAILURE);
}
/*
* Initialize the chip and restore current mode if needed
*/
(void) ECPP_CONFIG_CHIP(pp);
(void) ecpp_reset_port_regs(pp);
(void) ecpp_1284_termination(pp);
}
return (DDI_SUCCESS);
default:
return (DDI_FAILURE);
}
goto fail;
}
/*
* Determine SuperIO type and set chip-dependent variables
*/
goto fail_sio;
} else {
}
/*
* Map registers
*/
goto fail_map;
}
goto fail_dma;
}
if (ddi_get_iblock_cookie(dip, 0,
goto fail_ibc;
}
(void *)pp->ecpp_trap_cookie);
goto fail_intr;
}
goto fail_softintr;
}
goto fail_minor;
}
goto fail_iob;
} else {
}
#if defined(__x86)
}
#endif
goto fail_config;
}
return (DDI_SUCCESS);
fail:
return (DDI_FAILURE);
}
static int
{
int instance;
switch (cmd) {
case DDI_DETACH:
break;
case DDI_SUSPEND:
return (DDI_FAILURE);
}
/*
* Wait if there's any activity on the port
*/
ddi_get_lbolt() +
"ecpp_detach: suspend timeout\n");
return (DDI_FAILURE);
}
}
return (DDI_SUCCESS);
default:
return (DDI_FAILURE);
}
#if defined(__x86)
#endif
}
}
return (DDI_SUCCESS);
}
/*
* ecpp_get_props() reads ecpp.conf for user defineable tuneables.
* If the file or a particular variable is not there, a default value
* is assigned.
*/
static void
{
char *prop;
#if defined(__x86)
int len;
int value;
#endif
/*
* If fast_centronics is TRUE, non-compliant IEEE 1284
* peripherals ( Centronics peripherals) will operate in DMA mode.
* Transfers betwee main memory and the device will be via DMA;
* peripheral handshaking will be conducted by superio logic.
* If ecpp can not read the variable correctly fast_centronics will
* be set to FALSE. In this case, transfers and handshaking
* will be conducted by PIO for Centronics devices.
*/
} else {
}
/*
* If fast-1284-compatible is set to TRUE, when ecpp communicates
* with IEEE 1284 compliant peripherals, data transfers between
* main memory and the parallel port will be conducted by DMA.
* Handshaking between the port and peripheral will be conducted
* by superio logic. This is the default characteristic. If
* fast-1284-compatible is set to FALSE, transfers and handshaking
* will be conducted by PIO.
*/
} else {
}
/*
* Some centronics peripherals require the nInit signal to be
* toggled to reset the device. If centronics_init_seq is set
* to TRUE, ecpp will toggle the nInit signal upon every ecpp_open().
* Applications have the opportunity to toggle the nInit signal
* with ioctl(2) calls as well. The default is to set it to FALSE.
*/
} else {
}
/*
* If one of the centronics status signals are in an erroneous
* state, ecpp_wsrv() will be reinvoked centronics-retry ms to
* check if the status is ok to transfer. If the property is not
* found, wsrv_retry will be set to CENTRONICS_RETRY ms.
*/
"centronics-retry", CENTRONICS_RETRY);
/*
* In PIO mode, ecpp_isr() will loop for wait for the busy signal
* to be deasserted before transferring the next byte. wait_for_busy
* is specificied in microseconds. If the property is not found
* ecpp_isr() will wait for a maximum of WAIT_FOR_BUSY us.
*/
"centronics-wait-for-busy", WAIT_FOR_BUSY);
/*
* In PIO mode, centronics transfers must hold the data signals
* for a data_setup_time milliseconds before the strobe is asserted.
*/
"centronics-data-setup-time", DATA_SETUP_TIME);
/*
* In PIO mode, centronics transfers asserts the strobe signal
* for a period of strobe_pulse_width milliseconds.
*/
"centronics-strobe-pulse-width", STROBE_PULSE_WIDTH);
/*
* Upon a transfer the peripheral, ecpp waits write_timeout seconds
* for the transmission to complete.
*/
/*
* Get dma channel for M1553
*/
}
#if defined(__x86)
/* Get dma channel for i86 pc */
!= DDI_PROP_SUCCESS) {
} else
}
#endif
/*
* these properties are not yet public
*/
"ecp-rev-speed", ECP_REV_SPEED);
"rev-watchdog", REV_WATCHDOG);
"ecpp_get_prop: fast_centronics=%x, fast-1284=%x\n"
"ecpp_get_prop: wsrv_retry=%d, wait_for_busy=%d\n"
"ecpp_get_prop: data_setup=%d, strobe_pulse=%d\n"
"ecpp_get_prop: transfer-timeout=%d\n",
}
/*ARGSUSED*/
int
{
switch (infocmd) {
case DDI_INFO_DEVT2DEVINFO:
ret = DDI_SUCCESS;
} else {
ret = DDI_FAILURE;
}
break;
case DDI_INFO_DEVT2INSTANCE:
ret = DDI_SUCCESS;
break;
default:
ret = DDI_FAILURE;
break;
}
return (ret);
}
/*ARGSUSED2*/
static int
{
int instance;
struct stroptions *sop;
if (instance < 0) {
return (ENXIO);
}
return (ENXIO);
}
/*
* Parallel port is an exclusive-use device
* thus providing print job integrity
*/
return (EBUSY);
}
/* initialize state variables */
pp->timeout_error = 0;
pp->ecpp_drain_counter = 0;
pp->tfifo_intr = 0;
pp->softintr_pending = 0;
/* clear the state flag */
/*
* Get ready: check host/peripheral, negotiate into default mode
*/
return (EIO);
}
/*
* Configure the Stream head and enable the Stream
*/
return (EAGAIN);
}
/*
* if device is open with O_NONBLOCK flag set, let read(2) return 0
* if no data waiting to be read. Writes will block on flow control.
*/
/* enable the stream */
qprocson(q);
/* go revidle */
(void) ecpp_idle_phase(pp);
"ecpp_open: mode=%x, phase=%x ecr=%x, dsr=%x, dcr=%x\n",
return (0);
}
/*ARGSUSED1*/
static int
{
/*
* ecpp_close() will continue to loop until the
* queue has been drained or if the thread
* has received a SIG. Typically, when the queue
* has data, the port will be ECPP_BUSY. However,
* after a dma completes and before the wsrv
* starts the next transfer, the port may be IDLE.
* In this case, ecpp_close() will loop within this
* while(qsize) segment. Since, ecpp_wsrv() runs
* at software interupt level, this shouldn't loop
* very long.
*/
/*
* Returning from a signal such as
* SIGTERM or SIGKILL
*/
break;
} else {
}
}
"qsize(WR(q))=%d, qsize(RD(q))=%d\n",
/*
* Cancel all timeouts, disable interrupts
*
* Note that we can`t call untimeout(9F) with mutex held:
* callout may be blocked on the same mutex, and untimeout() will
* cv_wait() while callout is executing, thus creating a deadlock
* So we zero the timeout id's inside mutex and call untimeout later
*/
pp->softintr_pending = 0;
qprocsoff(q);
if (timeout_id) {
(void) untimeout(timeout_id);
}
if (fifo_timer_id) {
(void) untimeout(fifo_timer_id);
}
if (wsrv_timer_id) {
(void) untimeout(wsrv_timer_id);
}
/* set link to Compatible mode */
(void) ecp_reverse2forward(pp);
}
(void) ecpp_1284_termination(pp);
return (0);
}
/*
* standard put procedure for ecpp
*/
static int
{
if (!mp) {
return (0);
}
"ecpp_wput:bogus packet recieved mp=%x\n", mp);
return (0);
}
case M_DATA:
/*
* This is a quick fix for multiple message block problem,
* it will be changed later with better performance code.
*/
/*
* mblk has scattered data ... do msgpullup
* if it fails, continue with the current mblk
*/
"ecpp_wput:msgpullup: mp=%p len=%d\n",
}
}
/* let ecpp_wsrv() concatenate small blocks */
break;
case M_CTL:
break;
case M_IOCTL: {
/* TESTIO and GET_STATUS can be used during transfer */
} else {
ecpp_putioc(q, mp);
}
break;
}
case M_IOCDATA: {
/*
* If copy request failed, quit now
*/
return (0);
}
case ECPPIOC_SETPARMS:
case ECPPIOC_SETREGS:
case ECPPIOC_SETPORT:
case ECPPIOC_SETDATA:
case PRNIOC_SET_IFCAP:
case PRNIOC_SET_TIMEOUTS:
/*
* need to retrieve and use the data, but if the
* device is busy, wait.
*/
break;
case ECPPIOC_GETPARMS:
case ECPPIOC_GETREGS:
case ECPPIOC_GETPORT:
case ECPPIOC_GETDATA:
case BPPIOC_GETERR:
case BPPIOC_TESTIO:
case PRNIOC_GET_IFCAP:
case PRNIOC_GET_STATUS:
case PRNIOC_GET_1284_STATUS:
case PRNIOC_GET_TIMEOUTS:
/* data transfered to user space okay */
ecpp_ack_ioctl(q, mp);
break;
case ECPPIOC_GETDEVID:
break;
case PRNIOC_GET_1284_DEVID:
break;
case PRNIOC_GET_IFINFO:
break;
default:
break;
}
break;
}
case M_FLUSH:
}
} else {
}
break;
case M_READ:
/*
* When the user calls read(2), M_READ message is sent to us,
* first byte of which is the number of requested bytes
* We add up user requests and use resulting number
* to calculate the reverse transfer block size
*/
} else {
}
break;
default:
break;
}
return (0);
}
/*
* Process ECPPIOC_GETDEVID-like ioctls
*/
static void
{
struct ecpp_copystate *stp;
case ECPP_STRUCTIN:
/* user structure has arrived */
break;
case ECPP_ADDROUT:
/*
* data transfered to user space okay
* now update user structure
*/
break;
}
break;
case ECPP_STRUCTOUT:
/* user structure was updated okay */
ecpp_ack_ioctl(q, mp);
break;
default:
break;
}
}
static uchar_t
{
uchar_t pin_status = 0;
}
pin_status |= BPP_PE_ERR;
}
}
if (!(status & ECPP_nBUSY)) {
}
return (pin_status);
}
/*
* ioctl handler for output PUT procedure.
*/
static void
{
/* I_STR ioctls are invalid */
return;
}
case ECPPIOC_SETPARMS: {
break;
}
case ECPPIOC_GETPARMS: {
struct ecpp_transfer_parms xfer_parms;
break;
}
case ECPPIOC_SETREGS: {
break;
}
break;
}
case ECPPIOC_GETREGS: {
break;
}
/* these bits must be 1 */
break;
}
case ECPPIOC_SETPORT:
case ECPPIOC_SETDATA: {
break;
}
/*
* each of the commands fetches a byte quantity.
*/
break;
}
case ECPPIOC_GETDATA:
case ECPPIOC_GETPORT: {
/* must be in diagnostic mode for these commands to work */
break;
}
case ECPP_PORT_PIO:
break;
case ECPP_PORT_TDMA:
break;
default:
break;
}
} else {
break;
}
break;
}
case BPPIOC_GETERR: {
struct bpp_error_status bpp_status;
break;
}
case BPPIOC_TESTIO: {
} else {
} else {
ecpp_ack_ioctl(q, mp);
}
}
break;
}
case PRNIOC_RESET:
/*
* Initialize interface only if no transfer is in progress
*/
} else {
drv_usecwait(2);
ecpp_ack_ioctl(q, mp);
}
break;
case PRNIOC_GET_IFCAP: {
break;
}
case PRNIOC_SET_IFCAP: {
break;
}
case PRNIOC_GET_TIMEOUTS: {
struct prn_timeouts timeouts;
break;
}
case PRNIOC_SET_TIMEOUTS:
break;
case PRNIOC_GET_STATUS: {
/* DSR only makes sense in Centronics & Compat mode */
status = PRN_ONLINE;
} else {
}
} else {
}
break;
}
case PRNIOC_GET_1284_STATUS: {
/* status only makes sense in Centronics & Compat mode */
break;
}
(~dsr & ECPP_nBUSY);
break;
}
case ECPPIOC_GETDEVID:
sizeof (struct ecpp_device_id));
break;
case PRNIOC_GET_1284_DEVID:
sizeof (struct prn_1284_device_id));
break;
case PRNIOC_GET_IFINFO:
sizeof (struct prn_interface_info));
break;
default:
break;
}
}
/*
* allocate mblk and copyout the requested number of bytes
*/
static void
{
return;
}
}
/*
* copyin the structure using struct ecpp_copystate
*/
static void
{
struct ecpp_copystate *stp;
return;
}
}
/*
* read queue is only used when the peripheral sends data faster,
* then the application consumes it;
* once the low water mark is reached, this routine will be scheduled
*/
static int
{
/*
* send data upstream until next queue is full or the queue is empty
*/
}
/*
* if there is still space on the queue, enable backchannel
*/
if (canputnext(q)) {
(void) ecpp_idle_phase(pp);
}
}
return (0);
}
static int
{
/* if channel is actively doing work, wait till completed */
return (0);
/*
* if the system is about to suspend and ecpp_detach()
* is blocked due to active transfers, wake it up and exit
*/
return (0);
}
/* peripheral status should be okay before starting transfer */
if (pp->wsrv_timer_id == 0) {
} else {
"ecpp_wsrv: wrsv_timer is active\n");
}
return (0);
} else {
}
}
/*
* it`s important to null pp->msg here,
* cleaning up from the previous transfer attempts
*/
start_addr = NULL;
/*
* The following loop is implemented to gather the
* many small writes that the lp subsystem makes and
* compile them into one large dma transfer. The len and
* total_len variables are a running count of the number of
* bytes that have been gathered. They are bcopied to the
* ioblock buffer. The pp->e_busy is set to E_BUSY as soon as
* we start gathering packets to indicate the following transfer.
*/
case M_DATA:
/*
* if the first M_DATA is bigger than ioblock,
* just use this mblk and start the transfer
*/
goto breakout;
/*
* current M_DATA does not fit in ioblock,
* put it back and start the transfer
*/
goto breakout;
} else {
/*
* otherwise add data to ioblock and free mblk
*/
my_ioblock += len;
}
break;
case M_IOCTL:
/*
* Assume a simple loopback test: an application
* writes data into the TFIFO, reads it using
* ECPPIOC_GETDATA and compares. If the transfer
* times out (which is only possible on Grover),
* the ioctl might be processed before the data
* got to the TFIFO, which leads to miscompare.
* So if we met ioctl, postpone it until after xfer.
*/
if (total_len > 0) {
goto breakout;
}
ecpp_putioc(q, mp);
break;
case M_IOCDATA: {
/*
* If copy request failed, quit now
*/
break;
}
case ECPPIOC_SETPARMS:
case ECPPIOC_SETREGS:
case ECPPIOC_SETPORT:
case ECPPIOC_SETDATA:
case ECPPIOC_GETDEVID:
case PRNIOC_SET_IFCAP:
case PRNIOC_GET_1284_DEVID:
case PRNIOC_SET_TIMEOUTS:
case PRNIOC_GET_IFINFO:
ecpp_srvioc(q, mp);
break;
default:
break;
}
break;
}
case M_CTL:
goto breakout;
} else {
}
/* sanity check */
break;
} else {
}
/* This was a backchannel request */
(void) ecpp_peripheral2host(pp);
/* exit if transfer have been initiated */
goto breakout;
}
break;
case M_READ:
break;
default:
break;
}
}
/*
* If total_len > 0 then start the transfer, otherwise goto idle state
*/
if (total_len > 0) {
} else {
/* IDLE if xfer_timeout, or FIFO_EMPTY */
(void) ecpp_idle_phase(pp);
}
}
return (1);
}
/*
* Ioctl processor for queued ioctl data transfer messages.
*/
static void
{
case ECPPIOC_SETPARMS: {
struct ecpp_transfer_parms *xferp;
if (xferp->write_timeout <= 0 ||
break;
}
break;
}
} else {
/*
* mode nego was a success. If nibble mode check
* back channel and set into REVIDLE.
*/
/*
* problems reading the backchannel
* returned to centronics;
* ioctl fails.
*/
break;
}
ecpp_ack_ioctl(q, mp);
}
} else {
}
break;
}
case ECPPIOC_SETREGS: {
/* must be in diagnostic mode for these commands to work */
break;
}
/* bits 4-7 must be 1 or return EINVAL */
break;
}
/* get the old dcr */
/* get the new dcr */
ecpp_ack_ioctl(q, mp);
break;
}
case ECPPIOC_SETPORT: {
/* must be in diagnostic mode for these commands to work */
break;
}
switch (*port) {
case ECPP_PORT_PIO:
/* put superio into PIO mode */
ecpp_ack_ioctl(q, mp);
break;
case ECPP_PORT_TDMA:
/* change to mode 110 */
ecpp_ack_ioctl(q, mp);
break;
default:
}
break;
}
case ECPPIOC_SETDATA: {
/* must be in diagnostic mode for these commands to work */
break;
}
case ECPP_PORT_PIO:
ecpp_ack_ioctl(q, mp);
break;
case ECPP_PORT_TDMA:
ecpp_ack_ioctl(q, mp);
break;
default:
}
break;
}
case ECPPIOC_GETDEVID: {
struct ecpp_copystate *stp;
struct ecpp_device_id *dp;
struct ecpp_device_id id;
#ifdef _MULTI_DATAMODEL
struct ecpp_device_id32 *dp32;
} else {
#endif /* _MULTI_DATAMODEL */
#ifdef _MULTI_DATAMODEL
}
#endif /* _MULTI_DATAMODEL */
break;
}
case PRNIOC_GET_1284_DEVID: {
struct ecpp_copystate *stp;
struct prn_1284_device_id *dp;
struct ecpp_device_id id;
/* imitate struct ecpp_device_id */
#ifdef _MULTI_DATAMODEL
struct prn_1284_device_id32 *dp32;
} else {
#endif /* _MULTI_DATAMODEL */
#ifdef _MULTI_DATAMODEL
}
#endif /* _MULTI_DATAMODEL */
break;
}
case PRNIOC_SET_IFCAP: {
ecpp_ack_ioctl(q, mp);
break;
}
/* only changing PRN_BIDI is supported */
break;
}
} else { /* go unidirectional */
}
ecpp_ack_ioctl(q, mp);
break;
}
case PRNIOC_SET_TIMEOUTS: {
struct prn_timeouts *prn_timeouts;
break;
}
ecpp_ack_ioctl(q, mp);
break;
}
case PRNIOC_GET_IFINFO:
ecpp_srvioc_prnif(q, mp);
break;
default: /* unexpected ioctl type */
break;
}
}
static void
{
struct ecpp_copystate *stp;
int error;
int len;
int mode;
/* check arguments */
return;
}
/* Currently only Nibble mode is supported */
if (mode != ECPP_NIBBLE_MODE) {
return;
}
return;
}
/* read device ID length */
goto breakout;
}
/* don't take into account two length bytes */
len -= 2;
/* limit transfer to user buffer length */
}
if (len == 0) {
/* just return rlen */
goto breakout;
}
goto breakout;
}
/* read ID string */
if (error) {
goto breakout;
} else {
}
return;
(void) ecpp_1284_termination(pp);
}
/*
* PRNIOC_GET_IFINFO: return prnio interface info string
*/
static void
{
struct ecpp_copystate *stp;
struct prn_interface_info *ip;
struct prn_interface_info info;
#ifdef _MULTI_DATAMODEL
#endif
#ifdef _MULTI_DATAMODEL
struct prn_interface_info32 *ip32;
} else {
#endif /* _MULTI_DATAMODEL */
#ifdef _MULTI_DATAMODEL
}
#endif /* _MULTI_DATAMODEL */
/* check arguments */
return;
}
/* just copyout rlen */
return;
}
/* if needed, trim to the buffer size */
}
return;
}
}
static void
{
queue_t *q;
return;
}
/* if there is an ongoing DMA, it needs to be turned off. */
case ECPP_BUSY:
/*
* Change the port status to ECPP_FLUSH to
* indicate to ecpp_wsrv that the wq is being flushed.
*/
/*
* dma_cancelled indicates to ecpp_isr() that we have
* turned off the DMA. Since the mutex is held, ecpp_isr()
* may be blocked. Once ecpp_flush() finishes and ecpp_isr()
* gains the mutex, ecpp_isr() will have a _reset_ DMAC. Most
* significantly, the DMAC will be reset after ecpp_isr() was
* invoked. Therefore we need to have a flag "dma_cancelled"
* to signify when the described condition has occured. If
* ecpp_isr() notes a dma_cancelled, it will ignore the DMAC csr
* and simply claim the interupt.
*/
/* either DMA or PIO transfer */
if (COMPAT_DMA(pp) ||
/*
* if the bcr is zero, then DMA is complete and
* we are waiting for the fifo to drain. Therefore,
* turn off dma.
*/
"ecpp_flush: dma_stop failed.\n");
}
/*
* If the status of the port is ECPP_BUSY,
* the DMA is stopped by either explicitly above, or by
* ecpp_isr() but the FIFO hasn't drained yet. In either
* case, we need to unbind the dma mappings.
*/
"ecpp_flush: unbind failed.\n");
}
} else {
/*
* PIO transfer: disable nAck interrups
*/
}
/*
* The transfer is cleaned up. There may or may not be data
* in the fifo. We don't care at this point. Ie. SuperIO may
* transfer the remaining bytes in the fifo or not. it doesn't
* matter. All that is important at this stage is that no more
* fifo timers are started.
*/
pp->softintr_pending = 0;
break;
case ECPP_ERR:
/*
* Change the port status to ECPP_FLUSH to
* indicate to ecpp_wsrv that the wq is being flushed.
*/
/*
* Most likely there are mblks in the queue,
* but the driver can not transmit because
* of the bad port status. In this case,
* ecpp_flush() should make sure ecpp_wsrv_timer()
* is turned off.
*/
pp->wsrv_timer_id = 0;
break;
case ECPP_IDLE:
/* No work to do. Ready to flush */
break;
default:
}
/* in DIAG mode clear TFIFO if needed */
if (!(ecr & ECPP_FIFO_EMPTY)) {
}
}
/* Discard all messages on the output queue. */
/* The port is no longer flushing or dma'ing for that matter. */
/* Set the right phase */
} else {
}
}
/* cancel timeouts if any */
if (timeout_id) {
(void) untimeout(timeout_id);
}
if (fifo_timer_id) {
(void) untimeout(fifo_timer_id);
}
if (wsrv_timer_id) {
(void) untimeout(wsrv_timer_id);
}
}
static void
{
"ecpp_start:current_mode=%x,current_phase=%x,ecr=%x,len=%d\n",
switch (pp->current_mode) {
case ECPP_NIBBLE_MODE:
(void) ecpp_1284_termination(pp);
/* After termination we are either Compatible or Centronics */
/* FALLTHRU */
case ECPP_CENTRONICS:
case ECPP_COMPAT_MODE:
return;
}
} else {
/* PIO mode */
return;
}
(void) ecpp_pio_writeb(pp);
}
break;
case ECPP_DIAG_MODE: {
int oldlen;
/* put superio into TFIFO mode, if not already */
/*
* DMA would block if the TFIFO is not empty
* if by this moment nobody read these bytes, they`re gone
*/
drv_usecwait(1);
"ecpp_start: TFIFO not empty, clearing\n");
}
/* we can DMA at most 16 bytes into TFIFO */
if (len > ECPP_FIFO_SZ) {
len = ECPP_FIFO_SZ;
}
return;
}
/* put the rest of data back on the queue */
}
break;
}
case ECPP_ECP_MODE:
/* if in Reverse Phase negotiate to Forward */
} else {
}
}
}
return;
}
break;
}
/* schedule transfer timeout */
}
/*
* Transfer a PIO "block" a byte at a time.
* The block is starts at addr and ends at pp->last_byte
*/
static uint8_t
{
/*
* if status signals are bad, do not start PIO,
* put everything back on the queue.
*/
"ecpp_prep_pio_xfer:suspend PIO len=%d\n", len);
/*
* this circumstance we want to copy the
* untransfered section of msg to a new mblk,
* then free the orignal one.
*/
"ecpp_prep_pio_xfer: len1=%d\n", len);
} else {
"ecpp_prep_pio_xfer: len2=%d\n", len);
}
return (FAILURE);
}
/* pport must be in PIO mode */
}
return (SUCCESS);
}
static uint8_t
{
0,
ECR_mode_010, /* Centronix */
ECR_mode_010, /* Compat */
0, /* Byte */
0, /* Nibble */
ECR_mode_011, /* ECP */
0, /* Failure */
ECR_mode_110, /* Diag */
};
return (FAILURE);
}
/*
* if status signals are bad, do not start DMA, but
* rather put everything back on the queue.
*/
"ecpp_init_dma_xfer: suspending DMA len=%d\n",
/*
* this circumstance we want to copy the
* untransfered section of msg to a new mblk,
* then free the orignal one.
*/
"ecpp_init_dma_xfer:a:len=%d\n", len);
} else {
"ecpp_init_dma_xfer:b:len=%d\n", len);
}
"ecpp_init_dma_xfer: unbind FAILURE.\n");
}
return (FAILURE);
}
pp->tfifo_intr = 0;
/* set the right ECR mode and disable DMA */
/* prepare DMAC for a transfer */
return (FAILURE);
}
/* GO! */
return (SUCCESS);
}
static uint8_t
{
int err;
switch (err) {
case DDI_DMA_MAPPED:
break;
case DDI_DMA_PARTIAL_MAP: {
return (FAILURE);
}
/*
* The very first window is returned by bind_handle,
* but we must do this explicitly here, otherwise
* next getwin would return wrong cookie dmac_size
*/
"ecpp_setup_dma: ddi_dma_getwin failed!");
return (FAILURE);
}
"ecpp_setup_dma: cookies=%d, windows=%d"
" addr=%lx len=%d\n",
break;
}
default:
return (FAILURE);
}
return (SUCCESS);
}
static void
{
}
}
static void
{
}
}
{
int cheerio_pend_counter;
int retval = DDI_INTR_UNCLAIMED;
/*
* interrupt may occur while other thread is holding the lock
* and cancels DMA transfer (e.g. ecpp_flush())
* since it cannot cancel the interrupt thread,
* it just sets dma_cancelled to TRUE,
* telling interrupt handler to exit immediately
*/
return (DDI_INTR_CLAIMED);
}
/* Southbridge interrupts are handled separately */
#if defined(__x86)
#else
#endif
{
if (retval == DDI_INTR_UNCLAIMED) {
goto unexpected;
}
return (DDI_INTR_CLAIMED);
}
/*
* the intr is through the motherboard. it is faster than PCI route.
* sometimes ecpp_isr() is invoked before cheerio csr is updated.
*/
drv_usecwait(1);
}
/*
* This is a workaround for what seems to be a timing problem
* with the delivery of interrupts and CSR updating with the
* ebus2 csr, superio and the n_ERR pin from the peripheral.
*
* delay is not needed for PIO mode
*/
if (!COMPAT_PIO(pp)) {
drv_usecwait(100);
}
/* on 97317 in Extended mode IRQ_ST of DSR is deasserted when read */
/*
* check if interrupt is for this device:
* it should be reflected either in cheerio DCSR register
* or in IRQ_ST bit of DSR on 97317
*/
if ((dcsr & DCSR_INT_PEND) == 0) {
goto unclaimed;
}
/*
* on Excalibur, reading DSR will deassert SuperIO IRQx line
* RIO's DCSR_INT_PEND seems to follow IRQx transitions,
* so if DSR is read after interrupt occured, but before
* we get here, IRQx and hence INT_PEND will be deasserted
* as a result, we can miss a service interrupt in PIO mode
*
* malicious DSR reader is BPPIOC_TESTIO, which is called
* by LP in between data blocks to check printer status
* this workaround lets us not to miss an interrupt
*
* also, nErr interrupt (ECP mode) not always reflected in DCSR
*/
if (((dsr & ECPP_IRQ_ST) == 0) ||
dcsr = 0;
} else {
goto unclaimed;
}
}
/* the intr is for us - check all possible interrupt sources */
if (dcsr & DCSR_ERR_PEND) {
/* we are expecting a data transfer interrupt */
/*
* some kind of DMA error
*/
}
}
return (DDI_INTR_CLAIMED);
}
return (DDI_INTR_CLAIMED);
}
if (COMPAT_PIO(pp)) {
return (DDI_INTR_CLAIMED);
}
/* does peripheral need attention? */
return (DDI_INTR_CLAIMED);
}
pp->intr_spurious++;
/*
* The following procedure tries to prevent soft hangs
* in event of peripheral/superio misbehaviour:
* if number of unexpected interrupts in the last SPUR_PERIOD ns
* exceeded SPUR_CRITICAL, then shut up interrupts
*/
/* last unexpected interrupt was long ago */
} else {
/* last unexpected interrupt was recently */
}
} else {
}
"isr:unknown: dcsr=%x ecr=%x dsr=%x dcr=%x\nmode=%x phase=%x\n",
return (DDI_INTR_CLAIMED);
pp->intr_spurious++;
"isr:UNCL: dcsr=%x ecr=%x dsr=%x dcr=%x\nmode=%x phase=%x\n",
return (DDI_INTR_UNCLAIMED);
}
/*
* M1553 intr handler
*/
static uint_t
{
int retval = DDI_INTR_UNCLAIMED;
/* Centronics or Compat PIO transfer */
if (COMPAT_PIO(pp)) {
return (ecpp_pio_ihdlr(pp));
}
/* Centronics or Compat DMA transfer */
if (COMPAT_DMA(pp) ||
return (ecpp_dma_ihdlr(pp));
}
}
/* Nibble or ECP backchannel request? */
return (ecpp_nErr_ihdlr(pp));
}
return (retval);
}
/*
* DMA completion interrupt handler
*/
static uint_t
{
/* we are expecting a data transfer interrupt */
/* Intr generated while invoking TFIFO mode. Exit */
pp->tfifo_intr = 0;
return (DDI_INTR_CLAIMED);
}
}
} else {
/*
* fifo_timer() will do the cleanup when the FIFO drains
*/
tm = 0; /* no use in waiting if FIFO is already empty */
} else {
}
}
/*
* Stop the DMA transfer timeout timer
* this operation will temporarily give up the mutex,
* so we do it in the end of the handler to avoid races
*/
return (DDI_INTR_CLAIMED);
}
/*
* ecpp_pio_ihdlr() is a PIO interrupt processing routine
* It masks interrupts, updates statistics and initiates next byte transfer
*/
static uint_t
{
/* update statistics */
pp->ctxpio_obytes++;
/* disable nAck interrups */
/*
* If it was the last byte of the data block cleanup,
* otherwise trigger a soft interrupt to send the next byte
*/
"ecpp_pio_ihdlr: pp->joblen=%d,pp->ctx_cf=%d,\n",
} else {
if (pp->softintr_pending) {
"ecpp_pio_ihdlr:E: next byte in progress\n");
} else {
}
}
return (DDI_INTR_CLAIMED);
}
/*
* ecpp_pio_writeb() sends a byte using Centronics handshake
*/
static void
{
dcr |= ECPP_INTR_EN;
/* send the next byte */
/* Now Assert (neg logic) nStrobe */
}
/* Enable nAck interrupts */
}
}
/*
* Backchannel request interrupt handler
*/
static uint_t
{
return (DDI_INTR_UNCLAIMED);
}
return (DDI_INTR_CLAIMED);
}
/* mask nErr & nAck interrupts */
/* going reverse */
switch (pp->current_mode) {
case ECPP_ECP_MODE:
/*
* Peripheral asserts nPeriphRequest (nFault)
*/
break;
case ECPP_NIBBLE_MODE:
/*
* Event 18: Periph asserts nErr to indicate data avail
* Event 19: After waiting minimum pulse width,
* periph sets nAck high to generate an interrupt
*
* Interface is in Interrupt Phase
*/
break;
default:
return (DDI_INTR_UNCLAIMED);
}
return (DDI_INTR_CLAIMED);
}
/*
* Softintr handler does work according to softintr_flags:
* in case of ECPP_SOFTINTR_PIONEXT it sends next byte of PIO transfer
*/
static uint_t
{
if (!pp->softintr_pending) {
return (DDI_INTR_CLAIMED);
} else {
pp->softintr_pending = 0;
}
/*
* Sent next byte in PIO mode
*/
ecpp_reattempts = 0;
do {
break;
}
drv_usecwait(1);
}
/* if the peripheral still not recovered suspend the transfer */
"dsr=%x jl=%d cf_isr=%d\n",
/*
* if status signals are bad,
* put everything back on the wq.
*/
"ecpp_softintr:e1:unx_len=%d\n", unx_len);
} else {
"ecpp_softintr:e2:unx_len=%d\n", unx_len);
}
} else {
/* send the next one */
(void) ecpp_pio_writeb(pp);
}
}
return (DDI_INTR_CLAIMED);
}
/*
* Transfer clean-up:
* shut down the DMAC
* stop the transfer timer
* enable write queue
*/
static void
{
/*
* if we did not use the ioblock, the mblk that
* was used should be freed.
*/
}
/* The port is no longer active */
/* Stop the transfer timeout timer */
}
/*VARARGS*/
static void
{
static long last;
static char *lastfmt;
char msg_buffer[255];
if (!ecpp_debug) {
return;
}
/*
* This function is supposed to be a quick non-blockable
* wrapper for cmn_err(9F), which provides a sensible degree
* of debug message throttling. Not using any type of lock
* is a requirement, but this also leaves two static variables
* - last and lastfmt - unprotected. However, this will not do
* any harm to driver functionality, it can only weaken throttling.
* The following directive asks warlock to not worry about these
* variables.
*/
/*
* Don't print same error message too often.
*/
now = gethrestime_sec();
return;
}
/*
* Forward transfer timeout
*/
static void
ecpp_xfer_timeout(void *arg)
{
void *unx_addr;
if (pp->timeout_id == 0) {
return;
} else {
pp->timeout_id = 0;
}
if (COMPAT_PIO(pp)) {
/*
* PIO mode timeout
*/
/* turn off nAck interrupts */
pp->softintr_pending = 0;
if (unx_len > 0) {
} else {
return;
}
} else {
/*
* DMA mode timeout
*
* If DMAC fails to shut off, continue anyways and attempt
* to put untransfered data back on queue.
*/
"ecpp_xfer_timeout: failed dma_stop\n");
}
"ecpp_xfer_timeout: failed unbind\n");
}
/*
* if the bcr is zero, then DMA is complete and
* we are waiting for the fifo to drain. So let
* ecpp_fifo_timer() look after the clean up.
*/
if (unx_len == 0) {
return;
} else {
/* update statistics */
} else {
}
}
}
/* Following code is common for PIO and DMA modes */
}
/* mark the error status structure */
pp->fifo_timer_id = 0;
if (fifo_timer_id) {
(void) untimeout(fifo_timer_id);
}
}
static void
{
if (len == 0) {
return;
}
"ecpp_putback_untransfered: allocb FAILURE.\n");
return;
}
}
}
static uchar_t
{
int i, current_ecr;
for (i = ECPP_REG_WRITE_MAX_LOOP; i > 0; i--) {
/* mask off the lower two read-only bits */
return (SUCCESS);
}
return (FAILURE);
}
static uchar_t
{
int i;
for (i = ECPP_REG_WRITE_MAX_LOOP; i > 0; i--) {
/* compare only bits 0-4 (direction bit return 1) */
return (SUCCESS);
}
"(%d)dcr_write: dcr written =%x, dcr readback =%x\n",
i, dcr_byte, current_dcr);
return (FAILURE);
}
static uchar_t
{
return (SUCCESS);
}
/*
* The data transferred by the DMA engine goes through the FIFO,
* so that when the DMA counter reaches zero (and an interrupt occurs)
* the FIFO can still contain data. If this is the case, the ISR will
* schedule this callback to wait until the FIFO drains or a timeout occurs.
*/
static void
ecpp_fifo_timer(void *arg)
{
/*
* If the FIFO timer has been turned off, exit.
*/
if (pp->fifo_timer_id == 0) {
return;
} else {
pp->fifo_timer_id = 0;
}
/*
* If the FIFO is not empty restart timer. Wait FIFO_DRAIN_PERIOD
* (250 ms) and check FIFO_EMPTY bit again. Repeat until FIFO is
* empty or until 10 * FIFO_DRAIN_PERIOD expires.
*/
(((ecr & ECPP_FIFO_EMPTY) == 0) &&
"ecpp_fifo_timer(%d):FIFO not empty:ecr=%x\n",
++pp->ecpp_drain_counter;
return;
}
/*
* If the FIFO won't drain after 10 FIFO_DRAIN_PERIODs
* then don't wait any longer. Simply clean up the transfer.
*/
" clearing FIFO,can't wait:ecr=%x\n",
} else {
"ecpp_fifo_timer(%d):FIFO empty:ecr=%x\n",
}
pp->ecpp_drain_counter = 0;
}
/*
* Main section of routine:
* - stop the DMA transfer timer
* - update stats
* - if last mblk in queue, signal to close() & return to idle state
*/
/* Stop the DMA transfer timeout timer */
pp->timeout_id = 0;
/* data has drained from fifo, it is ok to free dma resource */
COMPAT_DMA(pp)) {
/* update residual */
/* update statistics */
} else {
}
/*
*/
if (--pp->dma_cookie_count > 0) {
/* process the next cookie */
&pp->dma_cookie);
/* process the next window */
&pp->dma_cookie,
"ecpp_fifo_timer: ddi_dma_getwin failed\n");
goto dma_done;
}
pp->dma_curwin++;
} else {
goto dma_done;
}
/* kick off new transfer */
"ecpp_fifo_timer: dma_start failed\n");
goto dma_done;
}
if (timeout_id) {
(void) untimeout(timeout_id);
}
return;
} else {
}
}
/*
* if we did not use the dmablock, the mblk that
* was used should be freed.
*/
}
/* The port is no longer active */
if (timeout_id) {
(void) untimeout(timeout_id);
}
}
/*
* In Compatibility mode, check if the peripheral is ready to accept data
*/
static uint8_t
{
return (SUCCESS);
return (FAILURE);
} else {
return (SUCCESS);
}
}
/*
* if the peripheral is not ready to accept data, write service routine
* periodically reschedules itself to recheck peripheral status
* and start data transfer as soon as possible
*/
static void
ecpp_wsrv_timer(void *arg)
{
if (pp->wsrv_timer_id == 0) {
return;
} else {
pp->wsrv_timer_id = 0;
}
}
/*
* Allocate a message indicating a backchannel request
* and put it on the write queue
*/
static int
{
return (FAILURE);
} else {
return (FAILURE);
}
return (SUCCESS);
}
}
/*
* Cancel the function scheduled with timeout(9F)
* This function is to be called with the mutex held
*/
static void
{
if (*id) {
*id = 0;
}
}
/*
* get prnio interface capabilities
*/
static uint_t
{
/* status (DSR) only makes sense in Centronics & Compat modes */
ifcap |= PRN_1284_STATUS;
}
return (ifcap);
}
/*
* Determine SuperI/O type
*/
static struct ecpp_hw_bind *
{
struct ecpp_hw_bind *hw_bind;
char *name;
int i;
hw_bind = &ecpp_hw_bind[i];
break;
}
}
return (hw_bind);
}
/*
*
* IEEE 1284 support routines:
* negotiation and termination;
* phase transitions;
* device ID;
*
*/
/*
* Interface initialization, abnormal termination into Compatibility mode
*
* Peripheral may be non-1284, so we set current mode to ECPP_CENTRONICS
*/
static void
{
/*
* Toggle the nInit signal if configured in ecpp.conf
* for most peripherals it is not needed
*/
}
}
/*
* ECP mode negotiation
*/
static int
{
/* ECP mode negotiation */
return (FAILURE);
/* Event 5: peripheral deasserts PError and Busy, asserts Select */
(ECPP_nBUSY | ECPP_SLCT)) {
(void) ecpp_1284_termination(pp);
return (FAILURE);
}
/* entered Setup Phase */
/* Event 30: host asserts nAutoFd */
/* Event 31: peripheral asserts PError */
(void) ecpp_1284_termination(pp);
return (FAILURE);
}
/* entered Forward Idle Phase */
/* successful negotiation into ECP mode */
return (SUCCESS);
}
/*
* Nibble mode negotiation
*/
static int
{
return (FAILURE);
}
/*
* If peripheral has data available, PE and nErr will
* be set low at Event 5 & 6.
*/
} else {
}
/* successful negotiation into Nibble mode */
pp->current_phase);
return (SUCCESS);
}
/*
* Wait ptimeout usec for periph to set 'mask' bits to 'val' state
*
* return value < 0 indicates timeout
*/
static int
{
drv_usecwait(1);
}
return (ptimeout);
}
/*
* 1284 negotiation Events 0..6
* required mode is indicated by extensibility request value
*
* After successful negotiation SUCCESS is returned and
* current mode is set according to xreq,
* otherwise FAILURE is returned and current mode is set to
* either COMPAT (1284 periph) or CENTRONICS (non-1284 periph)
*
* Current phase must be set by the caller (mode-specific negotiation)
*
* If rdsr is not NULL, DSR value after Event 6 is stored here
*/
static int
{
int xflag;
/* negotiation should start in Compatibility mode */
(void) ecpp_1284_termination(pp);
/* Set host into Compat mode */
/* Event 0: host sets extensibility request on data lines */
/* Event 1: host deassert nSelectin and assert nAutoFd */
/*
* Event 2: peripheral asserts nAck, deasserts nFault,
* asserts Select, asserts PError
*/
/* peripheral is not 1284-compliant */
(void) ecpp_1284_termination(pp);
return (FAILURE);
}
/*
* Event 3: host asserts nStrobe, latching extensibility value into
* peripherals input latch.
*/
/*
* Event 4: hosts deasserts nStrobe and nAutoFD to acknowledge that
* it has recognized an 1284 compatible peripheral
*/
/*
* Event 5: Peripheral confirms it supports requested extension
* For Nibble mode Xflag must be low, otherwise it must be high
*/
/*
* Event 6: Peripheral sets nAck high
* indicating that status lines are valid
*/
/* Something wrong with peripheral */
(void) ecpp_1284_termination(pp);
return (FAILURE);
}
/* Extensibility value is not supported */
(void) ecpp_1284_termination(pp);
return (FAILURE);
}
if (rdsr) {
}
return (SUCCESS);
}
/*
* 1284 Termination: Events 22..28 - set link to Compatibility mode
*
* This routine is not designed for Immediate termination,
* caller must take care of waiting for a valid state,
* (in particular, in ECP mode current phase must be Forward Idle)
* otherwise interface will be reinitialized
*
* In case of Valid state termination SUCCESS is returned and
* current_mode is ECPP_COMPAT_MODE, current phase is ECPP_PHASE_C_IDLE
* Otherwise interface is reinitialized, FAILURE is returned and
* current mode is ECPP_CENTRONICS, current phase is ECPP_PHASE_C_IDLE
*/
static int
{
return (SUCCESS);
}
/* Set host into Compat mode, interrupts disabled */
/*
* EPP mode uses simple nInit pulse for termination
*/
if (previous_mode == ECPP_EPP_MODE) {
/* Event 68: host sets nInit low */
/* Event 69: host sets nInit high */
goto endterm;
}
/* terminate peripheral to Compat mode */
/* Event 22: hosts sets nSelectIn low and nAutoFd high */
/* Event 23: peripheral deasserts nFault and nBusy */
/* Event 24: peripheral asserts nAck */
ECPP_nERR, 35000) < 0) {
return (FAILURE);
}
/* Event 25: hosts sets nAutoFd low */
/* Event 26: the peripheral puts itself in Compatible mode */
/* Event 27: peripheral deasserts nAck */
return (FAILURE);
}
/* Event 28: hosts deasserts nAutoFd */
/* Compatible mode Idle Phase */
return (SUCCESS);
}
/*
* Initiate ECP backchannel DMA transfer
*/
static uchar_t
{
/*
* hardware generates cycles to receive data from the peripheral
* we only need to read from FIFO
*/
/*
* If user issued read(2) of rev_resid bytes, xfer exactly this amount
* unless it exceeds ECP_REV_BLKSZ_MAX; otherwise try to read
* ECP_REV_BLKSZ_MAX or at least ECP_REV_BLKSZ bytes
*/
} else {
}
/*
* Allocate mblk for data, make max 2 attepmts:
* if len bytes block fails, try our block size
*/
"ecp_periph2host: failed allocb(%d)\n", len);
if (len > ECP_REV_BLKSZ) {
len = ECP_REV_BLKSZ;
} else {
break;
}
}
goto fail;
}
goto fail;
}
/*
* there are two problems with defining ECP backchannel xfer timeout
*
* a) IEEE 1284 allows infinite time between backchannel bytes,
* but we must stop at some point to send the data upstream,
* look if any forward transfer requests are pending, etc;
* all that done, we can continue with backchannel data;
*
* b) we don`t know how much data peripheral has;
* DMA counter is set to our buffer size, which can be bigger
* than needed - in this case a timeout must detect this;
*
* The timeout we schedule here serves as both the transfer timeout
* and a means of detecting backchannel stalls; in fact, there are
* two timeouts in one:
*
* equals the time needed to transfer the whole buffer
* (but not less than ECP_REV_MINTOUT ms); if it occurs,
* DMA is stopped and the data is sent upstream;
*
* - backchannel watchdog, which would look at DMA counter
* every rev_watchdog ms and stop the transfer only
* if the counter hasn`t changed since the last time;
* otherwise it would save DMA counter value and restart itself;
*
* transfer timeout is a multiple of rev_watchdog
* and implemented as a downward counter
*
* on Grover, we can`t access DMAC registers while DMA is in flight,
* so we can`t have watchdog on Grover, only timeout
*/
/* calculate number of watchdog invocations equal to the xfer timeout */
#if defined(__x86)
#else
#endif
"xfer_time=%d wdog=%d cnt=%d\n",
return (SUCCESS);
fail:
if (mp) {
}
return (FAILURE);
}
/*
* ECP backchannel read timeout
* implements both backchannel watchdog and transfer timeout in ECP mode
* if the transfer is still in progress, reschedule itself,
* otherwise call completion routine
*/
static void
ecpp_ecp_read_timeout(void *arg)
{
if (pp->timeout_id == 0) {
return;
} else {
pp->timeout_id = 0;
}
if (--pp->rev_timeout_cnt == 0) {
/*
* Transfer timed out
*/
} else {
/*
* Backchannel watchdog:
* look if DMA made any progress from the last time
*/
/*
* No progress - stop the transfer and send
* whatever has been read so far up the stream
*/
} else {
/*
* Something was transferred - restart ourselves
*/
}
}
}
/*
* ECP backchannel read completion:
* stop the DMA, free DMA resources and send read data upstream
*/
static void
{
/*
* Stop the transfer and unbind DMA handle
*/
}
}
/* clean up and update statistics */
/*
* Send the read data up the stream
*/
} else {
}
}
/* if bytes left in the FIFO another transfer is needed */
(void) ecpp_backchan_req(pp);
}
}
/*
* Read one byte in the Nibble mode
*/
static uchar_t
{
int i;
/*
* One byte is made of two nibbles
*/
for (i = 0; i < 2; i++) {
/* Event 7, 12: host asserts nAutoFd to move to read a nibble */
/* Event 8: peripheral puts data on the status lines */
/* Event 9: peripheral asserts nAck, data available */
"nibble_periph2host(%d): failed event 9 %x\n",
(void) ecpp_1284_termination(pp);
return (FAILURE);
}
/* Event 10: host deasserts nAutoFd to say it grabbed data */
/* (2) Event 13: peripheral asserts PE - end of data phase */
/* Event 11: peripheral deasserts nAck to finish handshake */
"nibble_periph2host(%d): failed event 11 %x\n",
(void) ecpp_1284_termination(pp);
return (FAILURE);
}
}
/* extract data byte from two nibbles - optimized formula */
return (SUCCESS);
}
/*
* process data transfers requested by the peripheral
*/
static uint_t
{
return (SUCCESS);
}
switch (pp->backchannel) {
case ECPP_CENTRONICS:
/* no backchannel */
return (SUCCESS);
case ECPP_NIBBLE_MODE:
/*
* Event 20: Host sets nAutoFd high to ack request
*/
/* Event 21: Periph sets PError low to ack host */
"ecpp_periph2host: failed event 21 %x\n",
(void) ecpp_1284_termination(pp);
return (FAILURE);
}
/* this routine will read the data in Nibble mode */
return (ecpp_idle_phase(pp));
case ECPP_ECP_MODE:
return (FAILURE);
}
case ECPP_DIAG_MODE: {
int i;
return (SUCCESS);
}
/* allocate the FIFO size */
"ecpp_periph2host: allocb FAILURE.\n");
return (FAILURE);
}
/*
* For the time being just read it byte by byte
*/
i = ECPP_FIFO_SZ;
}
"ecpp_periph2host: sending %d bytes\n",
return (SUCCESS);
} else {
"ecpp_periph2host: !canputnext data lost\n");
return (FAILURE);
}
}
default:
return (FAILURE);
}
}
/*
* Negotiate from ECP Forward Idle to Reverse Idle Phase
*
*/
static int
{
/* place port into PS2 mode */
/* set direction bit (DCR3-0 must be 0100 - National) */
/* enable hardware assist */
/* Event 39: host sets nInit low */
/* Event 40: peripheral sets PError low */
return (SUCCESS);
}
/*
* Negotiate from ECP Reverse Idle to Forward Idle Phase
*
*/
static int
{
/* Event 47: host deasserts nInit */
/*
* Event 48: peripheral deasserts nAck
* Event 49: peripheral asserts PError
*/
(void) ecpp_1284_termination(pp);
return (FAILURE);
}
/* place port into PS2 mode */
/* clear direction bit */
/* reenable hardware assist */
return (SUCCESS);
}
/*
* Default negotiation chooses the best mode supported by peripheral
* Note that backchannel mode may be different from forward mode
*/
static void
{
/* 1284 compatible device */
return;
/* 1284 compatible device */
} else {
/* Centronics device */
}
}
/*
* Negotiate to the mode indicated by newmode
*/
static int
{
/* any other mode is impossible */
return (SUCCESS);
}
/* termination from ECP is only allowed from the Forward Idle Phase */
/* this may break into Centronics */
(void) ecp_reverse2forward(pp);
}
switch (newmode) {
case ECPP_CENTRONICS:
(void) ecpp_1284_termination(pp);
/* put superio into PIO mode */
return (SUCCESS);
case ECPP_COMPAT_MODE:
/* ECPP_COMPAT_MODE should support Nibble as a backchannel */
return (SUCCESS);
} else {
return (FAILURE);
}
}
return (SUCCESS);
} else {
return (FAILURE);
}
case ECPP_NIBBLE_MODE:
return (FAILURE);
}
return (SUCCESS);
case ECPP_ECP_MODE:
return (FAILURE);
return (FAILURE);
}
/*
* National says CTR[3:0] should be 0100b before moving to 011
*/
return (FAILURE);
}
return (SUCCESS);
case ECPP_DIAG_MODE:
/*
* In DIAG mode application can do nasty things(e.g drive pins)
* To keep peripheral sane, terminate to Compatibility mode
*/
(void) ecpp_1284_termination(pp);
/* put superio into TFIFO mode */
return (FAILURE);
}
return (SUCCESS);
default:
"ecpp_mode_negotiation: mode %d not supported\n", newmode);
return (FAILURE);
}
}
/*
* Standard (9.1): Peripheral data is available only when the host places
* the interface in a mode capable of peripheral-to-host data transfer.
* This requires the host periodically to place the interface in such a mode.
* Polling can be eliminated by leaving the interface in an 1284 idle phase.
*/
static uchar_t
{
/*
* If there is no space on the read queue, do not reverse channel
*/
return (SUCCESS);
}
switch (pp->backchannel) {
case ECPP_CENTRONICS:
case ECPP_COMPAT_MODE:
case ECPP_DIAG_MODE:
/* nothing */
return (SUCCESS);
case ECPP_NIBBLE_MODE:
/*
* read as much data as possible, ending up in either
* Reverse Idle or Host Busy Data Available phase
*/
break;
}
/* put interface into Reverse Idle phase */
/*
* Event 7: host asserts nAutoFd
* enable nAck interrupt to get a backchannel request
*/
}
break;
case ECPP_ECP_MODE:
/*
* if data is already available, request the backchannel xfer
* otherwise stay in Forward Idle and enable nErr interrupts
*/
/* put interface into Forward Idle phase */
return (FAILURE);
}
/*
* if data already available, put backchannel request on the wq
* otherwise enable nErr interrupts
*/
(void) ecpp_backchan_req(pp);
} else {
}
return (SUCCESS);
default:
}
return (rval);
}
/*
* This routine will leave the port in ECPP_PHASE_NIBT_REVIDLE
* Due to flow control, though, it may stop at ECPP_PHASE_NIBT_AVAIL,
* and continue later as the user consumes data from the read queue
*
* The current phase should be NIBT_AVAIL or NIBT_NAVAIL
* If some events fail during transfer, termination puts link
* to Compatibility mode and FAILURE is returned
*/
static int
{
int i;
/*
* While data is available, read it in NIBBLE_REV_BLKSZ byte chunks
* and send up the stream
*/
/* see if there's space on the queue */
"read_nibble_backchan: canputnext failed\n");
return (SUCCESS);
}
"read_nibble_backchan: allocb failed\n");
return (SUCCESS);
}
/* read a chunk of data from the peripheral byte by byte */
i = NIBBLE_REV_BLKSZ;
break;
}
}
"read_nibble_backchan: sending %d bytes\n",
} else {
}
}
return (rval);
}
/*
* 'Request Device ID using nibble mode' negotiation
*/
static int
{
if (ecpp_1284_negotiation(pp,
return (FAILURE);
}
/*
* If peripheral has data available, PE and nErr will
* be set low at Event 5 & 6.
*/
} else {
}
pp->current_phase);
/* successful negotiation into Nibble mode */
return (SUCCESS);
}
/*
* Read 1284 device ID sequence
*
* This function should be called two times:
* 1) ecpp_getdevid(pp, NULL, &len) - to retrieve ID length;
* 2) ecpp_getdevid(pp, buffer, &len) - to read len bytes into buffer
*
* After 2) port is in Compatible mode
* If the caller fails to make second call, it must reset port to Centronics
*
*/
static int
{
int i;
switch (mode) {
case ECPP_NIBBLE_MODE:
/* negotiate only if neccessary */
return (EIO);
}
}
return (EIO);
}
/*
* Event 14: Host tristates data bus, peripheral
* asserts nERR if data available, usually the
* status bits (7-0) and requires two reads since
* only nibbles are transfered.
*/
/*
* first two bytes are the length of the sequence
* (incl. these bytes)
* first byte is MSB
*/
"ecpp_getdevid: id length read error\n");
return (EIO);
}
"ecpp_getdevid: id length = %d\n", *lenp);
if (*lenp < 2) {
return (EIO);
}
} else {
/*
* read the rest of the data
*/
i = *lenp;
break;
i--;
}
"ecpp_getdevid: read %d bytes\n", *lenp - i);
/*
* 1284: After receiving the sequence, the host is
* required to return the link to the Compatibility mode
*/
(void) ecpp_1284_termination(pp);
}
break;
/* Other modes are not yet supported */
default:
return (EINVAL);
}
return (0);
}
/*
* Various hardware support
*
* First define some stubs for functions that do nothing
*/
/*ARGSUSED*/
static void
{
}
/*ARGSUSED*/
static void
{
}
#if defined(__x86)
static size_t
{
int count;
return (count);
}
#endif
/*
*
* National PC87332 and PC97317 SuperIOs support routines
* These chips are used in PCI-based Darwin, Quark, Quasar, Excalibur
* and use EBus DMA facilities (Cheerio or RIO)
*
*/
static int
{
sizeof (struct config_reg), &acc_attr,
goto fail;
}
!= DDI_SUCCESS) {
goto fail;
}
!= DDI_SUCCESS) {
goto fail;
}
sizeof (struct cheerio_dma_reg), &acc_attr,
goto fail;
}
return (SUCCESS);
fail:
return (FAILURE);
}
static void
{
}
}
}
}
}
static uint8_t
{
return (retval);
}
static void
{
/*
* second write to this register is needed. the register behaves as
* a fifo. the first value written goes to the data register. the
* second write pushes the initial value to the register indexed.
*/
}
static int
{
/* ECP DMA configuration bit (PMC4) must be set */
if (!(pmc & PC87332_PMC_ECP_DMA_CONFIG)) {
}
/*
* The Parallel Port Multiplexor pins must be driven.
* Check to see if FCR3 is zero, if not clear FCR3.
*/
if (fcr & PC87332_FCR_PPM_FLOAT_CTL) {
}
/*
* clear bits 3-0 in CTR (aka DCR) prior to enabling ECP mode
* CTR5 can not be cleared in SPP mode, CTR5 will return 1.
* "FAILURE" in this case is ok. Better to use dcr_write()
* to ensure reliable writing to DCR.
*/
}
/* enable ECP mode, level intr (note that DCR bits 3-0 == 0x0) */
/* put SuperIO in initial state */
}
return (FAILURE);
}
/* we are in centronic mode */
/* in compatible mode with no data transfer in progress */
return (SUCCESS);
}
/*
* A new mode was set, do some mode specific reconfiguration
* in this case - set interrupt characteristic
*/
static void
{
if (COMPAT_PIO(pp)) {
} else {
}
}
static int
{
return (FAILURE);
}
return (FAILURE);
} else {
return (SUCCESS);
}
}
static void
{
}
}
/*
* OBP should configure the PC97317 such that it does not need further
* configuration. Upon sustaining, it may be necessary to examine
* or change the configuration registers. This routine is left in
* the file for that purpose.
*/
static int
{
/* set the logical device name */
/* SPP Compatibility */
/* low interrupt polarity */
/* ECP mode */
}
}
#ifdef DEBUG
#endif /* DEBUG */
return (SUCCESS);
}
/*
* A new mode was set, do some mode specific reconfiguration
* in this case - set interrupt polarity
*/
static void
{
/* set the logical device name */
} else {
}
}
static void
{
/* mask Cheerio interrupts */
}
static void
{
/* unmask Cheerio interrupts */
}
static int
{
} else {
}
return (SUCCESS);
}
/*
* Note: BCR is reset to 0, so counter should always be read before dma_stop
*/
static int
{
/* disable DMA and byte counter */
/* ACK and disable the TC interrupt */
DCSR_TC | DCSR_TCI_DIS);
/* read DMA count if requested */
if (countp) {
}
SET_DMAC_BCR(pp, 0);
/* turn off SuperIO's DMA */
return (FAILURE);
}
/* Disable SuperIO interrupts and DMA */
}
static size_t
{
return (GET_DMAC_BCR(pp));
}
/*
* Reset the DCSR by first setting the RESET bit to 1. Poll the
* DCSR_CYC_PEND bit to make sure there are no more pending DMA cycles.
* If there are no more pending cycles, clear the RESET bit.
*/
static void
{
int timeout = DMAC_RESET_TIMEOUT;
if (timeout == 0) {
break;
} else {
drv_usecwait(1);
timeout--;
}
}
SET_DMAC_CSR(pp, 0);
}
/*
*
* Grover Southbridge (M1553) support routines
* Southbridge contains an Intel 8237 DMAC onboard which is used
*
*/
static int
{
goto fail;
}
!= DDI_SUCCESS) {
goto fail;
}
!= DDI_SUCCESS) {
goto fail;
}
return (SUCCESS);
fail:
return (FAILURE);
}
static void
{
}
}
}
}
#if defined(__x86)
static int
{
int nregs = 0;
!= DDI_SUCCESS) {
goto fail;
}
!= DDI_SUCCESS) {
goto fail;
} else
} else {
}
return (SUCCESS);
fail:
return (FAILURE);
}
static void
{
}
}
}
#endif
static uint8_t
{
return (retval);
}
static void
{
}
static int
{
/* Unlock configuration regs with "key sequence" */
/* set FIFO threshold 1 and ECP mode, preserve bit 7 (IRQ polarity) */
/* lock configuration regs with key */
/* Set ECR, DCR in known state */
return (SUCCESS);
}
#if defined(__x86)
static int
{
}
return (SUCCESS);
}
#endif
/*
* dma8237_dma_start() programs the selected 8 bit channel
* of DMAC1 with the dma cookie. pp->dma_cookie must
* be set before this routine is called.
*/
static int
{
/* At this point Southbridge has not yet asserted DREQ */
/* set mode to read-from-memory. */
DMAMODE_READ | chn);
} else {
DMAMODE_WRITE | chn);
}
/*
* M1553 chip does not permit to access DMA register banks
* while DMA is in flight. As a result, ecpp and floppy drivers
* can potentially corrupt each other's DMA. The interlocking mechanism
* is provided by a parent nexus driver (isadma), which is enabled
* indirectly through a DMAC1_ALLMASK register access:
*
* writing a non-zero value to this register enters a lock,
* writing zero releases the lock.
*
* DMA transfer must only occur after entering a lock.
* If the lock is already owned by other driver, we will block.
*
* The following operation unmasks our channel and masks all others
*/
return (SUCCESS);
}
static int
{
/* stop DMA */
/* reset the channel mask so we can issue PIO's to our device */
}
/* read DMA count if requested */
if (countp) {
(*countp)++; /* need correction for reverse xfers */
}
}
return (SUCCESS);
}
#if defined(__x86)
static int
{
struct ddi_dmae_req dmaereq;
!= DDI_SUCCESS)
return (SUCCESS);
}
static int
{
/* stop DMA */
return (FAILURE);
/* read DMA count if requested */
if (countp) {
}
return (SUCCESS);
}
#endif
/* channel must be masked */
static void
{
case DMAE_CH0:
break;
case DMAE_CH1:
break;
case DMAE_CH2:
break;
case DMAE_CH3:
break;
default:
return;
}
}
/*
* This function may be useful during debugging,
* so we leave it in, but do not include in the binary
*/
#ifdef INCLUDE_DMA8237_READ_ADDR
static uint32_t
{
case DMAE_CH0:
break;
case DMAE_CH1:
break;
case DMAE_CH2:
break;
case DMAE_CH3:
break;
default:
return (NULL);
}
return (rval);
}
#endif
static void
{
uint16_t *p;
case DMAE_CH0:
break;
case DMAE_CH1:
break;
case DMAE_CH2:
break;
case DMAE_CH3:
break;
default:
return;
}
}
static uint32_t
{
uint16_t *p;
case DMAE_CH0:
break;
case DMAE_CH1:
break;
case DMAE_CH2:
break;
case DMAE_CH3:
break;
default:
return (NULL);
}
}
static void
{
}
static uint8_t
{
}
static size_t
{
cnt = 0;
else
cnt++;
return (cnt);
}
/*
*
* Kstat support routines
*
*/
static void
{
char buf[16];
/*
* Allocate, initialize and install interrupt counter kstat
*/
} else {
}
/*
* Allocate, initialize and install misc stats kstat
*/
sizeof (struct ecppkstat) / sizeof (kstat_named_t),
return;
}
#define EK_NAMED_INIT(name) \
}
static int
{
/*
* For the time being there is no point
* in supporting writable kstats
*/
if (rw == KSTAT_WRITE) {
return (EACCES);
}
return (0);
}
static int
{
/*
* For the time being there is no point
* in supporting writable kstats
*/
if (rw == KSTAT_WRITE) {
return (EACCES);
}
return (0);
}