e1000g_sw.h revision 6ad5fc39c6f3b123ae5588d60fc8dfe068e07bfc
/*
* This file is provided under a CDDLv1 license. When using or
* redistributing this file, you may do so under this license.
* In redistributing this file this license must be included
* and no other modification of this header file is permitted.
*
* CDDL LICENSE SUMMARY
*
* Copyright(c) 1999 - 2008 Intel Corporation. All rights reserved.
*
* The contents of this file are subject to the terms of Version
* 1.0 of the Common Development and Distribution License (the "License").
*
* You should have received a copy of the License with this software.
* You can obtain a copy of the License at
* See the License for the specific language governing permissions
* and limitations under the License.
*/
/*
* Copyright 2008 Sun Microsystems, Inc. All rights reserved.
* Use is subject to license terms of the CDDLv1.
*/
#ifndef _E1000G_SW_H
#define _E1000G_SW_H
#pragma ident "%Z%%M% %I% %E% SMI"
#ifdef __cplusplus
extern "C" {
#endif
/*
* **********************************************************************
* Module Name: *
* e1000g_sw.h *
* *
* Abstract: *
* This header file contains Software-related data structures *
* definitions. *
* *
* **********************************************************************
*/
#include <sys/mac_ether.h>
#include <sys/ethernet.h>
#include "e1000_api.h"
#define JUMBO_FRAG_LENGTH 4096
#define MAX_NUM_MULTICAST_ADDRESSES 256
#define MAX_TX_DESC_PER_PACKET 16
/*
* constants used in setting flow control thresholds
*/
#define E1000_PBA_MASK 0xffff
#define E1000_PBA_SHIFT 10
#define MAX_NUM_TX_DESCRIPTOR 4096
#define MAX_NUM_RX_DESCRIPTOR 4096
#define MAX_NUM_RX_FREELIST 4096
#define MAX_NUM_TX_FREELIST 4096
#define MAX_RX_LIMIT_ON_INTR 4096
#define MAX_RX_INTR_DELAY 65535
#define MAX_RX_INTR_ABS_DELAY 65535
#define MAX_TX_INTR_DELAY 65535
#define MAX_TX_INTR_ABS_DELAY 65535
#define MAX_INTR_THROTTLING 65535
#define MIN_NUM_TX_DESCRIPTOR 80
#define MIN_NUM_RX_DESCRIPTOR 80
#define MIN_NUM_RX_FREELIST 64
#define MIN_NUM_TX_FREELIST 80
#define MIN_RX_LIMIT_ON_INTR 16
#define MIN_RX_INTR_DELAY 0
#define MIN_RX_INTR_ABS_DELAY 0
#define MIN_TX_INTR_DELAY 0
#define MIN_TX_INTR_ABS_DELAY 0
#define MIN_INTR_THROTTLING 0
#define MIN_RX_BCOPY_THRESHOLD 0
#define MIN_TX_RECYCLE_THRESHOLD 0
#define DEFAULT_NUM_RX_DESCRIPTOR 2048
#define DEFAULT_NUM_TX_DESCRIPTOR 2048
#define DEFAULT_NUM_RX_FREELIST 4096
#define DEFAULT_NUM_TX_FREELIST 2304
#define DEFAULT_RX_LIMIT_ON_INTR 128
#ifdef __sparc
#define MAX_INTR_PER_SEC 7100
#define MIN_INTR_PER_SEC 3000
#define DEFAULT_INTR_PACKET_LOW 5
#define DEFAULT_INTR_PACKET_HIGH 128
#define DEFAULT_TX_RECYCLE_THRESHOLD 512
#else
#define MAX_INTR_PER_SEC 15000
#define MIN_INTR_PER_SEC 4000
#define DEFAULT_INTR_PACKET_LOW 10
#define DEFAULT_INTR_PACKET_HIGH 48
#endif
#define DEFAULT_RX_INTR_DELAY 0
#define DEFAULT_RX_INTR_ABS_DELAY 64
#define DEFAULT_TX_INTR_DELAY 64
#define DEFAULT_TX_INTR_ABS_DELAY 64
#define DEFAULT_RX_BCOPY_THRESHOLD 128
#define DEFAULT_TX_BCOPY_THRESHOLD 512
#define DEFAULT_TX_RECYCLE_NUM 64
#define DEFAULT_TX_UPDATE_THRESHOLD 256
#define DEFAULT_TX_NO_RESOURCE 6
#define DEFAULT_TX_INTR_ENABLE 1
#define DEFAULT_FLOW_CONTROL 3
#define DEFAULT_MASTER_LATENCY_TIMER 0 /* BIOS should decide */
/* which is normally 0x040 */
/*
*/
#define E1000_RX_BUFFER_SIZE_2K (2048)
#define E1000_RX_BUFFER_SIZE_4K (4096)
#define E1000_RX_BUFFER_SIZE_8K (8192)
#define E1000_RX_BUFFER_SIZE_16K (16384)
#define E1000_TX_BUFFER_SIZE_2K (2048)
#define E1000_TX_BUFFER_SIZE_4K (4096)
#define E1000_TX_BUFFER_SIZE_8K (8192)
#define E1000_TX_BUFFER_SIZE_16K (16384)
#define FORCE_BCOPY_EXCEED_FRAGS 0x1
#define FORCE_BCOPY_UNDER_SIZE 0x2
#define E1000G_RX_SW_FREE 0x0
#define E1000G_RX_SW_SENDUP 0x1
#define E1000G_RX_SW_STOP 0x2
#define E1000G_RX_SW_DETACH 0x3
/*
* definitions for smartspeed workaround
*/
/* or 30 seconds */
/* or 6 seconds */
/*
* Definitions for module_info.
*/
/*
* Defined for IP header alignment. We also need to preserve space for
* VLAN tag (4 bytes)
*/
#define E1000G_IPALIGNROOM 6
#define E1000G_IPALIGNPRESERVEROOM 64
/*
* bit flags for 'attach_progress' which is a member variable in struct e1000g
*/
/*
* Speed and Duplex Settings
*/
#define GDIAG_10_HALF 1
#define GDIAG_10_FULL 2
#define GDIAG_100_HALF 3
#define GDIAG_100_FULL 4
#define GDIAG_1000_FULL 6
#define GDIAG_ANY 7
/*
* Coexist Workaround RP: 07/04/03
* 82544 Workaround : Co-existence
*/
#define ROUNDOFF 0x1000
/*
* Defines for Jumbo Frame
*/
#define FRAME_SIZE_UPTO_2K 2048
#define FRAME_SIZE_UPTO_4K 4096
#define FRAME_SIZE_UPTO_8K 8192
#define FRAME_SIZE_UPTO_16K 16384
#define FRAME_SIZE_UPTO_9K 9234
/* The sizes (in bytes) of a ethernet packet */
#define ETHERNET_FCS_SIZE 4
#define MAXIMUM_ETHERNET_PACKET_SIZE \
#define MINIMUM_ETHERNET_PACKET_SIZE \
#define CRC_LENGTH ETHERNET_FCS_SIZE
/* Defines for Tx stall check */
#define E1000G_STALL_WATCHDOG_COUNT 8
#define MAX_TX_LINK_DOWN_TIMEOUT 8
/* Defines for DVMA */
#ifdef __sparc
#define E1000G_DEFAULT_DVMA_PAGE_NUM 2
#endif
/*
* Loopback definitions
*/
#define E1000G_LB_NONE 0
#define E1000G_LB_EXTERNAL_1000 1
#define E1000G_LB_EXTERNAL_100 2
#define E1000G_LB_EXTERNAL_10 3
#define E1000G_LB_INTERNAL_PHY 4
/*
* Private dip list definitions
*/
#define E1000G_PRIV_DEVI_ATTACH 0x0
#define E1000G_PRIV_DEVI_DETACH 0x1
/*
* QUEUE_INIT_LIST -- Macro which will init ialize a queue to NULL.
*/
#define QUEUE_INIT_LIST(_LH) \
/*
* IS_QUEUE_EMPTY -- Macro which checks to see if a queue is empty.
*/
#define IS_QUEUE_EMPTY(_LH) \
/*
* QUEUE_GET_HEAD -- Macro which returns the head of the queue, but does
* not remove the head from the queue.
*/
/*
* QUEUE_REMOVE_HEAD -- Macro which removes the head of the head of a queue.
*/
#define QUEUE_REMOVE_HEAD(_LH) \
{ \
{ \
} \
}
/*
* QUEUE_POP_HEAD -- Macro which will pop the head off of a queue (list),
* and return it (this differs from QUEUE_REMOVE_HEAD only in
* the 1st line).
*/
#define QUEUE_POP_HEAD(_LH) \
{ \
if (ListElem) \
{ \
} \
}
/*
* QUEUE_GET_TAIL -- Macro which returns the tail of the queue, but does not
* remove the tail from the queue.
*/
/*
* QUEUE_PUSH_TAIL -- Macro which puts an element at the tail (end) of the queue
*/
{ \
(PSINGLE_LIST_LINK)(_E); \
} else { \
} \
/*
* QUEUE_PUSH_HEAD -- Macro which puts an element at the head of the queue.
*/
{ \
} \
/*
* QUEUE_GET_NEXT -- Macro which returns the next element linked to the
* current element.
*/
/*
* QUEUE_APPEND -- Macro which appends a queue to the tail of another queue
*/
} else { \
} \
}
/*
* Property lookups
*/
DDI_PROP_DONTPASS, (n))
DDI_PROP_DONTPASS, (n), -1)
/*
* Shorthand for the NDD parameters
*/
#ifdef E1000G_DEBUG
/*
* E1000G-specific ioctls ...
*/
+ 'K') << 4) + 'G') << 4)
/*
* These diagnostic IOCTLS are enabled only in DEBUG drivers
*/
#define E1000G_PP_SPACE_REG 0 /* PCI memory space */
typedef struct {
/* input for poke */
#endif /* E1000G_DEBUG */
/*
* (Internal) return values from ioctl subroutines
*/
enum ioc_reply {
IOC_DONE, /* OK, reply sent */
IOC_ACK, /* OK, just send ACK */
IOC_REPLY /* OK, just send reply */
};
/*
* Named Data (ND) Parameter Management Structure
*/
typedef struct {
struct e1000g *ndp_instance;
char *ndp_name;
} nd_param_t;
/*
* NDD parameter indexes, divided into:
*
* read-only parameters describing the hardware's capabilities
* read-write parameters controlling the advertised capabilities
* read-only parameters describing the partner's capabilities
* read-write parameters controlling the force speed and duplex
* read-only parameters describing the link state
* read-only parameters describing the driver properties
* read-write parameters controlling the driver properties
*/
enum {
};
/*
* The entry of the private dip list
*/
typedef struct _private_devi_list {
struct _private_devi_list *next;
/*
* A structure that points to the next entry in the queue.
*/
typedef struct _SINGLE_LIST_LINK {
struct _SINGLE_LIST_LINK *Flink;
/*
* A "ListHead" structure that points to the head and tail of a queue
*/
typedef struct _LIST_DESCRIBER {
struct _SINGLE_LIST_LINK *volatile Flink;
struct _SINGLE_LIST_LINK *volatile Blink;
/*
* Address-Length pair structure that stores descriptor info
*/
typedef struct _sw_desc {
} sw_desc_t, *p_sw_desc_t;
typedef struct _desc_array {
typedef enum {
} dma_type_t;
typedef enum {
} chip_state_t;
typedef struct _dma_buffer {
/*
* Transmit Control Block (TCB), Ndis equiv of SWPacket This
* structure stores the additional information that is
* associated with every packet to be transmitted. It stores the
* message block pointer and the TBD addresses associated with
* the m_blk and also the link to the next tcb in the chain
*/
typedef struct _tx_sw_packet {
/* Link to the next tx_sw_packet in the list */
/*
* This structure is similar to the rx_sw_packet structure used
* for Ndis. This structure stores information about the 2k
* aligned receive buffer into which the FX1000 DMA's frames.
* This structure is maintained as a linked list of many
* receiver buffer pointers.
*/
typedef struct _rx_sw_packet {
/* Link to the next rx_sw_packet_t in the list */
struct _rx_sw_packet *next;
typedef struct _mblk_list {
} mblk_list_t, *p_mblk_list_t;
typedef struct _cksum_data {
} cksum_data_t;
typedef union _e1000g_ether_addr {
struct {
} reg;
struct {
} mac;
typedef struct _e1000g_stat {
#ifdef E1000G_DEBUG
#endif
#ifdef E1000G_DEBUG
#endif
#ifdef E1000G_DEBUG
#endif
typedef struct _e1000g_tx_ring {
/*
* Descriptor queue definitions
*/
struct e1000_tx_desc *tbd_area;
struct e1000_tx_desc *tbd_first;
struct e1000_tx_desc *tbd_last;
struct e1000_tx_desc *tbd_oldest;
struct e1000_tx_desc *tbd_next;
/*
* Software packet structures definitions
*/
/*
*/
/*
* Timer definitions for 82547
*/
/*
* reschedule when tx resource is available
*/
/*
* Statistics
*/
#ifdef E1000G_DEBUG
#endif
/*
* Pointer to the adapter
*/
typedef struct _e1000g_rx_ring {
/*
* Descriptor queue definitions
*/
struct e1000_rx_desc *rbd_area;
struct e1000_rx_desc *rbd_first;
struct e1000_rx_desc *rbd_last;
struct e1000_rx_desc *rbd_next;
/*
* Software packet structures definitions
*/
/*
* Statistics
*/
#ifdef E1000G_DEBUG
#endif
/*
* Pointer to the adapter
*/
typedef struct e1000g {
int instance;
struct e1000g_osdep osdep;
#ifndef NO_82542_SUPPORT
#endif
/*
* Rx and Tx packet count for interrupt adaptive setting
*/
/*
* The watchdog_lock must be held when updateing the
* timeout fields in struct e1000g, that is,
* watchdog_tid, watchdog_timer_started.
*/
/*
* The link_lock protects the link fields in struct e1000g,
* such as link_state, link_speed, link_duplex, link_complete, and
* link_tid.
*/
/*
* stopped while other functions change the hardware
* configuration of e1000g card, such as e1000g_reset(),
* e1000g_reset_hw() etc are executed.
*/
#ifdef __sparc
#endif
int intr_type;
int intr_cnt;
int intr_cap;
int tx_softint_pri;
/*
* NDD parameters
*/
/*
* FMA capabilities
*/
int fm_capabilities;
} e1000g_t;
/*
* Function prototypes
*/
#pragma inline(e1000_rar_set)
/*
* Global variables
*/
extern boolean_t e1000g_force_detach;
extern uint32_t e1000g_mblks_pending;
extern krwlock_t e1000g_rx_detach_lock;
#ifdef __cplusplus
}
#endif
#endif /* _E1000G_SW_H */