e1000g_sw.h revision 0f70fbf80d71251e7928b3122fb4848c2f92a5c6
/*
* This file is provided under a CDDLv1 license. When using or
* redistributing this file, you may do so under this license.
* In redistributing this file this license must be included
* and no other modification of this header file is permitted.
*
* CDDL LICENSE SUMMARY
*
* Copyright(c) 1999 - 2007 Intel Corporation. All rights reserved.
*
* The contents of this file are subject to the terms of Version
* 1.0 of the Common Development and Distribution License (the "License").
*
* You should have received a copy of the License with this software.
* You can obtain a copy of the License at
* See the License for the specific language governing permissions
* and limitations under the License.
*/
/*
* Copyright 2007 Sun Microsystems, Inc. All rights reserved.
* Use is subject to license terms of the CDDLv1.
*/
#ifndef _E1000G_SW_H
#define _E1000G_SW_H
#pragma ident "%Z%%M% %I% %E% SMI"
#ifdef __cplusplus
extern "C" {
#endif
/*
* **********************************************************************
* Module Name: *
* e1000g_sw.h *
* *
* Abstract: *
* This header file contains Software-related data structures *
* definitions. *
* *
* This driver runs on the following hardware: *
* - Wisemane based PCI gigabit ethernet adapters *
* *
* Environment: *
* Kernel Mode - *
* *
* **********************************************************************
*/
#ifdef DEBUG
#define e1000g_DEBUG
#endif
/*
* Solaris Multithreaded GLD wiseman PCI Ethernet Driver
*/
#include <sys/mac_ether.h>
#include <sys/ethernet.h>
#include "e1000_hw.h"
/*
* PCI Command Register Bit Definitions
* Configuration Space Header
*/
#ifdef __sparc
#ifdef _LP64
#else
#define DWORD_SWAP(value) \
#endif
#else
#endif
#define JUMBO_FRAG_LENGTH 4096
#define MAX_NUM_MULTICAST_ADDRESSES 256
#define MAX_TX_DESC_PER_PACKET 16
/*
* constants used in setting flow control thresholds
*/
#define E1000_PBA_MASK 0xffff
#define E1000_PBA_SHIFT 10
#define MAXNUMTXDESCRIPTOR 4096
#define MAXNUMRXDESCRIPTOR 4096
#define MAXNUMRXFREELIST 4096
#define MAXNUMTXSWPACKET 4096
#define MAXNUMRCVPKTONINTR 4096
#define MAXTXFRAGSLIMIT 1024
#define MAXTXINTERRUPTDELAYVAL 65535
#define MAXINTERRUPTTHROTTLINGVAL 65535
#define MAXTXRECYCLELOWWATER \
#define MINNUMTXDESCRIPTOR 80
#define MINNUMRXDESCRIPTOR 80
#define MINNUMRXFREELIST 64
#define MINNUMTXSWPACKET 80
#define MINNUMRCVPKTONINTR 16
#define MINTXFRAGSLIMIT 2
#define MINTXINTERRUPTDELAYVAL 0
#define MININTERRUPTTHROTTLINGVAL 0
#define MINRXBCOPYTHRESHOLD 0
#define DEFAULTNUMTXDESCRIPTOR 2048
#define DEFAULTNUMRXDESCRIPTOR 2048
#define DEFAULTNUMRXFREELIST 4096
#define DEFAULTNUMTXSWPACKET 2048
#define DEFAULTMAXNUMRCVPKTONINTR 256
#define DEFAULTTXFRAGSLIMIT 4
#define DEFAULTFLOWCONTROLVAL 3
#define DEFAULTTXINTERRUPTDELAYVAL 300
#define DEFAULTINTERRUPTTHROTTLINGVAL 0x225
/* needs this value to be 0 */
#define DEFAULTMASTERLATENCYTIMERVAL 0 /* BIOS should decide */
/* which is normally 0x040 */
#define DEFAULTRXBCOPYTHRESHOLD 0
#define DEFAULTTXBCOPYTHRESHOLD 512
#define DEFAULTTXRECYCLELOWWATER 64
#define DEFAULTTXRECYCLENUM 128
/*
*/
#define E1000_RX_BUFFER_SIZE_2K (2048)
#define E1000_RX_BUFFER_SIZE_4K (4096)
#define E1000_RX_BUFFER_SIZE_8K (8192)
#define E1000_RX_BUFFER_SIZE_16K (16384)
#define E1000_TX_BUFFER_SIZE_2K (2048)
#define E1000_TX_BUFFER_SIZE_4K (4096)
#define E1000_TX_BUFFER_SIZE_8K (8192)
#define E1000_TX_BUFFER_SIZE_16K (16384)
#define FORCE_BCOPY_EXCEED_FRAGS 0x1
#define FORCE_BCOPY_UNDER_SIZE 0x2
#define E1000G_RX_SW_FREE 0x0
#define E1000G_RX_SW_SENDUP 0x1
#define E1000G_RX_SW_DETACHED 0x2
/*
* By default it will print only to log
*/
#define DEFAULTDEBUGLEVEL 0x004
#define DEFAULTDISPLAYONLY 0
#define DEFAULTPRINTONLY 1
/*
* definitions for smartspeed workaround
*/
/* or 30 seconds */
/* or 6 seconds */
/*
* Definitions for module_info.
*/
/*
* Defined for IP header alignment. We also need to preserve space for
* VLAN tag (4 bytes)
*/
#define E1000G_IPALIGNROOM 6
#define E1000G_IPALIGNPRESERVEROOM 64
/*
* bit flags for 'attach_progress' which is a member variable in struct e1000g
*/
/*
* Speed and Duplex Settings
*/
#define GDIAG_10_HALF 1
#define GDIAG_10_FULL 2
#define GDIAG_100_HALF 3
#define GDIAG_100_FULL 4
#define GDIAG_1000_FULL 6
#define GDIAG_ANY 7
#define MAX_DEVICES 256
/*
* Coexist Workaround RP: 07/04/03
* 82544 Workaround : Co-existence
*/
#define ROUNDOFF 0x1000
/*
* Defines for Jumbo Frame
*/
#define FRAME_SIZE_UPTO_2K 2048
#define FRAME_SIZE_UPTO_4K 4096
#define FRAME_SIZE_UPTO_8K 8192
#define FRAME_SIZE_UPTO_16K 16384
#define FRAME_SIZE_UPTO_10K 10500
/*
* Max microsecond for ITR (Interrupt Throttling Register)
*/
#define E1000_ITR_MAX_MICROSECOND 0x3fff
/* Defines for Tx stall check */
#define E1000G_STALL_WATCHDOG_COUNT 8
#define MAX_TX_LINK_DOWN_TIMEOUT 8
/* Defines for DVMA */
#ifdef __sparc
#define E1000G_DEFAULT_DVMA_PAGE_NUM 2
#endif
/*
* Loopback definitions
*/
#define E1000G_LB_NONE 0
#define E1000G_LB_EXTERNAL_1000 1
#define E1000G_LB_EXTERNAL_100 2
#define E1000G_LB_EXTERNAL_10 3
#define E1000G_LB_INTERNAL_PHY 4
#define GET_ETHER_TYPE(ptr) (\
/*
* QUEUE_INIT_LIST -- Macro which will init ialize a queue to NULL.
*/
#define QUEUE_INIT_LIST(_LH) \
/*
* IS_QUEUE_EMPTY -- Macro which checks to see if a queue is empty.
*/
#define IS_QUEUE_EMPTY(_LH) \
/*
* QUEUE_GET_HEAD -- Macro which returns the head of the queue, but does
* not remove the head from the queue.
*/
/*
* QUEUE_REMOVE_HEAD -- Macro which removes the head of the head of a queue.
*/
#define QUEUE_REMOVE_HEAD(_LH) \
{ \
{ \
} \
}
/*
* QUEUE_POP_HEAD -- Macro which will pop the head off of a queue (list),
* and return it (this differs from QUEUE_REMOVE_HEAD only in
* the 1st line).
*/
#define QUEUE_POP_HEAD(_LH) \
{ \
if (ListElem) \
{ \
} \
}
/*
* QUEUE_GET_TAIL -- Macro which returns the tail of the queue, but does not
* remove the tail from the queue.
*/
/*
* QUEUE_PUSH_TAIL -- Macro which puts an element at the tail (end) of the queue
*/
{ \
(PSINGLE_LIST_LINK)(_E); \
} else { \
} \
/*
* QUEUE_PUSH_HEAD -- Macro which puts an element at the head of the queue.
*/
{ \
} \
/*
* QUEUE_GET_NEXT -- Macro which returns the next element linked to the
* current element.
*/
/*
* QUEUE_APPEND -- Macro which appends a queue to the tail of another queue
*/
} else { \
} \
}
/*
* Property lookups
*/
DDI_PROP_DONTPASS, (n))
DDI_PROP_DONTPASS, (n), -1)
/*
* Shorthand for the NDD parameters
*/
/*
* E1000G-specific ioctls ...
*/
+ 'K') << 4) + 'G') << 4)
/*
* These diagnostic IOCTLS are enabled only in DEBUG drivers
*/
#define E1000G_PP_SPACE_REG 0 /* PCI memory space */
typedef struct {
/* input for poke */
/*
* (Internal) return values from ioctl subroutines
*/
enum ioc_reply {
IOC_DONE, /* OK, reply sent */
IOC_ACK, /* OK, just send ACK */
IOC_REPLY /* OK, just send reply */
};
/*
* Named Data (ND) Parameter Management Structure
*/
typedef struct {
struct e1000g *ndp_instance;
char *ndp_name;
} nd_param_t;
/*
* NDD parameter indexes, divided into:
*
* read-only parameters describing the hardware's capabilities
* read-write parameters controlling the advertised capabilities
* read-only parameters describing the partner's capabilities
* read-write parameters controlling the force speed and duplex
* read-only parameters describing the link state
* read-only parameters describing the driver properties
* read-write parameters controlling the driver properties
*/
enum {
};
static struct ether_addr etherbroadcastaddr = {
0xff, 0xff, 0xff, 0xff, 0xff, 0xff
};
/*
* DMA access attributes <Little Endian Card>
*/
static ddi_device_acc_attr_t accattr = {
};
/*
* DMA access attributes for receive buffer <Big Endian> for Sparc
*/
#ifdef __sparc
static ddi_device_acc_attr_t accattr2 = {
};
#else
static ddi_device_acc_attr_t accattr2 = {
};
#endif
typedef struct _private_devi_list {
struct _private_devi_list *next;
/*
* A structure that points to the next entry in the queue.
*/
typedef struct _SINGLE_LIST_LINK {
struct _SINGLE_LIST_LINK *Flink;
/*
* A "ListHead" structure that points to the head and tail of a queue
*/
typedef struct _LIST_DESCRIBER {
struct _SINGLE_LIST_LINK *volatile Flink;
struct _SINGLE_LIST_LINK *volatile Blink;
/*
* Address-Length pair structure that stores descriptor info
*/
typedef struct _ADDRESS_LENGTH_PAIR {
typedef struct _DESCRIPTOR_PAIR {
} DESC_ARRAY, *PDESC_ARRAY;
typedef enum {
} dma_type_t;
typedef struct _dma_buffer {
/*
* Transmit Control Block (TCB), Ndis equiv of SWPacket This
* structure stores the additional information that is
* associated with every packet to be transmitted. It stores the
* message block pointer and the TBD addresses associated with
* the m_blk and also the link to the next tcb in the chain
*/
typedef struct _TX_SW_PACKET_ {
/* Link to the next TX_SW_PACKET in the list */
/*
* This structure is similar to the RX_SW_PACKET structure used
* for Ndis. This structure stores information about the 2k
* aligned receive buffer into which the FX1000 DMA's frames.
* This structure is maintained as a linked list of many
* receiver buffer pointers.
*/
typedef struct _RX_SW_PACKET {
/* Link to the next RX_SW_PACKET in the list */
struct _RX_SW_PACKET *next;
typedef struct _e1000g_msg_chain {
typedef struct _cksum_data {
} cksum_data_t;
/*
* MultiCast Command Block (MULTICAST_CB) The multicast
* structure contains an array of multicast addresses and
* also a count of the total number of addresses.
*/
typedef struct _multicast_cb_t {
} mltcst_cb_t, *pmltcst_cb_t;
typedef union _e1000g_ether_addr {
struct {
} reg;
struct {
} mac;
typedef struct _e1000gstat {
/*
* New Livengood Stat Counters
*/
/*
* Jumbo Frame Counters
*/
} e1000gstat, *e1000gstatp;
typedef struct _e1000g_tx_ring {
/*
* Descriptor queue definitions
*/
struct e1000_tx_desc *tbd_area;
struct e1000_tx_desc *tbd_first;
struct e1000_tx_desc *tbd_last;
struct e1000_tx_desc *tbd_oldest;
struct e1000_tx_desc *tbd_next;
/*
* Software packet structures definitions
*/
/*
*/
/*
* Timer definitions for 82547
*/
/*
* Pointer to the adapter
*/
typedef struct _e1000g_rx_ring {
/*
* Descriptor queue definitions
*/
struct e1000_rx_desc *rbd_area;
struct e1000_rx_desc *rbd_first;
struct e1000_rx_desc *rbd_last;
struct e1000_rx_desc *rbd_next;
/*
* Software packet structures definitions
*/
/*
* Pointer to the adapter
*/
typedef struct e1000g {
int AdapterInstance;
struct e1000g_osdep osdep;
#ifdef e1000g_DEBUG
#endif
/*
* The e1000g_timeout_lock must be held when updateing the
* timeout fields in struct e1000g, that is,
* WatchDogTimer_id, timeout_enabled, timeout_started.
*/
/*
* The e1000g_linklock protects the link fields in struct e1000g,
* such as link_state, link_speed, link_duplex, link_complete, and
* link_tid.
*/
/*
* stopped while other functions change the hardware
* configuration of e1000g card, such as e1000g_reset(),
* e1000g_reset_hw() etc are executed.
*/
int tx_softint_pri;
/*
* Message chain that needs to be freed
*/
/*
* reschedule when tx resource is available
*/
#ifdef __sparc
#endif
int intr_type;
int intr_cnt;
int intr_cap;
/*
* NDD parameters
*/
static ddi_dma_attr_t tx_dma_attr = {
DMA_ATTR_V0, /* version of this structure */
0, /* lowest usable address */
0xffffffffffffffffULL, /* highest usable address */
0x7fffffff, /* maximum DMAable byte count */
1, /* alignment in bytes */
0x7ff, /* burst sizes (any?) */
1, /* minimum transfer */
0xffffffffU, /* maximum transfer */
0xffffffffffffffffULL, /* maximum segment length */
16, /* maximum number of segments */
1, /* granularity */
0, /* flags (reserved) */
};
static ddi_dma_attr_t buf_dma_attr = {
DMA_ATTR_V0, /* version of this structure */
0, /* lowest usable address */
0xffffffffffffffffULL, /* highest usable address */
0x7fffffff, /* maximum DMAable byte count */
1, /* alignment in bytes */
0x7ff, /* burst sizes (any?) */
1, /* minimum transfer */
0xffffffffU, /* maximum transfer */
0xffffffffffffffffULL, /* maximum segment length */
1, /* maximum number of segments */
1, /* granularity */
0, /* flags (reserved) */
};
static ddi_dma_attr_t tbd_dma_attr = {
DMA_ATTR_V0, /* version of this structure */
0, /* lowest usable address */
0xffffffffffffffffULL, /* highest usable address */
0x7fffffff, /* maximum DMAable byte count */
E1000_MDALIGN, /* alignment in bytes 4K! */
0x7ff, /* burst sizes (any?) */
1, /* minimum transfer */
0xffffffffU, /* maximum transfer */
0xffffffffffffffffULL, /* maximum segment length */
1, /* maximum number of segments */
1, /* granularity */
0, /* flags (reserved) */
};
/*
* Function prototypes
*/
/*
* Global variables
*/
extern boolean_t e1000g_force_detach;
extern uint32_t e1000g_mblks_pending;
extern krwlock_t e1000g_rx_detach_lock;
#ifdef __cplusplus
}
#endif
#endif /* _E1000G_SW_H */