e1000g_sw.h revision ea6b684a18957883cb91b3d22a9d989f986e5a32
080575042aba2197b425ebfd52061dea061a9aa1xy * This file is provided under a CDDLv1 license. When using or
080575042aba2197b425ebfd52061dea061a9aa1xy * redistributing this file, you may do so under this license.
080575042aba2197b425ebfd52061dea061a9aa1xy * In redistributing this file this license must be included
080575042aba2197b425ebfd52061dea061a9aa1xy * and no other modification of this header file is permitted.
080575042aba2197b425ebfd52061dea061a9aa1xy * CDDL LICENSE SUMMARY
080575042aba2197b425ebfd52061dea061a9aa1xy * Copyright(c) 1999 - 2007 Intel Corporation. All rights reserved.
080575042aba2197b425ebfd52061dea061a9aa1xy * The contents of this file are subject to the terms of Version
080575042aba2197b425ebfd52061dea061a9aa1xy * 1.0 of the Common Development and Distribution License (the "License").
080575042aba2197b425ebfd52061dea061a9aa1xy * You should have received a copy of the License with this software.
080575042aba2197b425ebfd52061dea061a9aa1xy * You can obtain a copy of the License at
080575042aba2197b425ebfd52061dea061a9aa1xy * See the License for the specific language governing permissions
080575042aba2197b425ebfd52061dea061a9aa1xy * and limitations under the License.
080575042aba2197b425ebfd52061dea061a9aa1xy * Copyright 2007 Sun Microsystems, Inc. All rights reserved.
080575042aba2197b425ebfd52061dea061a9aa1xy * Use is subject to license terms of the CDDLv1.
080575042aba2197b425ebfd52061dea061a9aa1xy#pragma ident "%Z%%M% %I% %E% SMI"
080575042aba2197b425ebfd52061dea061a9aa1xyextern "C" {
080575042aba2197b425ebfd52061dea061a9aa1xy * **********************************************************************
080575042aba2197b425ebfd52061dea061a9aa1xy * Module Name: *
080575042aba2197b425ebfd52061dea061a9aa1xy * Abstract: *
080575042aba2197b425ebfd52061dea061a9aa1xy * This header file contains Software-related data structures *
080575042aba2197b425ebfd52061dea061a9aa1xy * definitions. *
080575042aba2197b425ebfd52061dea061a9aa1xy * **********************************************************************
080575042aba2197b425ebfd52061dea061a9aa1xy * constants used in setting flow control thresholds
080575042aba2197b425ebfd52061dea061a9aa1xy#define E1000_FC_HIGH_DIFF 0x1638 /* High: 5688 bytes below Rx FIFO size */
080575042aba2197b425ebfd52061dea061a9aa1xy#define E1000_FC_LOW_DIFF 0x1640 /* Low: 5696 bytes below Rx FIFO size */
25f2d433de915875c8393f0b0dc14aa155997ad0xy#define MIN_TX_BCOPY_THRESHOLD MINIMUM_ETHERNET_PACKET_SIZE
25f2d433de915875c8393f0b0dc14aa155997ad0xy#define DEFAULT_MASTER_LATENCY_TIMER 0 /* BIOS should decide */
080575042aba2197b425ebfd52061dea061a9aa1xy /* which is normally 0x040 */
25f2d433de915875c8393f0b0dc14aa155997ad0xy#define DEFAULT_TBI_COMPAT_ENABLE 1 /* Enable SBP workaround */
25f2d433de915875c8393f0b0dc14aa155997ad0xy#define TX_DRAIN_TIME (200) /* # milliseconds xmit drain */
080575042aba2197b425ebfd52061dea061a9aa1xy * The size of the receive/transmite buffers
080575042aba2197b425ebfd52061dea061a9aa1xy * definitions for smartspeed workaround
080575042aba2197b425ebfd52061dea061a9aa1xy#define E1000_SMARTSPEED_MAX 30 /* 30 watchdog iterations */
080575042aba2197b425ebfd52061dea061a9aa1xy /* or 30 seconds */
080575042aba2197b425ebfd52061dea061a9aa1xy#define E1000_SMARTSPEED_DOWNSHIFT 6 /* 6 watchdog iterations */
080575042aba2197b425ebfd52061dea061a9aa1xy /* or 6 seconds */
080575042aba2197b425ebfd52061dea061a9aa1xy * Definitions for module_info.
080575042aba2197b425ebfd52061dea061a9aa1xy * Defined for IP header alignment. We also need to preserve space for
080575042aba2197b425ebfd52061dea061a9aa1xy * VLAN tag (4 bytes)
080575042aba2197b425ebfd52061dea061a9aa1xy#define E1000G_IMS_TX_INTR (E1000_IMS_TXDW | E1000_IMS_TXQE)
080575042aba2197b425ebfd52061dea061a9aa1xy#define E1000G_ICR_TX_INTR (E1000_ICR_TXDW | E1000_ICR_TXQE)
080575042aba2197b425ebfd52061dea061a9aa1xy * bit flags for 'attach_progress' which is a member variable in struct e1000g
25f2d433de915875c8393f0b0dc14aa155997ad0xy#define ATTACH_PROGRESS_PCI_CONFIG 0x0001 /* PCI config setup */
25f2d433de915875c8393f0b0dc14aa155997ad0xy#define ATTACH_PROGRESS_REGS_MAP 0x0002 /* Registers mapped */
25f2d433de915875c8393f0b0dc14aa155997ad0xy#define ATTACH_PROGRESS_SETUP 0x0004 /* Setup driver parameters */
25f2d433de915875c8393f0b0dc14aa155997ad0xy#define ATTACH_PROGRESS_ADD_INTR 0x0008 /* Interrupt added */
25f2d433de915875c8393f0b0dc14aa155997ad0xy#define ATTACH_PROGRESS_LOCKS 0x0010 /* Locks initialized */
25f2d433de915875c8393f0b0dc14aa155997ad0xy#define ATTACH_PROGRESS_SOFT_INTR 0x0020 /* Soft interrupt added */
25f2d433de915875c8393f0b0dc14aa155997ad0xy#define ATTACH_PROGRESS_KSTATS 0x0040 /* Kstats created */
25f2d433de915875c8393f0b0dc14aa155997ad0xy#define ATTACH_PROGRESS_ALLOC 0x0080 /* DMA resources allocated */
25f2d433de915875c8393f0b0dc14aa155997ad0xy#define ATTACH_PROGRESS_INIT 0x0100 /* Driver initialization */
25f2d433de915875c8393f0b0dc14aa155997ad0xy#define ATTACH_PROGRESS_ENABLE_INTR 0x0800 /* DDI interrupts enabled */
080575042aba2197b425ebfd52061dea061a9aa1xy * Speed and Duplex Settings
080575042aba2197b425ebfd52061dea061a9aa1xy * Coexist Workaround RP: 07/04/03
080575042aba2197b425ebfd52061dea061a9aa1xy * 82544 Workaround : Co-existence
080575042aba2197b425ebfd52061dea061a9aa1xy * Defines for Jumbo Frame
25f2d433de915875c8393f0b0dc14aa155997ad0xy/* The sizes (in bytes) of a ethernet packet */
080575042aba2197b425ebfd52061dea061a9aa1xy/* Defines for Tx stall check */
080575042aba2197b425ebfd52061dea061a9aa1xy/* Defines for DVMA */
080575042aba2197b425ebfd52061dea061a9aa1xy * Loopback definitions
ea6b684a18957883cb91b3d22a9d989f986e5a32yy * Private dip list definitions
080575042aba2197b425ebfd52061dea061a9aa1xy * QUEUE_INIT_LIST -- Macro which will init ialize a queue to NULL.
080575042aba2197b425ebfd52061dea061a9aa1xy * IS_QUEUE_EMPTY -- Macro which checks to see if a queue is empty.
080575042aba2197b425ebfd52061dea061a9aa1xy * QUEUE_GET_HEAD -- Macro which returns the head of the queue, but does
080575042aba2197b425ebfd52061dea061a9aa1xy * not remove the head from the queue.
080575042aba2197b425ebfd52061dea061a9aa1xy#define QUEUE_GET_HEAD(_LH) ((PSINGLE_LIST_LINK)((_LH)->Flink))
080575042aba2197b425ebfd52061dea061a9aa1xy * QUEUE_REMOVE_HEAD -- Macro which removes the head of the head of a queue.
080575042aba2197b425ebfd52061dea061a9aa1xy * QUEUE_POP_HEAD -- Macro which will pop the head off of a queue (list),
080575042aba2197b425ebfd52061dea061a9aa1xy * and return it (this differs from QUEUE_REMOVE_HEAD only in
080575042aba2197b425ebfd52061dea061a9aa1xy * the 1st line).
080575042aba2197b425ebfd52061dea061a9aa1xy * QUEUE_GET_TAIL -- Macro which returns the tail of the queue, but does not
080575042aba2197b425ebfd52061dea061a9aa1xy * remove the tail from the queue.
080575042aba2197b425ebfd52061dea061a9aa1xy#define QUEUE_GET_TAIL(_LH) ((PSINGLE_LIST_LINK)((_LH)->Blink))
080575042aba2197b425ebfd52061dea061a9aa1xy * QUEUE_PUSH_TAIL -- Macro which puts an element at the tail (end) of the queue
080575042aba2197b425ebfd52061dea061a9aa1xy } else { \
080575042aba2197b425ebfd52061dea061a9aa1xy * QUEUE_PUSH_HEAD -- Macro which puts an element at the head of the queue.
080575042aba2197b425ebfd52061dea061a9aa1xy * QUEUE_GET_NEXT -- Macro which returns the next element linked to the
080575042aba2197b425ebfd52061dea061a9aa1xy * current element.
080575042aba2197b425ebfd52061dea061a9aa1xy * QUEUE_APPEND -- Macro which appends a queue to the tail of another queue
080575042aba2197b425ebfd52061dea061a9aa1xy } else { \
080575042aba2197b425ebfd52061dea061a9aa1xy * Property lookups
080575042aba2197b425ebfd52061dea061a9aa1xy#define E1000G_PROP_EXISTS(d, n) ddi_prop_exists(DDI_DEV_T_ANY, (d), \
080575042aba2197b425ebfd52061dea061a9aa1xy#define E1000G_PROP_GET_INT(d, n) ddi_prop_get_int(DDI_DEV_T_ANY, (d), \
080575042aba2197b425ebfd52061dea061a9aa1xy * Shorthand for the NDD parameters
080575042aba2197b425ebfd52061dea061a9aa1xy#define param_adv_autoneg nd_params[PARAM_ADV_AUTONEG_CAP].ndp_val
080575042aba2197b425ebfd52061dea061a9aa1xy#define param_adv_pause nd_params[PARAM_ADV_PAUSE_CAP].ndp_val
080575042aba2197b425ebfd52061dea061a9aa1xy#define param_adv_asym_pause nd_params[PARAM_ADV_ASYM_PAUSE_CAP].ndp_val
080575042aba2197b425ebfd52061dea061a9aa1xy#define param_adv_1000fdx nd_params[PARAM_ADV_1000FDX_CAP].ndp_val
080575042aba2197b425ebfd52061dea061a9aa1xy#define param_adv_1000hdx nd_params[PARAM_ADV_1000HDX_CAP].ndp_val
080575042aba2197b425ebfd52061dea061a9aa1xy#define param_adv_100fdx nd_params[PARAM_ADV_100FDX_CAP].ndp_val
080575042aba2197b425ebfd52061dea061a9aa1xy#define param_adv_100hdx nd_params[PARAM_ADV_100HDX_CAP].ndp_val
080575042aba2197b425ebfd52061dea061a9aa1xy#define param_adv_10fdx nd_params[PARAM_ADV_10FDX_CAP].ndp_val
080575042aba2197b425ebfd52061dea061a9aa1xy#define param_adv_10hdx nd_params[PARAM_ADV_10HDX_CAP].ndp_val
080575042aba2197b425ebfd52061dea061a9aa1xy#define param_force_speed_duplex nd_params[PARAM_FORCE_SPEED_DUPLEX].ndp_val
080575042aba2197b425ebfd52061dea061a9aa1xy * E1000G-specific ioctls ...
080575042aba2197b425ebfd52061dea061a9aa1xy * These diagnostic IOCTLS are enabled only in DEBUG drivers
080575042aba2197b425ebfd52061dea061a9aa1xy#define E1000G_PP_SPACE_E1000G 1 /* driver's soft state */
080575042aba2197b425ebfd52061dea061a9aa1xytypedef struct {
080575042aba2197b425ebfd52061dea061a9aa1xy /* input for poke */
25f2d433de915875c8393f0b0dc14aa155997ad0xy#endif /* E1000G_DEBUG */
080575042aba2197b425ebfd52061dea061a9aa1xy * (Internal) return values from ioctl subroutines
080575042aba2197b425ebfd52061dea061a9aa1xy * Named Data (ND) Parameter Management Structure
080575042aba2197b425ebfd52061dea061a9aa1xytypedef struct {
080575042aba2197b425ebfd52061dea061a9aa1xy * NDD parameter indexes, divided into:
080575042aba2197b425ebfd52061dea061a9aa1xy * read-only parameters describing the hardware's capabilities
080575042aba2197b425ebfd52061dea061a9aa1xy * read-write parameters controlling the advertised capabilities
080575042aba2197b425ebfd52061dea061a9aa1xy * read-only parameters describing the partner's capabilities
080575042aba2197b425ebfd52061dea061a9aa1xy * read-write parameters controlling the force speed and duplex
080575042aba2197b425ebfd52061dea061a9aa1xy * read-only parameters describing the link state
080575042aba2197b425ebfd52061dea061a9aa1xy * read-only parameters describing the driver properties
080575042aba2197b425ebfd52061dea061a9aa1xy * read-write parameters controlling the driver properties
ea6b684a18957883cb91b3d22a9d989f986e5a32yy * The entry of the private dip list
0f70fbf80d71251e7928b3122fb4848c2f92a5c6xytypedef struct _private_devi_list {
080575042aba2197b425ebfd52061dea061a9aa1xy * A structure that points to the next entry in the queue.
080575042aba2197b425ebfd52061dea061a9aa1xytypedef struct _SINGLE_LIST_LINK {
080575042aba2197b425ebfd52061dea061a9aa1xy * A "ListHead" structure that points to the head and tail of a queue
080575042aba2197b425ebfd52061dea061a9aa1xytypedef struct _LIST_DESCRIBER {
080575042aba2197b425ebfd52061dea061a9aa1xy * Address-Length pair structure that stores descriptor info
25f2d433de915875c8393f0b0dc14aa155997ad0xytypedef struct _sw_desc {
25f2d433de915875c8393f0b0dc14aa155997ad0xytypedef struct _desc_array {
080575042aba2197b425ebfd52061dea061a9aa1xytypedef enum {
080575042aba2197b425ebfd52061dea061a9aa1xytypedef struct _dma_buffer {
080575042aba2197b425ebfd52061dea061a9aa1xy * Transmit Control Block (TCB), Ndis equiv of SWPacket This
080575042aba2197b425ebfd52061dea061a9aa1xy * structure stores the additional information that is
080575042aba2197b425ebfd52061dea061a9aa1xy * associated with every packet to be transmitted. It stores the
080575042aba2197b425ebfd52061dea061a9aa1xy * message block pointer and the TBD addresses associated with
080575042aba2197b425ebfd52061dea061a9aa1xy * the m_blk and also the link to the next tcb in the chain
25f2d433de915875c8393f0b0dc14aa155997ad0xytypedef struct _tx_sw_packet {
25f2d433de915875c8393f0b0dc14aa155997ad0xy /* Link to the next tx_sw_packet in the list */
25f2d433de915875c8393f0b0dc14aa155997ad0xy * This structure is similar to the rx_sw_packet structure used
080575042aba2197b425ebfd52061dea061a9aa1xy * for Ndis. This structure stores information about the 2k
080575042aba2197b425ebfd52061dea061a9aa1xy * aligned receive buffer into which the FX1000 DMA's frames.
080575042aba2197b425ebfd52061dea061a9aa1xy * This structure is maintained as a linked list of many
080575042aba2197b425ebfd52061dea061a9aa1xy * receiver buffer pointers.
ea6b684a18957883cb91b3d22a9d989f986e5a32yytypedef struct _rx_sw_packet {
25f2d433de915875c8393f0b0dc14aa155997ad0xy /* Link to the next rx_sw_packet_t in the list */
25f2d433de915875c8393f0b0dc14aa155997ad0xytypedef struct _mblk_list {
7941757c1241fe30e30f921910595c8ac6af9ef1xytypedef struct _cksum_data {
080575042aba2197b425ebfd52061dea061a9aa1xytypedef union _e1000g_ether_addr {
25f2d433de915875c8393f0b0dc14aa155997ad0xytypedef struct _e1000g_stat {
080575042aba2197b425ebfd52061dea061a9aa1xy kstat_named_t rx_exceed_pkt; /* Rx Exceed Max Pkt Count */
080575042aba2197b425ebfd52061dea061a9aa1xy kstat_named_t rx_esballoc_fail; /* Rx Desballoc Failure */
25f2d433de915875c8393f0b0dc14aa155997ad0xy kstat_named_t rx_avail_freepkt; /* Rx Freelist Avail Buffers */
080575042aba2197b425ebfd52061dea061a9aa1xy kstat_named_t tx_multi_copy; /* Tx Copy Multi Fragments */
25f2d433de915875c8393f0b0dc14aa155997ad0xy kstat_named_t tx_multi_cookie; /* Tx Pkt Span Multi Cookies */
080575042aba2197b425ebfd52061dea061a9aa1xy kstat_named_t Fcruc; /* Unknown Flow Conrol Packet Rcvd Count */
080575042aba2197b425ebfd52061dea061a9aa1xy kstat_named_t Prc1023; /* Packets Received - 511-1023b */
080575042aba2197b425ebfd52061dea061a9aa1xy kstat_named_t Prc1522; /* Packets Received - 1024-1522b */
080575042aba2197b425ebfd52061dea061a9aa1xy kstat_named_t Cexterr; /* Carrier Extension Error count */
080575042aba2197b425ebfd52061dea061a9aa1xy kstat_named_t Tsctfc; /* TCP seg contexts xmit fail count */
080575042aba2197b425ebfd52061dea061a9aa1xytypedef struct _e1000g_tx_ring {
080575042aba2197b425ebfd52061dea061a9aa1xy * Descriptor queue definitions
080575042aba2197b425ebfd52061dea061a9aa1xy * Software packet structures definitions
080575042aba2197b425ebfd52061dea061a9aa1xy * TCP/UDP checksum offload
080575042aba2197b425ebfd52061dea061a9aa1xy * Timer definitions for 82547
25f2d433de915875c8393f0b0dc14aa155997ad0xy * reschedule when tx resource is available
25f2d433de915875c8393f0b0dc14aa155997ad0xy * Statistics
080575042aba2197b425ebfd52061dea061a9aa1xy * Pointer to the adapter
080575042aba2197b425ebfd52061dea061a9aa1xytypedef struct _e1000g_rx_ring {
080575042aba2197b425ebfd52061dea061a9aa1xy * Descriptor queue definitions
080575042aba2197b425ebfd52061dea061a9aa1xy * Software packet structures definitions
25f2d433de915875c8393f0b0dc14aa155997ad0xy * Statistics
080575042aba2197b425ebfd52061dea061a9aa1xy * Pointer to the adapter
080575042aba2197b425ebfd52061dea061a9aa1xytypedef struct e1000g {
25f2d433de915875c8393f0b0dc14aa155997ad0xy * The watchdog_lock must be held when updateing the
080575042aba2197b425ebfd52061dea061a9aa1xy * timeout fields in struct e1000g, that is,
25f2d433de915875c8393f0b0dc14aa155997ad0xy * watchdog_tid, watchdog_timer_started.
25f2d433de915875c8393f0b0dc14aa155997ad0xy * The link_lock protects the link fields in struct e1000g,
7941757c1241fe30e30f921910595c8ac6af9ef1xy * such as link_state, link_speed, link_duplex, link_complete, and
7941757c1241fe30e30f921910595c8ac6af9ef1xy * link_tid.
080575042aba2197b425ebfd52061dea061a9aa1xy * The chip_lock assures that the Rx/Tx process must be
080575042aba2197b425ebfd52061dea061a9aa1xy * stopped while other functions change the hardware
080575042aba2197b425ebfd52061dea061a9aa1xy * configuration of e1000g card, such as e1000g_reset(),
080575042aba2197b425ebfd52061dea061a9aa1xy * e1000g_reset_hw() etc are executed.
080575042aba2197b425ebfd52061dea061a9aa1xy e1000g_ether_addr_t unicst_addr[MAX_NUM_UNICAST_ADDRESSES];
080575042aba2197b425ebfd52061dea061a9aa1xy struct ether_addr mcast_table[MAX_NUM_MULTICAST_ADDRESSES];
080575042aba2197b425ebfd52061dea061a9aa1xy * NDD parameters
080575042aba2197b425ebfd52061dea061a9aa1xy * Function prototypes
080575042aba2197b425ebfd52061dea061a9aa1xyvoid e1000g_release_dma_resources(struct e1000g *Adapter);
25f2d433de915875c8393f0b0dc14aa155997ad0xyuint_t e1000g_tx_softint_worker(caddr_t arg1, caddr_t arg2);
080575042aba2197b425ebfd52061dea061a9aa1xyvoid phy_spd_state(struct e1000_hw *hw, boolean_t enable);
25f2d433de915875c8393f0b0dc14aa155997ad0xy#pragma inline(e1000_rar_set)
080575042aba2197b425ebfd52061dea061a9aa1xy * Global variables
080575042aba2197b425ebfd52061dea061a9aa1xy#endif /* _E1000G_SW_H */